DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to the Applicant’s amendment/request for reconsideration after non-final rejection and IDS filed on 3/4/2026. Claims 1-20 are pending, wherein claims 6, 9, 16, 19, 20 have been amended.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of U.S. Patent No. 12,518,130 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are obvious variations of each other, reciting similar components, similar interconnections among components, and performing similar operations of fetching a portion of the structure data of the graph; perform node sampling using the fetched portion of the structure data to select one or more sampled nodes; fetching a portion of the attribute data of the graph according to the selected one or more sampled nodes; and sending the fetched portion of the attribute data of the graph; except that
(1) In the patented claims, the system comprises a plurality of processing units, each configured to perform graph neural network (GNN) processing, whereas in the present claims, the system comprises a host, which comprises one or more processors configured to perform graph neural network (GNN) processing for the graph using the portion of the attribute data of the graph, which is an obvious subset of the plurality of processing units of the patented claims;
(2) In the patented claims, the system comprises a plurality of memory extension cards, each configured to store the graph data for the GNN processing, whereas in the present claims, the system comprises a circuitry board, which comprise a plurality of memory drives configured to store structure data of a graph and attribute data of the graph, wherein the plurality of memory drives include flash drives, which are obvious variations of the plurality of memory cards of the patented claims as known in the art, and further used for performing similar GNN processing;
(3) In the patented claims, each of the plurality of processing units is communicatively coupled with three other processing units via one or more interconnects respectively and the plurality of processing units are communicatively coupled with the plurality of memory extension cards respectively, whereas in the present claims, the host, which comprise one or more processors which are obvious variations of the patented “plurality processing units”, is communicatively coupled with the circuitry board (which comprises the plurality of memory drives including flash drives), which are similarly interconnected with the memory (i.e., plurality of memory drives instead of plurality of memory cards of the patented claims);
(4) In the patented claims, the system further comprises graphic engine circuitry, communicatively coupled to the plurality of memory extension cards, which are used to perform the recited operations, whereas in the present claims, the system comprises the circuit board which comprises the access engine circuitry which are similarly communicatively coupled to the plurality of memory drive, to perform the recited operations, which are obvious variations of each other because they recite similar obvious components, interconnected to similar components, to perform similar operations;
(5) In the patented claims, the portion of structure data and attribute data of the graph is fetched from one or more of the memory cards, whereas in the present claims, the portion of the structure data and attribute data of the graph is fetched from one or more of the plurality of memory drives, which are obvious variations of each other, performing similar operations with similar memory types as discussed above;
(6) In the patented claims, the fetched portion of the attribute data of the graph is sent to the one or more of the processing units, wherein the present claims, the fetched portion of the attribute data of the graph is sent to the host which comprises which one or more processors, performing similar operations and sending to similar processing unit(s);
(7) In the present claims, the further operation of performing graph neural network (GNN) processing, using one or more processors, for the graph using the portion of the attribute data of the graph, is intended by the patented claims which recites the plurality of processing units (obvious variations of the “one or more processors” of the present claims) to perform neural network (GNN) processing.
(8) Per present claims 11-19 and 20, the claims are directed to a computer-implemented method and a non-transitory computer-readable storage medium, respectively, performing the similar method/operations, whereas the patented claims are directed to a system performing the similar method/operations as discussed above. It would have been obvious to one of ordinary skilled in the art at the time of the effective filing data of the invention, to derive the method and/or non-transitory computer medium performing the method, from the system and vice versa, because such method, non-transitory computer medium, system are known in the art of computer-aided design and analysis of circuits and computer data processing, for implementing the computer-implemented method.
Furthermore, it would have been obvious to one of ordinary skilled in the art at the time of the effective filing date of the inventions, to derive the operations of the patented claims to arrive at the claims of the present claims or vice versa, because these operations are performed on similar processing unit(s), memories, and similar interconnections among the components as discussed above.
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Terminal Disclaimer
The terminal disclaimer filed on 3/4/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US Patent No. 12/332,828 B2, has been reviewed and is accepted. The terminal disclaimer has been recorded.
Allowable Subject Matter
Claims 1-20 would be allowable if the non-statutory obviousness rejection(s) under 35 U.S.C. 101, set forth in this Office action, are overcome.
The following is a statement of reasons for the indication of allowable subject matter:
As per claims 1-20, as previously indicated, the independent claims 1, 11 and 20, from which the respective claims depend, recite the system/computer-implemented method/non-transitory computer readable medium comprising a combination of inventive operations/steps performed by the access engine circuitry of the circuit board, comprising: performing node sampling using the fetched portion of the structure data to select one or more sampled nodes; fetching a portion of the attribute data of the graph according to the selected one or more sampled nodes; and sending the fetched portion of the attribute data of the graph to one or more processors to perform graph neural network (GNN) processing for the graph using the portion of the attribute data of the graph, as claimed, which the prior arts made of record failed to teach or suggest as claimed. Furthermore, under the 2019 Patent Eligibility Guideline, the claims are directed to patent eligible subject matter because (1) under Step 1, the claims are directed to a process, article of manufacture and machine, respectively; (2) under Step 2A, Prong One, the claims are not directed to mathematical concepts comprising mathematical relationships, mathematical formulas or equations, and mathematical calculations since no expressed equation or formula is recited in the claims; nor are the claims directed to a mental process since one of ordinary skilled in the art at the time of the filing of the invention, would NOT reasonably be able to perform the method mentally since the calculations would involve large amount of data associated with structure data of the graph, as normally found in the art of computer-aided design and analysis of circuits and computer data processing; nor are the claims directed to certain methods of organizing human activity.
Remarks
The rejections of claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No.12,332,828 B2, are withdrawn in light of the TD filed on 3/4/2026 which has been approved.
Claims 1-20 are newly rejected under on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of U.S. Patent No. 12,518,130 B2 as a result of the updated search.
Conclusion
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Any response to this action should be mailed to:
Commissioner for Patents
P. O. Box 1450
Alexandria, VA 22313-1450
or faxed to:
571-273-8300
/PHALLAKA KIK/Primary Examiner, Art Unit 2851 June 18, 2026
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