Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/17/2025 has been entered.
Drawings Objection Withdrawal
Applicant’s amendment of Claims 1 and 12 is acknowledged. Thus, the objection to drawings is withdrawn.
Claim Rejections Withdrawal
Applicant’s amendment of Claims 1 and 12 is acknowledged. Thus, the rejection under 35 U.S.C. 112(a) is withdrawn.
Claim Rejections – 35 U.S.C. 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 1 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimoyama (JP 2010123783, machine-translation provided).
Regarding Claim 1
FIG. 4 of Shimoyama discloses a structure comprising: a transistor comprising a gate structure (24), a source region (12) and a drain region (21), the transistor on a substrate comprising an active region (under 24) and an N-well (15), wherein a portion of the N-well extends directly underneath the active region, the source region, and the drain region; and a first gate-protecting line at a first wiring level above the substrate, the first gate-protecting line comprising a first portion (above 26) and a second portion (above 16), the second portion not forming a circuit with the first portion and the transistor, the first portion connecting to the gate structure of the transistor and the second portion connecting to the N-well, wherein the second portion of the first gate-protecting line directly contacts the N-well.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 2 rejected under 35 U.S.C. 103 as being unpatentable over Chen (U.S. Patent Pub. No. 2002/0155680) of record, in view of Chang (U.S. Patent Pub. No. 2016/0365410).
Regarding Claim 1
FIG. 11 of Chen discloses a structure comprising: a transistor comprising a gate structure (46), a source region (52) and a drain region (52), the transistor on a substrate (40) comprising an active region and an N-well (50); and a first gate-protecting line (66) at a first wiring level above the substrate, the first gate-protecting line comprising a first portion and a second portion, the second portion not forming a circuit with the first portion and the transistor (isolated by 68), the first portion connecting to the gate structure of the transistor and the second portion connecting to the N-well of the substrate [0021] , wherein the second portion of the first gate-protecting line directly contacts the N-well.
Chen is silent with respect to “a portion of the N-well extends directly underneath the active region, the source region, and the drain region”.
FIG. 2 of Chang discloses a similar structure, comprising an N-well (205), wherein a portion of the N-well extends directly underneath the active region, the source region (257), and the drain region (256).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Noguchi, as taught by Chang. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of improving drain-source current-voltage characteristics ([0044] of Chang).
Regarding Claim 2
FIG. 11 of Chen discloses the first gate-protecting line (66) comprises a metal [0021] wiring structure on a first wiring level.
Claim 1 rejected under 35 U.S.C. 103 as being unpatentable over Pan (U.S. Patent No. 8,890,164), in view of Fan (CN 208722886, machine-translation provided), in view of Gelsomini (U.S. Patent Pub. No. 2003/0207526)
Regarding Claim 1
FIG. 2 of Pan discloses a structure comprising: a transistor comprising a gate structure (113), a source region (105) and a drain region (107), the transistor on a substrate (40) comprising an active region and an N-well (103), wherein a portion of the N-well extends directly underneath the active region, the source region, and the drain region; and a first gate-protecting line (66) at a first wiring level above the substrate, the first gate-protecting line comprising a second portion (203), the second portion connecting to the N-well of the substrate, wherein the second portion of the first gate-protecting line directly contacts the N-well.
Pan is silent with respect to “the first gate-protecting line comprising a first portion”; “the second portion not forming a circuit with the first portion and the transistor, the first portion connecting to the gate structure of the transistor” and “the second portion of the first gate-protecting line directly contacts the N-well”.
FIG. 3 of Fan discloses a similar structure, comprising an N-well (31), wherein a portion of the N-well extends directly underneath the active region (between 37 and 40), the source region (40), and the drain region (37); and a first gate-protecting line at a first wiring level above the substrate, the first gate-protecting line comprising a first portion (connecting 33) and a second portion (connecting 37), the second portion not forming a circuit with the first portion and the transistor, the first portion connecting to the gate structure of the transistor and the second portion connecting to the N-well.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Pan, as taught by Fan. The ordinary artisan would have been motivated to modify Pan in the above manner for purpose of improving compatibility and reliability (Abstract of Fan).
Pan as modified by Fan is silent with respect to “the second portion of the first gate-protecting line directly contacts the N-well”.
FIG. 3 of Gelsomini discloses a similar structure, comprising an N-well (203), wherein a portion of the N-well extends directly underneath the active region (under 209), the source region (307), and the drain region (307); wherein the second portion (204) of the first gate-protecting line directly contacts the N-well.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Pan, as taught by Gelsomini. The ordinary artisan would have been motivated to modify Pan in the above manner for purpose of improving device reliability ([0009] of Gelsomini).
Claims 4, 5, 7-9, 12, 17 and 19 rejected under 35 U.S.C. 103 as being unpatentable over Shimoyama, in view of Beatly (U.S. Patent No. 6,034,433) of record.
Regarding Claim 4
Shimoyama discloses Claim 1.
Shimoyama is silent with respect to “a second gate-protecting line at a second wiring level above the first wiring level, the second gate-protecting line comprising a first portion and a second portion, the second portion of the second gate-protecting line being electrically isolated from the first portion of the second gate-protecting line and from the transistor, the first portion of the second gate-protecting line connecting to the first portion of the first gate-protecting line and the second portion of the second gate-protecting line connecting to the second portion of the first gate-protecting line gate structure of the transistor and the substrate”.
FIG. 2 of Beatly discloses a similar structure, comprising a second gate-protecting line at a second wiring level above the first wiring level, the second gate-protecting line comprising a first portion (111) and a second portion (119), the second portion of the second gate-protecting line being electrically isolated from the first portion of the second gate-protecting line and from the transistor (100), the first portion of the second gate-protecting line connecting to the first portion (110) of the first gate-protecting line and the second portion of the second gate-protecting line connecting to the second portion (118) of the first gate-protecting line gate structure of the transistor and the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Shimoyama, as taught by Beatly. The ordinary artisan would have been motivated to modify Shimoyama in the above manner for purpose of preventing charge damage to a protected structure during processing of a semiconductor device (Abstract of Beatly).
Regarding Claim 5
Beatly discloses the second gate-protecting line (111/119) comprises a metal wiring structure on a wiring level above the first wiring level (Col. 4, Lines 11-20).
Regarding Claim 7
FIG. 2B of Beatly discloses a third gate-protecting line at a third wiring level above the second wiring level, the third gate-protecting line comprising a first portion (112) and a second portion (120), the second portion of the third gate-protecting line being not forming a circuit with the first portion of the third gate-protecting line and from the transistor (100), the first portion of the third gate-protecting line connecting to the first portion of the second gate-protecting-line and the second portion of the third gate-protecting line connecting to the second portion of the second gate-protecting-line.
Regarding Claim 8
FIG. 2B of Beatly discloses the second gate-protecting line includes a cut which breaks a connection between the gate structure and the substrate.
Regarding Claim 9
FIG. 2B of Beatly discloses the third gate-protecting line (116) comprises a metal wiring structure.
Regarding Claim 12
FIG. 4 of Shimoyama discloses a structure comprising: comprising a gate structure (24) of a transistor on a substrate comprising a source region (12) and a drain region (21), the gate structure disposed on a substrate (15) comprising an active region (under 24) and an N-well (15) having a portion that extends directly underneath the active region, the source region, and the drain region; a first gate-protecting line at a first wiring level above the transistor, the first gate-protecting line comprising a first portion (above 26) and a second portion (above 16), the second portion not forming a circuit with the first portion and from the transistor, the first portion connecting to the gate structure of the transistor and the second portion connecting directly to the substrate; and a second gate-protecting line at a second wiring level above the first wiring level, the second gate-protecting line comprising a first portion and a second portion, the second portion of the second gate-protecting line not forming a circuit with the first portion of the second gate-protecting line portion and from the transistor, the first portion of the second gate-protecting line connecting to the first portion of the first gate-protecting line and the second portion connecting directly to the substrate.
Shimoyama is silent with respect to “a second gate-protecting line at a second wiring level above the first wiring level, the second gate-protecting line comprising a first portion and a second portion, the second portion of the second gate-protecting line not forming a circuit with the first portion of the second gate-protecting line portion and from the transistor, the first portion of the second gate-protecting line connecting to the first portion of the first gate-protecting line and the second portion of the second gate-protecting line connecting to the second portion of the first gate-protecting line gate structure of the transistor and the substrate”.
FIG. 2 of Beatly discloses a similar structure, comprising a first gate-protecting line at a first wiring level above the transistor, the first gate-protecting line comprising a first portion (110) and a second portion (118), the second portion being electrically isolated from the first portion and from the transistor (100), the first portion connecting to the gate structure of the transistor and the second portion connecting directly to the substrate (150) and includes a cut which breaks any connection between the gate structure and the substrate; and a second gate-protecting line at a second wiring level above the first wiring level, the second gate-protecting line comprising a first portion (111) and a second portion (119), the second portion of the second gate-protecting line not forming a circuit with the first portion of the second gate-protecting line portion and from the transistor, the first portion of the second gate-protecting line connecting to the first portion of the first gate-protecting line and the second portion of the second gate-protecting line connecting to the second portion of the first gate-protecting line gate structure of the transistor and the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Shimoyama, as taught by Beatly. The ordinary artisan would have been motivated to modify Shimoyama in the above manner for purpose of preventing charge damage to a protected structure during processing of a semiconductor device Abstract of Beatly).
Regarding Claim 17
FIG. 2b of Beatly discloses the first gate-protecting line and the second gate-protecting line each comprise a metal wiring structure which do not form a circuit with one another.
Regarding Claim 19
FIG. 2b of Beatly discloses the first gate-protecting line and the second gate-protecting line are at back end of the line wiring levels.
Claims 10-16 rejected under 35 U.S.C. 103 as being unpatentable over Shimoyama, in view of Beatly, in view of Wilford (U.S. Patent No. 6,433,403) of record.
Regarding Claim 10
Shimoyama discloses Claim 1.
Shimoyama is silent with respect to “a top metal line disposed above the first wiring level, the top metal line electrically connecting to the first portion of the first gate-protecting line and a tie down device within the substrate connected to a wiring level above the first gate-protecting line”.
FIG. 2 of Beatly discloses a similar structure, comprising a top metal line disposed above the first wiring level, the top metal line electrically connecting to the first portion of the first gate-protecting line.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Shimoyama, as taught by Beatly. The ordinary artisan would have been motivated to modify Shimoyama in the above manner for purpose of preventing charge damage to a protected structure during processing of a semiconductor device Abstract of Beatly).
Shimoyama as modified by Beatly is silent with respect to “a tie down device within the substrate connected to a wiring level above the first gate-protecting line”.
FIG. 4 of Wilford discloses a similar structure, comprising a tie down device (104) within the substrate (12) connected to a wiring level above the first gate-protecting line.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Shimoyama, as taught by Wilford. The ordinary artisan would have been motivated to modify Shimoyama in the above manner for purpose of preventing ESD damage (Col. 2, Lines 15-18 of Wilford).
Regarding Claim 11
FIG. 4 of Wilford discloses the tie down device is provided in the N-well (72).
Regarding Claim 13
FIG. 4 of Wilford discloses a tie down device connected to a top metal line disposed above the first wiring level and the second wiring level, the top metal line being connected to the first portion of the first gate-protecting line.
Regarding Claim 14
The claim “the tie down device provides electrostatic discharge protection (ESD) to the first gate-protecting line” containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Shimoyama teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Regarding Claim 15
FIG. 4 of Wilford discloses the tie down device is provided in a local N-well in the substrate.
Regarding Claim 16
FIG. 2 of Beatly discloses the top metal line is directly connected to the first portion of the second gate-protecting line and the first portion of the second gate-protecting line is directly connected to the first portion of the first second gate-protecting line.
Claim 12 rejected under 35 U.S.C. 103 as being unpatentable over Shimoyama, in view of Chang, in view of Beatly.
Regarding Claim 12
FIG. 11 of Chen discloses a structure comprising: a gate structure (46) of a transistor on a substrate (40); a first gate-protecting line (66) at a first wiring level above the transistor, the first gate-protecting line comprising a first portion and a second portion, the second portion being electrically isolated (isolated by 68) from the first portion and from the transistor, the first portion connecting to the gate structure of the transistor and the second portion connecting directly to the substrate and includes a cut which breaks any connection between the gate structure and the substrate.
Chen is silent with respect to “an N-well having a portion that extends directly underneath the active region, the source region, and the drain region” and “a second gate-protecting line at a second wiring level above the first wiring level, the second gate-protecting line comprising a first portion and a second portion, the second portion of the second gate-protecting line being electrically isolated from the first portion of the second gate-protecting line portion and from the transistor, the first portion of the second gate-protecting line connecting to the first portion of the first gate-protecting line and the second portion of the second gate-protecting line connecting to the second portion of the first gate-protecting line gate structure of the transistor and the substrate”.
FIG. 2 of Chang discloses a similar structure, comprising an N-well (205), wherein a portion of the N-well extends directly underneath the active region, the source region (257), and the drain region (256).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Noguchi, as taught by Chang. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of improving drain-source current-voltage characteristics ([0044] of Chang).
Chen as modified by Chang is silent with respect to “a second gate-protecting line at a second wiring level above the first wiring level, the second gate-protecting line comprising a first portion and a second portion, the second portion of the second gate-protecting line being electrically isolated from the first portion of the second gate-protecting line portion and from the transistor, the first portion of the second gate-protecting line connecting to the first portion of the first gate-protecting line and the second portion of the second gate-protecting line connecting to the second portion of the first gate-protecting line gate structure of the transistor and the substrate”.
FIG. 2 of Beatly discloses a similar structure, comprising a first gate-protecting line at a first wiring level above the transistor, the first gate-protecting line comprising a first portion (110) and a second portion (118), the second portion being electrically isolated from the first portion and from the transistor (100), the first portion connecting to the gate structure of the transistor and the second portion connecting directly to the substrate (150) and includes a cut which breaks any connection between the gate structure and the substrate; and a second gate-protecting line at a second wiring level above the first wiring level, the second gate-protecting line comprising a first portion (111) and a second portion (119), the second portion of the second gate-protecting line being electrically isolated from the first portion of the second gate-protecting line portion and from the transistor, the first portion of the second gate-protecting line connecting to the first portion of the first gate-protecting line and the second portion of the second gate-protecting line connecting to the second portion of the first gate-protecting line gate structure of the transistor and the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chen, as taught by Beatly. The ordinary artisan would have been motivated to modify Chen in the above manner for purpose of preventing charge damage to a protected structure during processing of a semiconductor device Abstract of Beatly).
Pertinent Art
Xu (CN 107393908) discloses an N-well (NW), wherein a portion of the N-well extends directly underneath the active region, the source region, and the drain region; and a first gate-protecting line at a first wiring level above the substrate, the first gate-protecting line comprising a first portion and a second portion, the second portion not forming a circuit with the first portion and the transistor (separated by fuse 401), the first portion connecting to the gate structure of the transistor and the second portion connecting to the N-well. Zhuang (CN 104464816) discloses an N-well (76), wherein a portion of the N-well extends directly underneath the active region, the source region (172), and the drain region (174); and a first gate-protecting line at a first wiring level above the substrate, the first gate-protecting line comprising a first portion (WLRB) and a second portion (WLPB), the second portion not forming a circuit with the first portion and the transistor, the first portion connecting to the gate structure of the transistor and the second portion connecting to the N-well. Han (CN 112151620) discloses an N-well (11), wherein a portion of the N-well extends directly underneath the active region, the source region (14), and the drain region (12). Zheng (U.S. Patent Pub. No. 20030201819) discloses an N-well (220), wherein a portion of the N-well extends directly underneath the active region, the source region (224), and the drain region (226). US 6060347 discloses the second portion of the first gate-protecting line directly contacts the N-well. Pertinent art also includes US 6537883 and 6013927; and Miyata (JP 3075892).
Response to Arguments
Applicant’s arguments with respect to Claims 1 and 12 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897