Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed 1/12/2026 have been entered and considered. The amendments to claims 1, 3, and 6, and the amendment to the specification are acknowledged.
In view of the amendment to claim 1, the objection to the claim has been withdrawn.
In view of the amendments to claims 1, 3, and 6, the rejections under 35 U.S.C. 112 have been withdrawn.
Though the examiner notes that amended figures were indicated presented by the applicant, no figures are present in the reply of 1/12/2026 and the drawing objections are sustained.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the at least one bonding pad per copper pillar electrically connected to its corresponding pillar in claim 1 and the bond pads now being operably placed on the last additional package layer formed in claim 3 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. US 20210057362 A1 (hereinafter referred to as Chen).
Regarding claim 1, Chen teaches
A method of producing a Package-Level Chip Scale Package (“package 10” para. 0041 FIG. 1A-1K) comprising
Taking a wafer (“wafer substrate WS” para. 0010);
Forming at least one die on a surface of the wafer (“wafer substrate WS may include active components (e.g., transistors or the like) and/or passive components (e.g., resistors, capacitors, inductors, or the like)” para. 0011, such that the examiner understands that at least some portions of “wafer substrate WS” are considered die.);
Forming an intermediary layer on a surface of the die (“first interconnection structure 120” and “first bonding structure 130” para. 0012 FIG. 1A-1B);
Forming at least one conductive pillar on the intermediary layer (“through insulating vias (TIV) 300” para. 0028 FIG. 1D);
Depositing an epoxy plastic over the conductive pillar layer to a thickness exceeding the height of the conductive pillar (“first encapsulant material 400a′” made of epoxy resin, para. 0031 FIG. 1E);
Grinding excess epoxy plastic to expose an upper surface of the conductive pillar (“first encapsulant material 400a′, the TIVs 300, and the semiconductor dies 200 are thinned until the TIVs 300 and the TSVs 212 are both exposed” para. 0032 FIG. 1F);
After grinding, forming at least one bonding pad on an exposed upper surface of at least one conductive pillar (“under-ball metallurgy (UBM) patterns 600” para. 0037 FIG. 1J), each bonding pad being electrically connected to its corresponding pillar (as shown in FIG. 1J, each “TTV 300” is in electrical contact with a “UBM pattern 600”, para. 0037); and
Singulating the packaged die (“a singulation process is performed to form a plurality of packages 10” para. 0040 FIG. 1K).
Regarding claim 2, Chen teaches the method of claim 1, wherein the bond pads are not spaced more than 0.15mm apart from each other (“two adjacent UBM patterns 600 may have a pitch ranging between about 100 μm and about 1000 μm” Para. 0038).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, in view of Yu et al. US 20180053746 A1 (hereinafter referred to as Yu).
Regarding claim 3, Chen, teaches the method of claim 1 but fails to teach further comprising forming at least one additional package layer after grinding, the bond pads being operably placed on the last additional package layer formed.
Nevertheless, Yu teaches
further comprising forming at least one additional package layer (layer with “semiconductor die 370 and semiconductor die 380”, “TEM chip 110”, “vias 379”, and “RDL 390”, para. 0060,0062, and 0064 FIG. 17) after grinding (“second molding layer 348 may be cured after being deposited, and may further undergo a planarization process” before “RDL 350” and “third molding layer 388” are formed, para. 0059 FIG. 13), the bond pads (“UBM structures 398” para. 0064) being operably placed on the last additional package layer formed
Chen and Yu teach packages with stacked devices. The “UBM patterns 600” are formed directly on the “TTVs 300” in Chen while the “UBM structures 398” are formed on an “RDL 350” over a layer including “semiconductor die 370”, “semiconductor die 380”, and “TEM chip 110”. The layer including “second molding layer 348”, “vias 349”, “die 340”, and “die 346” (para. 0057-0059) are analogous to the layer including “semiconductor die 200”, “TIV 300”, and “first encapsulant 400a” in Chen. The examiner understands that this additional layer in Yu integrates more semiconductor die to the package, therefore greater functionality and capability. In particular, the “TEM chip 110” has the capability of reducing warpage and may be a logic die, memory die, power management die, a sensor, a MEMS device, or more (para. 0019-0020). Redistribution structures are known to, as the name suggests, redistribute signals across different wirings. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the additional package layer may be formed over the “TIV 300” in Chen to include more semiconductor die such as “TEM chip 110”, “semiconductor die 370”, and “semiconductor die 380” that can have signals routed by “RDL 350”, increasing the package functionality.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Chen with the formation of the additional package layer as taught in Yu. An additional package layer adds further capability and functionality to the package.
Regarding claim 4, Chen, modified by Yu, teaches the method of claim 3, wherein at least one additional package layer contains an active component (“TEM chip 110 may include active devices”, para. 0019).
Regarding claim 5, Chen, modified by Yu, teaches the method of claim 3, wherein at least one additional package layer contains at least one passive component (“TEM chip 110 may include passive devices (e.g., resistor, capacitor, inductors)”, para. 0019).
Regarding claim 6, Chen, modified by Yu, teaches the method of claim 3, wherein at least one package component additional package layer contains a mems component (“TEM chip 110” may be a MEMS die, para. 0020).
Regarding claim 9, Chen, modified by Yu, teaches the method of claim 3, wherein the passive component is a magnetic component (“TEM chip 110” may be an inductor, para. 0019).
Regarding claim 10, Chen, modified by Yu, teaches the method of claim 9, wherein the magnetic component is an inductor (“TEM chip 110” may be an inductor, para. 0019).
Claim 3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, in view of Yu et al. US 20210098325 A1 (hereinafter referred to as Yu’25).
Regarding claim 3, Chen teaches the method of claim 1 but fails to teach further comprising forming at least one additional package layer after grinding, the bond pads being operably placed on the last additional package layer formed.
Nevertheless, Yu’25 teaches
further comprising forming at least one additional package layer (“redistribution structure RDL” para. 0023 FIG. 15) after grinding (“a planarization process is performed on the encapsulation material 300a” para. 0022 FIG. 3), the bond pads (the examiner considers “redistribution metallic layer 416” a pad for “redistribution metallic layer 418” which is a pillar bump, para. 0040 FIG. 15) being operably placed on the last additional package layer formed (“redistribution metallic layer 416” are part of the last package layer formed, the “redistribution structure RDL”).
Chen and Yu’25 teach methods of forming packages where encapsulated pillars are electrically connected to bonding pads that are then singulated. After “encapsulation material 300a” is planarized to expose “vias 270” (para. 0022 FIG. 3), a “supporting element 400” is formed as part of a lower portion of “redistribution structure RDL” (para. 0023 FIG. 13). As explained in para. 0045, “Supporting element 400 is used as a buffer between the encapsulated semiconductor devices 100, 200 and the redistribution structure RDL to reduce and absorb stress which is caused by coefficient of thermal expansion (CTE) mismatch between different materials. The supporting element 400 may prevent the metallic lines of the redistribution structure RDL from being opened induced by the delamination of the insulating encapsulant 300 from the semiconductor devices 100, 200.” The rest of the “redistribution structure RDL” interconnects “first semiconductor device 100” and “second semiconductor device 200” with external components (para. 0045). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “supporting element 400” improves the reliability of the package by preventing warpage due to thermal expansion and “redistribution structure RDL” enables integration of the package with other devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught in Chen with the additional package layer taught in Yu’25. The additional layer provides routing for the die in the package to external devices that can be bonded later while also mitigating delamination and damage due to warping.
Regarding claim 7, Chen, modified by Yu’25, teaches the method of claim 3, wherein at least one package layer is a thermal expansion control layer (“supporting element 400” in “redistribution structure RDL” absorbs stress from thermal warping (Yu para. 0045).
Claim 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, modified by Yu’25, as applied to claim 3 above, in view of Lee et al. US 20160007467 A1 (hereinafter referred to as Lee).
Chen, modified by Yu’25, teaches the method of claim 7 but fails to teach wherein the thermal expansion control layer is NiFe (36:64, ± 5%).
Nevertheless, Lee teaches
wherein the thermal expansion control layer is NiFe (36:64, ± 5%) (“stiffener substrate 100” is made of invar containing 63.5% iron and 36.5% nickel, para. 0042 FIG. 3).
Chen, modified by Yu’25, and Lee teach methods of forming packages that comprise thermal expansion control layers. “Supporting element 400” in Yu’25 comprises copper or a copper alloy (Yu’25 para. 0026). “Stiffener substrate 100” has a rigidity that prevents warpage (Lee para. 0028) and the invar alloy has a small coefficient of thermal expansion (para. 0042). Effective warpage control is attributed to the “stiffener substrate 100” having a small coefficient of thermal expansion (para. 0043). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “supporting element 400” can be made of invar alloy having 63.5% iron and 36.5% nickel instead of copper. The known material is rigid and has a small coefficient of thermal expansion, which is desired for controlling warpage.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Chen and Yu’25 with the nickel iron alloy of thermal expansion control layer taught in Lee. The alloy having 63.5% iron and 36.5% nickel is suitable for use as a thermal expansion control layer for its low coefficient of thermal expansion and rigidity.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898