DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chuang (US 2017 /0194557).
Regarding claim 1, Chuang discloses, in FIG. 3 and in related text, a method for fabricating a semiconductor device, comprising:
forming a first metal interconnection (121’) on a substrate (see Chuang, FIG. 3, [0029], [0033]);
forming a stop layer (141) on the first metal interconnection (121’), wherein the stop layer is a single layer directly contacting the first metal interconnection (see Chuang, FIG. 4, [0034]);
removing part of the stop layer to form a first opening (137’) exposing the first metal interconnection (121’) (see Chuang, FIG. 5, [0034]);
forming an electromigration enhancing layer (barrier layer 161) in the first opening, wherein the electromigration enhancing layer is a single layer filling the first opening completely while a width of a bottom surface of the electromigration enhancing layer is less than a width of a top surface of the first metal interconnection (121’) (see Chuang, FIG. 6, [0035]); and
forming a second metal interconnection (132) on (above) the electromigration enhancing layer (161) (see Chuang, FIG. 15, [0035], [0044]).
Regarding claim 2, Chuang discloses the method of claim 1.
Chuang discloses forming a first inter-metal dielectric (IMD) layer (128) on the substrate;
forming the first metal interconnection (121’) in the first IMD layer;
forming the stop layer (141) on the first IMD layer (see Chuang, FIG. 4, [0034]);
forming the electromigration enhancing layer (161) in the first opening (137’) (see Chuang, FIGS. 5-6, [0034]-[0035]);
forming a second IMD layer (127) on (above) the stop layer (140) and the electromigration enhancing layer (161);
forming the second metal interconnection (132) on (above) the electromigration enhancing layer (161) and in the second IMD layer (127); and
forming a first magnetic tunneling junction (MTJ) (135) on the second metal interconnection (132) (see Chuang, FIG. 15, [0027], [0044]).
Regarding claim 3, Chuang discloses the method of claim 2.
Chuang discloses planarizing (CMP) the electromigration enhancing layer (161) before forming the second IMD layer (see Chuang, FIG. 7, [0035]).
Regarding claim 4, Chuang discloses the method of claim 2.
Chuang discloses forming the second metal interconnection (132 on the left-hand side) and a third metal interconnection (132 on the right-hand side) on (above) the electromigration enhancing layer (161) and in the second IMD layer (127); and
forming the first MTJ (135 on the left-hand side) on the second metal interconnection and a second MTJ (135 on the right-hand side) on the third metal interconnection (see Chuang, FIG. 15, [0044]).
Regarding claim 5, Chuang discloses the method of claim 4.
Chuang discloses removing the stop layer (141) to form the first opening (137’ on the left-hand side) and a second opening (137’ on the right-hand side) (see Chuang, FIG. 5, [0034]);
forming the electromigration enhancing layer (161) in the first opening and the second opening (see Chuang, FIG. 6, [0035]);
planarizing (CMP) the electromigration enhancing layer to form a first electromigration enhancing layer (161 on the left-hand side) and a second electromigration enhancing layer (161 on the right-hand side) (see Chuang, FIG. 7, [0035]); and
forming the second metal interconnection (132 on the left-hand side) on the first electromigration enhancing layer and the third metal interconnection (132 on the right-hand side) on the second electromigration enhancing layer (see Chuang, FIG. 15, [0044]).
Regarding claim 6, Chuang discloses the method of claim 1.
Chuang discloses wherein the first metal interconnection (121’, copper) and the second metal interconnection (132, Ta) comprise different materials (see Chuang, [0024], [0035]).
Claims 1 and 6-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yang (US 2020/0388757).
Regarding claim 1, Yang discloses, in FIG. 1 and in related text, a method for fabricating a semiconductor device, comprising:
forming a first metal interconnection (18D) on a substrate;
forming a stop layer (20) on the first metal interconnection, wherein the stop layer is a single layer directly contacting the first metal interconnection (see Yang, FIG. 1, [0031], [0037]-[0038]);
removing part of the stop layer (20) to form a first opening (22) exposing the first metal interconnection (18D) (see Yang, FIG. 2, [0039]);
forming an electromigration enhancing layer (24) in the first opening, wherein the electromigration enhancing layer is a single layer filling the first opening completely while a width of a bottom surface of the electromigration enhancing layer is less than a width of a top surface of the first metal interconnection (18D) (see Yang, FIG. 3, [0040]; note that layer 24 includes TaN or TiN);
forming a second metal interconnection (28S) on the electromigration enhancing layer (24) (see Yang, FIG. 7, [0046], [0048]).
Regarding claim 6, Yang discloses the method of claim 1.
Yang discloses wherein the first metal interconnection (18D, copper) and the second metal interconnection (28S, tungsten) comprise different materials (see Yang, [0031], [0037], [0046], [0048]).
Regarding claim 7, Yang discloses the method of claim 1.
Yang discloses wherein the first metal interconnection (18D, copper) and the electromigration enhancing layer (24, TaN) comprise different materials (see Yang, [0031], [0037], [0040]).
Regarding claim 8, Yang discloses the method of claim 1.
Yang discloses wherein the second metal interconnection (28S, tungsten) and the electromigration enhancing layer (24, TaN) comprise different materials (see Yang, [0040], [0046], [0048]).
Response to Arguments
Applicant's arguments filed on 03/04/2026 have been fully considered but they are not persuasive.
Applicant argues, in pages 5-6 of the Remarks, that Chuang fails to disclose the limitation “wherein the stop layer is a single layer directly contacting the first metal interconnection” of amended claim 1.
In response, the Office notes that Chuang discloses the above limitation. Furthermore, Yang discloses the above limitation. See discussion on rejections of claim 1 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
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