Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-13 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIMOTO (Pub. No.: US 2020/0006392) in view of YOSHIDA et al. (Pub. No.: US 2019/0172843) (hereinafter YOSHIDA) and further in view of Suzuki (Pub. No.: US 2013/0207114).
Re claim 1, KIMOTO, FIG. 12E teaches an active-matrix substrate having a display region including a plurality of pixel regions, the active-matrix substrate comprising:
a substrate (1);
a plurality of thin-film transistors (GE/7c/5/SE/DE), supported on the substrate and associated with the plurality of pixel regions;
a plurality of pixel electrodes (PE(T2)) disposed in the plurality of pixel regions; and
a first insulating layer (12/13) located above the plurality of thin-film transistors and the plurality of pixel electrodes,
wherein each of the pixel electrodes (PE(T2), ¶ [0155]) is formed from a transparent conducting material,
each of the thin-film transistors includes a gate electrode (GE), a gate insulating layer (5) covering the gate electrode, source (SE) and drain electrodes (DE) placed at a distance from each other on top of the gate insulating layer, and an oxide semiconductor layer (7c, [0139]),
the oxide semiconductor layer includes a channel region (7c) that is in contact with the gate insulating layer (5) between the source electrode and the drain electrode, a source contact region that is in contact with at least part of an upper surface of the source electrode (9 of SE), and a drain contact region (that is in contact with at least part of an upper surface of the drain electrode (8 of DE),
the source electrode has a stack structure (8/9 of SE) including a source transparent conducting layer formed at a layer that is identical to that at which each of the pixel electrodes (PE, [0141]) is formed and a source metal layer disposed on top of part of an upper surface of the source transparent conducting layer and formed from a metal material,
the drain electrode includes a drain transparent (9 of DE) conducting layer formed at a layer that is identical to that at which each of the pixel electrodes (PE(T2)) is formed, and
the drain transparent conducting layer (8 of DE) is formed integrally with a corresponding one of the plurality of pixel electrodes (PE(T2)).
KIMOTO fails to teach the source electrode and the drain electrode are disposed between the gate insulating layer and the oxide semiconductor layer, and a portion of the upper surface of the source metal layer is in direct contact with a portion of the first insulating layer.
YOSHIDA teaches the source electrode (7A, [0120]) and the drain electrode (8A) are disposed between the gate insulating layer (11, FIG. 15(b), note that “the second insulating layer 11 disposed between the back-gate electrode BG and the oxide semiconductor layer 5 is also hereinafter referred to as a “sub-gate insulating layer.””, ¶ [0068]) and the oxide semiconductor layer (5), and a portion of the upper surface of the source metal layer (7A, FIG. 15(b)) is in direct contact with a portion of the first insulating layer (11).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of reducing the manufacturing cost by implement the back gate electrode as taught by YOSHIDA, [0014].
Moreover, KIMOTO/YOSHIDA fails to teach the gate electrode, the gate insulating layer, the source and drain electrodes and the oxide semiconductor layer, and the first insulating layer are arranged in this order ascending from the substrate, and a portion of the oxide semiconductor layer is in direct contact with a portion of an upper surface of the source metal layer.
Suzuki teaches the gate electrode (11a, FIG. 11), the gate insulating layer (12a), the source and drain electrodes (15aa/15b) and the oxide semiconductor layer (C/16a, Abstract), and the first insulating layer (17a, [0051]) are arranged in this order ascending from the substrate, and a portion of the oxide semiconductor layer (16a, FIG. 10(d)), [0052]) is in direct contact with a portion of an upper surface of the source metal layer (14a, [0054]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing or reducing the diffusion of the copper into the upper layers as taught by Suzuki, [0012].
Moreover, after the combining of YOSHIDA and Suzuki would teach a portion of the oxide semiconductor layer is in direct contact with a portion of an upper surface of the source metal layer, and another portion of the upper surface of the source metal layer is in direct contact with a portion of the first insulating layer.
Re claim 2, KIMOTO, FIG. 12E teaches the active-matrix substrate according to Claim 1, wherein the drain electrode includes the drain transparent conducting layer and a drain metal layer (9 of DE) disposed on top of part of an upper surface of the drain transparent conducting layer (8 of DE) and formed at a layer that is identical to that at which the source metal layer is formed (9 of SE).
Re claim 3, KIMOTO, FIG. 1 [flip it 90º] teaches the active-matrix substrate according to Claim 1, further comprising:
a plurality of source bus lines (SL) extending in a row-wise direction; and
a plurality of gate bus lines (GL) extending in a column-wise direction, wherein
each of the source bus lines has the stack structure including the source transparent conducting layer (8 of SE) and the source metal layer (9 of SE), and
the source electrode (SE) of each of the thin-film transistors is formed integrally with a corresponding one of the plurality of source bus lines (SL).
Re claim 7, KIMOTO, FIG. 12E teaches the active-matrix substrate according to Claim 1, further comprising a common electrode (TC(T2), [0155]) disposed on top of the first insulating layer (12), wherein when seen from a direction normal to the substrate, the common electrode partially overlaps the plurality of pixel electrodes via the first insulating layer.
Re claim 8, KIMOTO, FIG. 12E teaches the active-matrix substrate according to Claim 1, wherein in each of the pixel regions, the first insulating layer (12/13) has an opening through which part of each of the pixel electrodes (PE(T2)) is exposed.
Re claim 9, KIMOTO, FIG. 12E teaches the active-matrix substrate according to Claim 1, further comprising a plurality of terminals disposed in a non-display region other than the display region,
wherein each of the terminals includes
a source connection including a connection transparent conducting layer (CE(T2) formed at a layer that is identical to that at which each of the pixel electrodes (PE(T2)) is formed and a connection metal layer disposed on top of part of an upper surface of the connection transparent conducting layer and formed at a layer that is identical to that at which the source metal layer is formed,
a connection covering layer (7b), formed at a layer that is identical to that at which the oxide semiconductor layer (7c) of each of the thin-film transistors is formed, that covers part of an upper surface and side surfaces of the source connection,
an extension of the first insulating layer provided on top of the connection covering layer,
a contact hole, formed in the first insulating layer (12/13) and the connection covering layer, through which part of the source connection is exposed, and
an upper connection that is in contact with the part of the source connection in the contact hole.
Re claim 10, KIMOTO, FIG. 12E teaches the active-matrix substrate according to Claim 6, further comprising a plurality of terminals disposed in a non-display region other than the display region, wherein each of the terminals includes
a source connection including a connection transparent conducting layer (TC(T2)/SE), note that “the source connecting portion SC are electrically connected to each other via the upper connecting portion TC”, [0155]) formed at a layer that is identical to that at which each of the pixel electrodes (PE(T2)) is formed and a connection metal layer disposed on top of part of an upper surface of the connection transparent conducting layer and formed at a layer that is identical to that at which the source metal layer is formed,
an extension of the first insulating layer (12/13) provided on top of the source connection (SE),
a contact hole (HC), formed in the first insulating layer, through which part of the source connection is exposed, and
an upper connection (TC(T2)) that is in contact with the part of the source connection in the contact hole.
Re claim 11, KIMOTO, FIG. 12E teaches the active-matrix substrate according to Claim 1, wherein the first insulating layer does not include an organic insulating film (ITO material, [0203]).
Re claim 12, KIMOTO, FIG. 12E teaches the active-matrix substrate according to Claim 1, wherein the oxide semiconductor layer contains an In-Ga-Zn-O semiconductor [0178].
Re claim 13, KIMOTO, FIG. 12E teaches the active-matrix substrate according to Claim 12, wherein the In-Ga-Zn-O semiconductor includes a crystalline portion ([0178] & [0271]).
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Re claim 19, KIMOTO, FIG. 12E [as shown above] teaches the active matrix substrate according to Claim 1, wherein the source contact region [SCR] is directly in contact with the at least part of the upper surface of the source electrode (9 of SE), and the drain contact region [DCR] is directly in contact with the at least part of the upper surface of the drain electrode (9 of DE).
Response to Arguments
Applicant's arguments with respect to claims 1-13 and 19 on the remarks filed on 04/30/2026 have been considered but are not persuasive because Suzuki teaches in each of the thin-film transistors, the gate electrode (11a, FIG. 11), the gate insulating layer (12a), the source and drain electrodes (15aa/15b) and the oxide semiconductor layer (C/16a, Abstract), and the first insulating layer (17a, [0051]) are arranged in this order ascending from the substrate, and a portion of the oxide semiconductor layer (16a, FIG. 10(d)), [0052]) is in direct contact with a portion of an upper surface of the source metal layer (14a, [0054]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing or reducing the diffusion of the copper into the upper layers as taught by Suzuki, [0012].
Moreover, after the combining of YOSHIDA and Suzuki would teach a portion of the oxide semiconductor layer is in direct contact with a portion of an upper surface of the source metal layer, and another portion of the upper surface of the source metal layer is in direct contact with a portion of the first insulating layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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