DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 21, 2025, has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-11 and 13-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee (US 2023/0146151), of record.
(Re Claim 1) Lee teaches a semiconductor structure, comprising (see Figs. 1-26 and corresponding text):
a first work function layer (140) disposed on a substrate (100);
a second work function layer (150) disposed on the first work function layer;
a protective layer (160) disposed on the second work function layer;
a gate stack (277+267+257+247) disposed on the protective layer;
a first liner (355+360) disposed on the gate stack;
a second liner (380 or 345) disposed on the first liner;
a planarization layer (370) disposed on the second liner; and
a gate plug (530+540) disposed on the planarization layer and in contact with the first work function layer and the second work function layer.
(Re Claim 2) wherein a side surface of the first work function layer is aligned with a side surface of the second work function layer (Fig. 26, side surfaces are aligned).
(Re Claim 3) wherein the gate plug extends through the planarization layer, the second liner, the protective layer, and the second work function layer (Fig. 26, also compare Figs. 21 and 25, the gate plug 600 is formed in the opening 520 which was formed through each of the claimed layers).
(Re Claim 4) wherein the first liner comprises an oxide and the second liner comprises a nitride (¶¶40, 46).
(Re Claim 5) wherein the planarization layer comprises an oxide and the second liner comprises a nitride (¶¶40, 46).
(Re Claim 6) wherein the first liner comprises an oxide and the protective layer comprises a nitride (¶¶25, 40).
(Re Claim 7) wherein the first liner comprises an oxide and the second work function layer comprises polycrystalline silicon (¶¶25, 40).
(Re Claim 8) wherein a top surface of the planarization layer is aligned with a top surface of the second liner (Fig. 26).
(Re Claim 9) wherein the second work function layer has a vertical side surface (Fig. 26).
(Re Claim 10) wherein a side surface of the second work function layer is aligned with a side surface of the protective layer (Fig. 26).
(Re Claim 11) wherein the first work function layer has a vertical side surface (Fig. 26).
(Re Claim 13) wherein the gate stack further comprises: a gate structure (277+267+257+247) disposed on the protective layer; and a spacer layer (3451+200) disposed on the gate structure, wherein the first liner and the second liner contact the spacer layer (Fig. 26).
(Re Claim 14) wherein the spacer layer further comprises: a first spacer layer (200) disposed on the gate structure; and a second spacer (345) disposed on the gate structure, wherein the first spacer layer comprises an oxide and the second spacer comprises a nitride (¶¶40, 29).
(Re Claim 15) wherein the first liner comprises an oxide (¶40).
Response to Arguments
Applicant's arguments filed November 21, 2025, have been fully considered and are persuasive with respect to the mapping used in the prior rejection. Based on the prior mapping, the fist liner was not disposed on a top and side surface of the gate stack. The rejections above have been updated based on the amendments and now the first liner is the combination of 355+360. The claim language does not preclude this treatment. The remainder of Applicant’s remarks are moot.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches pertinent device structures having the multilayer buried word line, protective layers, gates, liners, etc..
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
1 Second liner being the 380 alternative noted in claim 1