Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments/Amendments
Applicant's arguments, pages 2-4 of the remarks, filed 03/04/2026, with respect to the 35 U.S.C 103 rejection of claim 1 as unpatentable over US20160027738A1; Murray et al.; (hereinafter “Murray”) in view of US 20030228749A1; Sinha et al.; (hereinafter “Sinha”) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103 to claim 1 as being unpatentable over Murray in view of US20190013353A1; Lee et al.; (hereinafter “Lee”). Lee has been introduced in view of the arguments to claim 1 for teaching at least the limitation: “a bottommost surface of the second metal interconnection is on and directly contacting a topmost surface of the electromigration enhancing layer” recited in claim 1 (see 35 U.S.C. 103 rejection of claim 1 below)
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/22/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 3-9 are rejected under 35 U.S.C. 103 as being unpatentable over Murray in view of Lee.
Regarding Claim 1 (currently amended), Murray teaches a semiconductor device ([0005], semiconductor interconnect structure), comprising:
a first metal interconnection (#208, Figure 7, conductive material) on a substrate ([0026], interconnect structure #202 locates on substrate);
a first inter-metal dielectric (IMD) layer around the first metal interconnection (#204, dielectric layer around #208);
an electromigration enhancing layer (#312, [0027], metal capping layer serves as diffusion barrier) on the first metal interconnection (#312 disposes on #208);
a second IMD layer on and around the electromigration enhancing layer (dielectric layer #416 and dielectric capping layer #314 surround #312); and
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a second metal interconnection (#622, conductive material in via #110/#120) on the electromigration enhancing layer (Figure 7 of Murray annotated, #622 disposes on #312).
Murray does not explicitly teach a bottommost surface of the second metal interconnection is on and directly contacting a topmost surface of the electromigration enhancing layer.
However, Lee teaches a comparable semiconductor device (Figure 1, [0029], MRAM arrays), comprising a bottommost surface of a second metal interconnection (#116, conductive pedestals) is on and directly contacting a topmost surface of an electromigration enhancing layer (#124, [0039], tantalum nitride conductive layer, wherein the bottommost surface of #116 is on and directly contacts the topmost surface of #124).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention of Murray with the teaching of Lee, as it would be simply a substitution of one known element (MRAM structure of Murray) for another (MRAM structure of Lee) in comparable devices to obtain predictable results. See MPEP 2143(I)(B).
Regarding Claim 3, Murray in view of Lee teaches the semiconductor device as described in claim 1, wherein Murray further teaches bottom surfaces of the electromigration enhancing layer and the second IMD layer are coplanar (Figure 7, bottom surfaces of metal capping layer #312 and dielectric capping layer #314 are coplanar).
Regarding Claim 4, Murray in view of Lee teaches the semiconductor device as described in claim 1, wherein Murray further teaches a sidewall of the electromigration enhancing layer comprises a planar sidewall (Figure 7 of Murray annotated, planar sidewall #SW of #312).
Regarding Claim 5, Murray in view of Lee teaches the semiconductor device as described in claim 1, wherein Murray further teaches a sidewall of the electromigration enhancing layer is orthogonal to a top surface of the first IMD layer (Figure 7 of Murray annotated, sidewall #SW of #312 is orthogonal to top surface #S1 of dielectric layer #204).
Regarding Claim 6, Murray in view of Lee teaches the semiconductor device as described in claim 1, wherein Murray further teaches a sidewall of the electromigration enhancing layer is orthogonal to a top surface of the first metal interconnection (Figure 7 of Murray annotated, #SW of #312 is orthogonal to top surface #S2 of conductive material #208).
Regarding Claim 7, Murray in view of Lee teaches the semiconductor device as described in claim 1, wherein Murray further teaches the first metal interconnection) and the second metal interconnection (conductive material #622 can be selected from group of metals such as Al or W) comprise different materials (([0033] & [0045], conductive materials #208 and #622 are of group of metals such as Cu, W or more, wherein #208 and #622 can be different materials according to [0045]).
Regarding Claim 8, Murray in view of Lee teaches the semiconductor device as described in claim 1, wherein Murray further teaches the first metal interconnection ([0033], #208 is of group of metals such as Cu, W or more) and the electromigration enhancing layer comprise different materials ([0035], metal capping layer #312 can be Ti, Ta or different material than #208 in order to serve as diffusion barrier).
Regarding Claim 9, Murray in view of Lee teaches the semiconductor device as described in claim 1, wherein Murray further teaches the second metal interconnection ([0045], #622 is of group of metals such as Cu, W or more) and the electromigration enhancing layer comprise different materials ([0035], metal capping layer #312 can be Ti, Ta or different materials than #622 in order to serve as diffusion barrier).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Murray in view of Lee, and further in view of US 10707413 B1; Dutta et al.; (hereinafter “Dutta”).
Regarding Claim 2, Murray in view of Lee teaches the semiconductor device as described in claim 1, wherein Murray further teaches:
a third metal interconnection (#622, Figure 7, conductive material in via #110/#120) on the electromigration enhancing layer (#622 disposes on metal capping layer #312);
the second IMD layer (#416, dielectric layer) around the second metal interconnection and the third metal interconnection (Figure 7, #416 surrounds conductive material #622 in vias #110 and #120).
Murray in view of Lee does not explicitly teach a first magnetic tunneling junction (MTJ) on the second metal interconnection; and a second MTJ on the third metal interconnection.
However, Dutta teaches a semiconductor device (col. 2, ln. 12, MRAM device) wherein a first magnetic tunneling junction (MTJ) (#145-1, Figure 8, MTJ layer stack) on the second metal interconnection (#145-1 disposes on one of metallization structures #122); and a second MTJ (#145-2, MTJ stack layer) on the third metal interconnection (#145-2 disposes one of structures #122).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention of Murray in view of Lee with the teaching of Dutta, as it would be simply a substitution of one known element (back-end-of-line BEOL interconnect structure of Dutta) for another (BEOL interconnect structure of Murray) to obtain predictable results. See MPEP 2143(I)(B). Additionally, [0031] of Murray teaches the interconnect structure applicable to magnetic memory device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20060234497A1 – Figures 4-5 and [0031]
US20060216929A1 – Figure 2I
US20210013097A1 – Figure 7B and [0068-0069]
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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