Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 3-9 are rejected under 35 U.S.C. 103 as being unpatentable over US20160027738A1; Murray et al.; (hereinafter “Murray”) in view of US20060216929A1; Park et al.; (hereinafter “Park”).
Regarding Claim 1 (currently amended), Murray teaches a semiconductor device ([0005], semiconductor interconnect structure), comprising:
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a first metal interconnection (#208, Figure 7 of Murray annotated) on a substrate ([0026]);
a first inter-metal dielectric (IMD) layer (#204) around the first metal interconnection (#208);
an electromigration enhancing layer (#312, [0027], metal capping layer serves as diffusion barrier) on the first metal interconnection (#208);
a second IMD layer (#416/#314) on and around the electromigration enhancing layer (#312); and
a second metal interconnection (#622) on the electromigration enhancing layer (#312), and
a width of the bottommost surface of the second metal interconnection is less than a width of the topmost surface of the electromigration enhancing layer (Figure 7 of Murray annotated, a width of the bottommost surface of conductive feature #622 is less than a width of the topmost surface of layer #312).
Murray does not explicitly teach a bottommost surface of the second metal interconnection is on and directly contacting only a portion of a topmost surface of the electromigration enhancing layer while a width of the bottommost surface of the second metal interconnection is less than a width of the topmost surface of the electromigration enhancing layer.
However, Park teaches metal interconnects and vias structure in semiconductor device ([0014]), comprising a bottommost surface of a second metal interconnection (#232, Figure 2I, [0027], interconnect via) is on and directly contacting only a portion of a topmost surface of an electromigration enhancing layer (#208, [0017], cap layer for preventing out diffusion of atoms, wherein #232 directly contacts a portion of #208) while a width of the bottommost surface of the second metal interconnection is less than a width of the topmost surface of the electromigration enhancing layer (Figure 2I, a width of the bottommost surface of #232 is less than topmost surface of #208).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention of Murray with the teaching of Park, as it would be simply a substitution of one known element (interconnect structure of Murray) for another (interconnect structure of Park) in comparable devices to obtain predictable results (electrically interconnect devices in backend process). See MPEP 2143(I)(B).
Regarding Claim 3, Murray in view of Park teaches the semiconductor device as described in claim 1, wherein Murray further teaches bottom surfaces of the electromigration enhancing layer and the second IMD layer are coplanar (Figure 7, bottom surfaces of metal capping layer #312 and dielectric capping layer #314 are coplanar).
Regarding Claim 4, Murray in view of Park teaches the semiconductor device as described in claim 1, wherein Murray further teaches a sidewall of the electromigration enhancing layer comprises a planar sidewall (Figure 7 of Murray annotated, planar sidewall #SW of #312).
Regarding Claim 5, Murray in view of Park teaches the semiconductor device as described in claim 1, wherein Murray further teaches a sidewall of the electromigration enhancing layer is orthogonal to a top surface of the first IMD layer (Figure 7 of Murray annotated, sidewall #SW of #312 is orthogonal to top surface #S1 of dielectric layer #204).
Regarding Claim 6, Murray in view of Park teaches the semiconductor device as described in claim 1, wherein Murray further teaches a sidewall of the electromigration enhancing layer is orthogonal to a top surface of the first metal interconnection (Figure 7 of Murray annotated, #SW of #312 is orthogonal to top surface #S2 of conductive material #208).
Regarding Claim 7, Murray in view of Park teaches the semiconductor device as described in claim 1, wherein Murray further teaches the first metal interconnection) and the second metal interconnection (conductive material #622 can be selected from group of metals such as Al or W) comprise different materials (([0033] & [0045], conductive materials #208 and #622 are of group of metals such as Cu, W or more, wherein #208 and #622 can be different materials according to [0045]).
Regarding Claim 8, Murray in view of Park teaches the semiconductor device as described in claim 1, wherein Murray further teaches the first metal interconnection ([0033], #208 is of group of metals such as Cu, W or more) and the electromigration enhancing layer comprise different materials ([0035], metal capping layer #312 can be Ti, Ta or different material than #208 in order to serve as diffusion barrier).
Regarding Claim 9, Murray in view of Park teaches the semiconductor device as described in claim 1, wherein Murray further teaches the second metal interconnection ([0045], #622 is of group of metals such as Cu, W or more) and the electromigration enhancing layer comprise different materials ([0035], metal capping layer #312 can be Ti, Ta or different materials than #622 in order to serve as diffusion barrier).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Murray in view of Park, and further in view of US 10707413 B1; Dutta et al.; (hereinafter “Dutta”).
Regarding Claim 2, Murray in view of Park teaches the semiconductor device as described in claim 1, wherein Murray further teaches:
a third metal interconnection (#622, Figure 7, conductive material in via #110/#120) on the electromigration enhancing layer (#622 disposes on metal capping layer #312);
the second IMD layer (#416, dielectric layer) around the second metal interconnection and the third metal interconnection (Figure 7, #416 surrounds conductive material #622 in vias #110 and #120).
Murray in view of Park does not explicitly teach a first magnetic tunneling junction (MTJ) on the second metal interconnection; and a second MTJ on the third metal interconnection.
However, Dutta teaches a semiconductor device (col. 2, ln. 12, MRAM device) wherein a first magnetic tunneling junction (MTJ) (#145-1, Figure 8, MTJ layer stack) on the second metal interconnection (#145-1 disposes on one of metallization structures #122); and a second MTJ (#145-2, MTJ stack layer) on the third metal interconnection (#145-2 disposes one of structures #122).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention of Murray in view of Park with the teaching of Dutta, as it would be simply a substitution of one known element (back-end-of-line BEOL interconnect structure of Dutta) for another (BEOL interconnect structure of Murray) to obtain predictable results (implementation of interconnect structure in magnetic memory device). See MPEP 2143(I)(B).
Response to Arguments/Amendments
Applicant's amendments to claim 1 and corresponding arguments, pages 4-6 of the remarks, filed 08/04/2026, with respect to the 35 U.S.C 103 rejection of claim 1 as unpatentable over Murray in view of US20190013353A1; Lee et al.; (hereinafter “Lee”) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103 to claim 1 as being unpatentable over Murray in view of Park. Park has been introduced in view of the amendment to claim 1 (see 35 U.S.C. 103 rejection of amended claim 1 above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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