DETAILED ACTION
Election/Restriction
1. Applicant's election without traverse of Group I, claims 1 - 15, 30 - 35 is acknowledged.
Specification
2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
3. Claims 1, 13, 30 are objected to because of the following informalities:
In claim 1, line 11, “an eighth transistor” should be changed to “the first sub-pixel further comprises second, third, fourth, fifth, sixth, seventh, and eighth transistors wherein the eighth transistor” because claim 1 does not include second, third, fourth, fifth, sixth, seventh transistors before the eighth transistor.
In claim 13, line 12, “an eighth transistor” should be changed to “the first sub-pixel further comprises second, third, fourth, fifth, sixth, seventh, and eighth transistors wherein the eighth transistor” because claim 13 does not include second, third, fourth, fifth, sixth, seventh transistors before the eighth transistor.
In claim 30, line 13, “an eighth transistor” should be changed to “the first sub-pixel further comprises second, third, fourth, fifth, sixth, seventh, and eighth transistors wherein the eighth transistor” because claim 13 does not include second, third, fourth, fifth, sixth, seventh transistors before the eighth transistor.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1 – 5, 10, 11 are rejected under 35 U.S.C. 103 as being unpatentable over CHUNG et al. (2019/0348491) in view of Zhang et al. (11721286).
With regard to claim 1, CHUNG et al. disclose a display device (for example, see figs. 3, 4) comprising:
a first data line (referred to as “DL1” by examiner’s annotation shown in fig. 4 below; wherein the S/D wiring DL1 functioning as a first data line) inherently configured to receive a first data voltage;
a second data line (referred to as “DL2” by examiner’s annotation shown in fig. 4 below; wherein the S/D wiring DL2 functioning as a second data line) inherently configured to receive a second data voltage;
a low driving voltage line (a power supply line E-VSS (ELVSS) receiving a driving current Id and maybe having 0 volt, functioning as a low driving voltage line) inherently configured to receive a low driving voltage; and
a first sub-pixel (PX, fig. 4) connected to the first data line (DL1), the second data line (DL2), and the low driving voltage line,
wherein the first sub-pixel (PX, fig. 4) comprises: a cathode pad electrode (referred to as “E2” by examiner’s annotation shown in fig. 4 below) connected to the low driving voltage line (the power supply line E-VSS, fig. 4 functioning as a low driving voltage line and connected to a low voltage ELVss based on the same ground potential Vss; for example, see fig. 5);
a first transistor (T1) inherently configured to generate a control current (any current to be a control current) according to the first data voltage (it is inherently having the first data voltage from the first data line DL1) of the first data line (DL1) and having a first gate electrode (G1);
a transistor (T6) inherently configured to generate a driving current (Id) applied to a light emitting element (OLED) inherently according to the second data voltage (it is inherently having the second data voltage from the second data line DL2) of the second data line (DL2); and
a first capacitor (Cst, fig. 4) comprising a first capacitor electrode (C1) connected to the first gate electrode (G1, fig. 4), and a second capacitor electrode (C2) on the first capacitor electrode (C1), and wherein the low driving voltage line (E-VSS, fig. 3) is surrounding the second capacitor electrode (the Pixel PX, figs. 3, 4 comprising the capacitor electrode C2).
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CHUNG et al. do not clearly disclose the low driving voltage line is at a same layer as the second capacitor electrode and the transistor to be eighth transistor.
However, Zhang et al. discloses the low driving voltage line is at a same layer as the second capacitor electrode. (the power signal terminal VSS, functioning as the low driving voltage line, is as the second electrode of the capacitor C1; for example, see column 23, lines 57 – 61) and the transistor (T8) to be eighth transistor and connected to the light emitting device OLED. (for example, see fig. 7).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the CHUNG et al.’s device to have the low driving voltage line is at a same layer as the second capacitor electrode as taught by Zhang et al. in order to enhance a high capacitance efficiency of the capacitor and in order to increase current flowing through an OLED of the pixel for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 2, fig. 4 of CHUNG et al. disclose a scan write line (14, fig. 4) inherently configured to receive a scan write signal; and a second transistor (T2, fig. 4) comprising a second gate electrode (G2) connected to the scan write line (14, fig. 4), but fig. 4 of CHUNG et al. do not clearly disclose the second gate electrode overlaps the low driving voltage line.
However, Fig. 5 of CHUNG et al. disclose the second gate electrode (CE2) overlaps the low driving voltage line (low power line E-VSS connected to VSP, in fig. 5. Thus, E-Vss and VSP functioning as the low driving voltage line).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the fig. 4 of CHUNG et al. and Zhang et al.’s device to have the second gate electrode overlaps the low driving voltage line as taught by fig. 5 of CHUNG et al. in order to secure power efficiency of the pixel for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 3, fig. 4 of CHUNG et al. do not clearly disclose the low driving voltage line is on a lower side of the first data line and the second data line.
However, Fig. 5 of CHUNG et al. disclose the low driving voltage line (low power line E-VSS connected to VSP, in fig. 5. Thus, E-Vss and VSP functioning as the low driving voltage line) is on (above) a lower side (a bottom side) of the first data line (S/D electrode IE1 functioning as the first data line) and the second data line (low power line E-VSS connected to VSP, in fig. 5. Thus, E-Vss and VSP functioning as the low driving voltage line).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the fig. 4 of CHUNG et al. and Zhang et al.’s device to have the low driving voltage line is on a lower side of the first data line and the second data line as taught by fig. 5 of CHUNG et al. in order to secure power efficiency of the pixel for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 4, CHUNG et al. disclose the cathode pad electrode (electrode E2 functioning as the cathode pad electrode based on the second electrode E2 of each of the organic light emitting elements OD may receive the same voltage; for example, see paragraph [0153]) is connected to the low driving voltage line (E-VSS) through a pad contact hole (referred to as “V1” by examiner’s annotation shown in fig. 5 below).
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With regard to claim 5, CHUNG et al. disclose the cathode pad electrode (E2) comprises a stem portion (referred to as “V2” by examiner’s annotation shown in fig. 5 below) extending in a first direction (a vertical direction), and a branch portion (referred to as “BR” by examiner’s annotation shown in fig. 5 below) connected to the stem portion (V2) and extending in a second direction (a horizontal direction) intersecting the first direction (a vertical direction), and wherein the pad contact hole (V1) is in the stem portion (V2).
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With regard to claim 10, CHUNG et al. disclose an anode pad electrode (electrode E1 functioning as an anode pad electrode because the second electrode E2 functioning as a cathode of each of the organic light emitting elements OD may receive the same voltage; for example, see paragraph [0153] spaced from the cathode pad electrode (E2), wherein the light emitting element (EML) is on the cathode pad electrode (E2) and the anode pad electrode (E1).
With regard to claim 11, CHUNG et al. disclose a first light emitting line (OLED, fig. 4) inherently configured to receive a first light emitting signal; a first high driving voltage line (26) configured to receive a first high driving voltage (ELVDD); and a fifth transistor (T5) connecting the first high driving voltage line (26) to one electrode (S1) of the first transistor (T1) according to the first light emitting signal (the first light emitting signal is connected to the electrode S1), wherein the low driving voltage line (E-VSS) includes a hole (referred to as “H1” by examiner’s annotation shown in fig. 3 below) exposing one electrode (S5) of the fifth transistor (the fifth transistor T5 forming in the pixel PX).
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6. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over CHUNG et al. (2019/0348491) in view of Zhang et al. (11721286) and further in view of Kuo et al. (10770441).
With regard to claim 12, CHUNG et al. and Zhang et al. do not clearly disclose the light emitting element is a flip chip type micro light emitting diode element
However, Kuo et al. disclose the light emitting element (130, fig. 1A) is a flip chip type micro light emitting diode element. (for example, see column 4, lines 4, 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the CHUNG et al. and Zhang et al.’s device to have the light emitting element is a flip chip type micro light emitting diode element as taught by Kuo et al. in order to a high light efficiency of the light emitting devices for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
7. Claims 30, 32 - 35 are rejected under 35 U.S.C. 103 as being unpatentable over CHUNG et al. (2019/0348491) in view of Zhang et al. (11721286) and further in view of SIM et al. (2022/0102477).
With regard to claim 30, CHUNG et al. disclose a display device (for example, see figs. 2 - 4) comprising:
a substrate (SUB, fig. 2)
a first data line (referred to as “DL1” by examiner’s annotation shown in fig. 4 below wherein the S/D wiring DL1 functioning as a first data line) on one surface (a first data line DL1, forming in the pixel, wherein the pixel PX forming on a top surface) of the substrate (SUB) and inherently configured to receive a first data voltage;
a second data line (referred to as “DL2” by examiner’s annotation shown in fig. 4 below; wherein the S/D wiring DL2 functioning as a second data line) inherently configured to receive a second data voltage;
a low driving voltage line (a power supply line E-VSS (ELVSS), receiving a driving current Id and maybe having 0 volt, functioning as a low driving voltage line) inherently configured to receive a low driving voltage; and
a first sub-pixel (PX, fig. 4) connected to the first data line (DL1), the second data line (DL2), and the low driving voltage line,
wherein the first sub-pixel (PX, fig. 4) comprises: a light emitting element (OLED); a cathode pad electrode (referred to as “E2” by examiner’s annotation shown in fig. 4 below) connected to the low driving voltage line (the power supply line E-VSS, fig. 4 functioning as a low driving voltage line and connected to a low voltage ELVss based on the same ground potential Vss; for example, see fig. 5);
a first transistor (T1) inherently configured to generate a control current (any current to be a control current) according to the first data voltage (it is inherently having the first data voltage from the first data line DL1) of the first data line (DL1) and having a first gate electrode (G1);
a transistor (T6) inherently configured to generate a driving current (Id) applied to a light emitting element (OLED) inherently according to the second data voltage (it is inherently having the second data voltage from the second data line DL2) of the second data line (DL2); and
a first capacitor (Cst, fig. 4) comprising a first capacitor electrode (C1) connected to the first gate electrode (G1, fig. 4), and a second capacitor electrode (C2) on the first capacitor electrode (C1), and wherein the low driving voltage line (E-VSS, fig. 3) is surrounding the second capacitor electrode (the Pixel PX, figs. 3, 4 comprising the capacitor electrode C2).
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CHUNG et al. do not clearly disclose the low driving voltage line is at a same layer as the second capacitor electrode and the transistor to be eighth transistor.
However, Zhang et al. discloses the low driving voltage line is at a same layer as the second capacitor electrode. (the power signal terminal VSS, functioning as the low driving voltage line, is as the second electrode of the capacitor C1; for example, see column 23, lines 57 – 61) and the transistor (T8) to be eighth transistor and connected to the light emitting device OLED. (for example, see fig. 7).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the CHUNG et al.’s device to have the low driving voltage line is at a same layer as the second capacitor electrode as taught by Zhang et al. in order to enhance a high capacitance efficiency of the capacitor and in order to increase current flowing through an OLED of the pixel for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
CHUNG et al. and Zhang et al. do not clearly disclose the display device is a tiled display device comprising: a plurality of display devices and a joint located between the plurality of display devices.
However, SIM et al. disclose the display device (1000) is a tiled display device (for example, see paragraph [0125]) comprising: a plurality of display devices (400A, 400B) and a joint (referred to as “J1” by examiner’s annotation shown in fig. 12 below) located between the plurality of display devices (400A, 400B). (for example, see fig. 12).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the CHUNG et al. and Zhang et al.’s device to have the display device is a tiled display device comprising: a plurality of display devices and a joint located between the plurality of display devices as taught by SIM et al. in order to increase an effective display screen size with the same area for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 32, CHUNG et al. disclose the substrate (SUB) comprises glass (for example, see paragraph [0122]).
With regard to claim 33, SIM et al. disclose the first display device further comprises: a pad (PAD1) on a first surface (a top surface) of the substrate (110, 110’); and a side connection line (140) on the first surface (the top surface) of the substrate (110), a second surface (a bottom surface of the substrate 110, 110’) opposite to the first surface (the top surface), and one side surface (referred to as “S” by examiner’s annotation shown in fig. 13 below) between the first surface (the top surface) and the second surface (the bottom surface), and connected to the pad (PAD1).
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With regard to claim 34, SIM et al. disclose a connection line (450, fig. 13) on the second surface (the bottom surface) of the substrate 110, 110’); and a flexible film (patterns 460, 480 functioning as a flexible film based on the substrate 110 can have a flexibility so as to be bendable as needed; for example, see paragraph [0047]) connected to connecting wiring (PAD2 functioning as connecting wiring) through a conductive adhesive member (layers 460, 480, 490 functioning as a conductive adhesive member), and the side connection line (480) is connected to the connection line (450).
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With regard to claim 35, CHUNG et al. disclose the plurality of display devices (400A, 400B, 400C, 400D) are arranged in a matrix form of M rows and N columns.
8. Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over CHUNG et al. (2019/0348491) in view of Zhang et al. (11721286) and in view of SIM et al. (2022/0102477) and further in view of Kuo et al. (10770441).
With regard to claim 31, CHUNG et al., Zhang et al. and SIM et al. do not clearly disclose the light emitting element is a flip chip type micro light emitting diode element
However, Kuo et al. disclose the light emitting element (130, fig. 1A) is a flip chip type micro light emitting diode element. (for example, see column 4, lines 4, 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the CHUNG et al., Zhang et al. and SIM et al.’s device to have the light emitting element is a flip chip type micro light emitting diode element as taught by Kuo et al. in order to a high light efficiency of the light emitting devices for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
9. Claims 6 - 9 would be allowable if rewritten to overcome the objection, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 6 - 9 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as a twelfth transistor connecting the second high driving voltage line to one electrode of the eighth transistor according to the second light emitting signal, wherein the second high driving voltage line is on the low driving voltage line as recited in claim 6.
10. Claims 13 - 15 would be allowable if rewritten to overcome the objection, set forth in this Office action.
Claims 13 - 15 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as a capacitor electrode on the first gate electrode, and wherein the low driving voltage line is at a same layer as the capacitor electrode, and the second high driving voltage line includes an opening exposing the low driving voltage line as recited in claim 13.
CHUNG et al. (2019/0348491) disclose a display device (for example, see figs. 3, 4) comprising:
a first data line (referred to as “DL1” by examiner’s annotation shown in fig. 4 below; wherein the S/D wiring DL1 functioning as a first data line) inherently configured to receive a first data voltage; a second data line (referred to as “DL2” by examiner’s annotation shown in fig. 4 below; wherein the S/D wiring DL2 functioning as a second data line) inherently configured to receive a second data voltage; a low driving voltage line (a power supply line E-VSS, receiving a driving current Id and maybe having 0 volt, functioning as a low driving voltage line) inherently configured to receive a low driving voltage; and a first sub-pixel (PX, fig. 4) connected to the first data line (DL1), the second data line (DL2), and the low driving voltage line and the second high driving voltage line ELVDD, wherein the first sub-pixel (PX, fig. 4) comprises: a first transistor (T1) inherently configured to generate a control current (any current to be a control current) according to the first data voltage (it is inherently having the first data voltage from the first data line DL1) of the first data line (DL1) and having a first gate electrode (G1); a transistor (T6) inherently configured to generate a driving current (Id) applied to a light emitting element (OLED) inherently according to the second data voltage (it is inherently having the second data voltage from the second data line DL2) of the second data line (DL2).
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Conclusion
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812