DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 01/16/2026 has been entered. Applicant's amendment has overcome
the objections to the Claims previously set forth in the Non-Final Office Action dated on 10/17/2025.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 01/16/2026, have been fully considered, the arguments are not persuasives and some of them are moot because do not apply to new ground of rejections with new references, US 20200091095 A1 to Jung, US 20210366873 A1 to Gandhi, being used in the current rejection, see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-17 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210091056 A1, hereinafter Yu, of the record) in view of Jung et al. (US 20200091095 A1, hereinafter Jung).
Re: Independent Claim 1, Yu discloses an electronic device (Fig. 24), comprising:
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Yu’s Figure 24-Annotated.
a first interconnection structure (210 a third interconnect structure in [0057], Fig. 24) extending along and centered on a first axis (horizontal direction, Fig. 24);
an electronic component (324 a processing die, when 324 is closer to the photonic package 100 than the memory die 326 in [0078], Fig. 24-Annotated) disposed over the first interconnection structure (210);
a photonic component (100 a photonic package in [0079], Fig. 24) disposed over the first interconnection structure (210); and
a first bridge component (50-R an interconnect device included in 250 in [0079], Fig. 24-Annotated) disposed under the first interconnection structure (210) and configured to electrically connect the electronic component (324) with the photonic component (100) through the first interconnection structure (210),
wherein the electronic component (324) is configured to transmit a first signal downwardly without passing (the signal is going up to reach the photonic package 100 in [0079], Fig. 24) the first bridge (50-R) component and the photonic component (100) is configured to transmit/receive a second signal to/from outside of the electronic device (in [0079], Fig. 24-Annotated), and wherein a transmission speed of the second signal is higher than a transmission speed of the first signal (wherein 100 incorporated an optical fiber 150 to allow optical signals and/or optical power to be transferred between the photonic package 100 and an optical fiber 150 in a higher speed in [0030,0080]).
Yu does not expressly disclose the first interconnection structure comprising conductive paths extending along and centered only on a second axis perpendicular to the first axis.
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Jung’s Figure 9-Annotated.
However, in the same semiconductor device field of endeavor, Jung discloses the first interconnection structure (240 a connection member including 245 in [0058], Fig. 9) comprising conductive paths (245 a redistribution layer in [0058], Fig. 9) extending along and centered only on a second axis (vertical direction, Fig. 9) perpendicular to the first axis (horizontal direction, Fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jung’s feature of the first interconnection structure comprising conductive paths extending along and centered only on a second axis perpendicular to the first axis to Yu’s device to perform various functions depending on a design of the redistribution layer ([0070], Jung).
Re: Claim 2, Yu modified by Jung discloses the electronic device of claim 1,
Yu modified by Jung does not expressly disclose wherein the electronic component is directly coupled to the first interconnection structure without an intervening carrier, and a backside surface of the photonic component is lower than a backside surface of the electronic component relative to the first interconnection structure.
However, in the same semiconductor device field of endeavor, Jung discloses wherein the electronic component (220 semiconductor chip in [0052], Fig. 9) is directly coupled to the first interconnection structure (240 a connection member including 245 in [0058], Fig. 9) without an intervening carrier (Fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jung’s feature of wherein the electronic component is directly coupled to the first interconnection structure without an intervening carrier to Yu’s device to perform various functions depending on a design of the redistribution layer ([0070], Jung).
Still, Yu modified by Jung does not expressly disclose a backside surface of the photonic component is lower than a backside surface of the electronic component relative to the first interconnection structure.
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Yu’s Figure 27-Annotated.
However, in the same semiconductor device field of endeavor, Yu discloses in a second embodiment, a backside surface of the photonic component (100-2 [0084], Fig. 27-Annotated) is lower than a backside surface of the electronic component (324-2 [0084] Fig. 27-Annotated) relative to the first interconnection structure (210-2 [0084], Fig. 27-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the YU’s feature of a backside surface of the photonic component is lower than a backside surface of the electronic component relative to the first interconnection structure to the combination of Yu and Jung to provides additional electrical routing ([0084], Yu).
Re: Claim 3, Yu modified by Jung discloses the electronic device of claim 1, wherein the first interconnection structure (210 Yu) includes a first circuit region (first circuit, Fig. 24-Annotated Yu) and a second circuit region (second circuit, Fig. 24-Annotated Yu), the first circuit region (first circuit Yu) is between the electronic component (324 Yu) and first bridge component (50-R Yu), and the second circuit region (second circuit Yu) is between the photonic component (100 Yu) and first bridge component (50-R Yu), wherein a circuit density of the second circuit region (second circuit Yu) is higher (wherein the second circuit includes more connections with 50-R Fig. 24-Annotated Yu) than a circuit density of the first circuit region (first circuit Yu).
Re: Claim 4, Yu modified by Jung discloses the electronic device of claim 2, wherein an active surface of the photonic component (100 Yu) and an active surface of the first bridge component (210 Yu) face toward each other (Fig. 24 Yu).
Re: Claim 5, Yu modified by Jung discloses the electronic device of claim 4, further comprising: an optical fiber (150 an optical fiber in [0030], Fig. 24 Yu) coupled to the backside surface (150 is vertically mounted over the photonic package 100 in [0033] Yu) of the photonic component (100 Yu).
Re: Claim 6, Yu modified by Jung discloses the electronic device of claim 1, wherein an overlapping area between the photonic component (100 Yu) and the first bridge component is larger than (Fig. 24 Yu) an overlapping area between the electronic component (324 Yu) and the first bridge component (50-R Yu).
Re: Claim 7, Yu modified by Jung discloses the electronic device of claim 1, further comprising: a memory (326 a memory die in [0078], Fig. 24-Annotated Yu); and a second bridge component (50-L an interconnect device included in 250 in [0079], Fig. 24-Annotated Yu) configured to electrically connect the electronic component (324 Yu) with the memory (326 Yu).
Re: Claim 8, Yu modified by Jung discloses the electronic device of claim 7, further comprising: an encapsulant (208 an encapsulant in [0055], Fig. 24 Yu) at least partially covering (Fig. 24 Yu) the first bridge component (50-R Yu) and the second bridge component (50-L Yu), wherein the encapsulant (208 Yu) supports the electronic component (324 Yu), the photonic component (100 Yu), and the memory (326 Yu).
Re: Claim 9, Yu modified by Jung discloses the electronic device of claim 7, wherein the first signal is transmitted without passing (the signal is going up to reach the photonic package 100 in [0079], Fig. 24 Yu) the second bridge component (100 Yu).
Re: Claim 10, Yu modified by Jung discloses the electronic device of claim 1, further comprising: a second interconnection structure (230 a fourth interconnect structure in [0066], Fig. 24 Yu) extending along and centered on the first axis; and an encapsulant (208 an encapsulant in [0055], Fig. 24 Yu) disposed between the first interconnection structure (210 Yu) and the second interconnection structure (230 Yu), wherein the first bridge component is at least partially embedded (Fig. 24 Yu) in the encapsulant (208 Yu).
Yu modified by Jung does not expressly disclose the second interconnection structure comprising conductive paths extending along and centered only on the second axis perpendicular to the first axis.
However, in the same semiconductor device field of endeavor, Jung discloses the second interconnection structure (240 a connection member including 245 in [0058], Fig. 9) comprising conductive paths (245 a redistribution layer in [0058], Fig. 9) extending along and centered only on the second axis (vertical direction, Fig. 9) perpendicular to the first axis (horizontal direction, Fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jung’s feature of the second interconnection structure comprising conductive paths extending along and centered only on the second axis perpendicular to the first axis to Yu’s device to perform various functions depending on a design of the redistribution layer ([0070], Jung).
Re: Claim 11, Yu modified by Jung discloses the electronic device of claim 10, further comprising: a memory (326 a memory die in [0078], Fig. 24-Annotated Yu) disposed over the first interconnection structure (210 Yu); and a second bridge component (50-L an interconnect device included in 250 in [0079], Fig. 24-Annotated Yu) at least partially embedded (Fig. 24-Annotated Yu) in the encapsulant (208 Yu).
Re: Claim 12, Yu modified by Jung discloses the electronic device of claim 11, further comprising: a plurality of conductive vias (206 through vias in [0066], Fig. 24, Yu) extending between the first interconnection structure (210, Yu) and the second interconnection structure (230 Yu).
Yu modified by Jung does not expressly disclose wherein a circuit density of the first interconnection structure is higher than a circuit density of the second interconnection structure.
However, the Applicant has not presented persuasive evidence that the claimed “a circuit density of the first interconnection structure higher than a circuit density of the second interconnection structure” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed circuit density of the first interconnection structure higher than a circuit density of the second interconnection structure). Also, the applicant has not shown that the claimed “difference of circuit density of the first interconnection structure higher than a circuit density of the second interconnection structure” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Jung discloses “an interconnection structure (240) comprising a redistribution layer (245), [0058], Fig. 9, in addition, Jung discloses that the design of the interconnection structure is depending on its functions [0070]”, therefore, the circuit density of the first interconnection structure higher than a circuit density of the second interconnection structure is a result effective variable. It has been held that is not inventive to discover the optimum circuit density of the first interconnection structure and the second interconnection structure by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a circuit density of the first interconnection structure higher than a circuit density of the second interconnection structure to the rest of the claimed invention to perform various functions depending on a design of the redistribution layer ([0070], Jung).
Re: Claim 13, Yu modified by Jung discloses the electronic device of claim 12,
Yu modified by Jung does not expressly disclose wherein a height of the plurality of conductive vias (206 Yu) is greater than a height of the first bridge component (50-R Yu).
However, the Applicant has not presented persuasive evidence that the claimed
“height of the plurality of conductive vias is greater than a height of the first bridge component” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed height of the plurality of conductive vias is greater than a height of the first bridge component). Also, the applicant has not shown that the claimed “difference of height of the plurality of conductive vias is greater than a height of the first bridge component” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Yu discloses “height of the plurality of conductive vias are the same than a height of the first bridge component, Fig. 24, in addition, Yu discloses that the first bridge component can be formed at different heights in [0054]”, therefore, the height of the plurality of conductive vias and the first bridge component is a result effective variable. It has been held that is not inventive to discover the optimum height of the plurality of conductive vias and the first bridge component by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add height of the plurality of conductive vias greater than a height of the first bridge component to the rest of the claimed invention to optimize and improve the electrical connections of the device.
Re: Claim 14, Yu modified by Jung discloses the electronic device of claim 11, wherein the second bridge component (50-L Yu) has a first surface exposed from the encapsulant (208 Yu) and contacting (Fig. 24-Annotated) the second interconnection structure (230 Yu), and wherein the first surface of the second bridge component (50-L Yu) is exclusive of contact terminals (TSVs 54 of the interconnect device 50 are optional in [0017], Yu).
Re: Claim 15, Yu modified by Jung discloses the electronic device of claim 14, wherein the second bridge component (50-L Yu) includes a passive component, and a redistribution layer (RDL) (the RDL included in 210, Fig. 24 Yu) is disposed over a second surface of the second bridge component (50-L Yu) to electrically connect the electronic component (324 Yu) with the memory (326 Yu).
Re: Claim 16, Yu modified by Jung discloses the electronic device of claim 10, wherein the first bridge component (50-R Yu) has a backside surface exposed from the encapsulant (208 Yu) and contacting (Fig. 24-Annotated) the second interconnection structure (230 Yu), and wherein the backside surface of the first bridge component (50-R Yu) is exclusive of contact terminals (TSVs 54 of the interconnect device 50 are optional in [0017], Yu).
Re: Claim 17, Yu modified by Jung discloses the electronic device of claim 16, wherein the first bridge component (50-R Yu) has an active surface and a lateral surface covered (Fig. 24-Annotated Yu) by the encapsulant (208 Yu).
Claim(s) 18-20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu in view of Jung and further in view of Gandhi et al. (US 20210366873 A1, hereinafter Gandhi).
Re: Claim 18, Yu modified by Jung discloses the electronic device of claim 10, further comprising: wherein the second interconnection structure (230 Yu) is disposed over the substrate (302 Yu);
Yu modified by Jung does not expressly disclose a first substrate; a second substrate disposed over and spaced apart from the first substrate, and two connectors disposed between the first substrate and the second substrate, wherein the two connectors are non-overlapped with the electronic component along a direction substantially perpendicular to an active surface of the electronic component.
However, in the same semiconductor device field of endeavor, Gandhi discloses a first substrate (134 a package substrate in [0022], Fig. 1); a second substrate (116 a RDL substrate in [0022], Fig. 1) disposed over (Fig. 1) and spaced apart from the first substrate (134), and two connectors (114L,144R signal feed throughs in [0022], Fig. 1-Annotated) disposed between the first substrate (134) and the second substrate (116), wherein the two connectors (114L,144R) are non-overlapped with the electronic component (104 a die in [0024], Fig. 1) along a direction (vertical direction, Fig. 1-Annotated) substantially perpendicular to an active surface (surface of 104, Fig. 1-Annotated) of the electronic component (104).
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Gandhi’s Figure 1-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Gandhi’s feature of a first substrate; a second substrate disposed over and spaced apart from the first substrate, and two connectors disposed between the first substrate and the second substrate, wherein the two connectors are non-overlapped with the electronic component along a direction substantially perpendicular to an active surface of the electronic component to the combination of Yu and Jung to allow connection between the top and bottom substrates ([0031], Gandhi).
Re: Claim 19, Yu modified by Jung and Gandhi discloses the electronic device of claim 18,
Yu modified by Jung and Gandhi does not expressly disclose a power regulating device disposed between the first substrate and the second substrate, wherein the power regulating device is overlapped with the electronic component along the direction.
However, in the same semiconductor device field of endeavor, Gandhi discloses a power regulating device (112 a chiplet including a power regulation/distribution system in [0032], Fig. 1) disposed between the first substrate (134) and the second substrate (116), wherein the power regulating device (112) is overlapped with the electronic component (104) along the direction (vertical direction, Fig. 1-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Gandhi’s feature of a power regulating device disposed between the first substrate and the second substrate, wherein the power regulating device is overlapped with the electronic component along the direction to the combination of Yu, Jung and Gandhi to regulate and distribute the power of the system ([0032], Gandhi).
Re: Claim 20, Yu modified by Jung and Gandhi discloses the electronic device of claim 18,
Yu modified by Jung and Gandhi does not expressly disclose wherein the power regulating device is disposed between the two connectors.
However, in the same semiconductor device field of endeavor, Gandhi discloses wherein the power regulating device (112 a chiplet including a power regulation/distribution system in [0032], Fig. 1) is disposed between (112 between connectors 114L and 114R, Fig. 1-Annotated) the two connectors (114L,144R).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Gandhi’s feature of wherein the power regulating device is disposed between the two connectors to the combination of Yu, Jung and Gandhi to regulate and distribute the power of the system ([0032], Gandhi).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pietambaram et al. (US 20220155539 A1) teaches “HIGH BANDWIDTH OPTICAL INTERCONNECTION ARCHITECTURES”. This document is related to an optical package comprises a package substrate, a photonics die, electronic die and coupled by a bridge.
Thacker et al. (US 20140321803 A1) teaches “HYBRID-INTEGRATED PHOTONIC CHIP PACKAGE WITH AN INTERPOSER”. This document is related to an optical integrated circuit (including an optical fiber) and an integrated circuit that are adjacent to each in the chip package.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898