DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claims 1, 12, and 15 filed on 12/04/2025 have been fully considered for examination based on their merits. The previously presented claims 2-11, 13-14, and 16-20 have been considered.
Response to Arguments
Applicant’s arguments, see Remarks, pages 10-20, filed 12/04/2025, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of TZENG.
Regarding Independent Claim(s) 1. Applicant argues (see Remarks, pages 16-17) that the MINZUAN art fails to disclose or suggest the amended feature, the S/D electrode or connection electrode being connected to lines such that a bias voltage line provides a bias voltage to each of first and second pixels and a reference voltage line provides a reference voltage to each of the first and second pixels. Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph.
Regarding Independent Claim(s) 12. Applicant argues (see Remarks, page 17), that the SONG in view of MINZUAN art fails to disclose or suggest the amended feature, an initialization voltage provides an initialization voltage to each of the first and second pixels. Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further review on SONG art, the amended feature is correctly mapped in this office action. Examiner also pointed out the amended feature, the reference voltage line providing a reference voltage to each of the first and second pixels is currently taught by TZENG.
Applicant also argues (see Remarks, page 18) that the previous Office Action that the initialization voltage line (330), and the upper semiconductor layer (420) are on different layers and a third insulating layer (833) in between them. Therefore SONG fails to disclose or suggest a second semiconductor layer that includes each of the first and second portions and connection portion. Examiner disagreed with this argument and point out that the annotations in Figure 4D clearly depicts the connection portions as conductive layers which are electrically connected to the initialization voltage line (330). Furthermore, the initialization voltage to each first and second pixels are mapped in this Office Action.
Regarding Independent Claim(s) 15. Applicant argues (see Remarks, page 17), that the combination of SONG and MINZUAN does not disclose or suggest the amended feature, a power voltage provides a power voltage to each of the first and second pixels. Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of TZENG.
Regarding Dependent Claim(s) 2-11, 13-14, and 16-20. The dependent claims 2-11, 13-14, and 16-20 follow similar arguments as independent claims 1, 12, and 15, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-9, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hee Rim Song et al, (hereinafter SONG), US 20190385522 A1 in view of Liu Minzuan et al, (hereinafter MINZUAN), CN 112768476 A, further in view of Bo-Shiang Tzeng et al, (hereinafter TZENG), US 20200243600 A1.
Regarding Claim 1, SONG teaches in Figures 4A-4D, a display device (Figure 1, 60), comprising:
a first semiconductor layer (Fig. 4A, 100, lower semiconductor layer) disposed on a substrate (Fig. 5, 810), and comprising a first portion (Fig. 4A, 110 first vertical portion; annotated Figure 4A), disposed in a first pixel area (PXi, one pixel, [0077]; annotated Figure 4A) including a first pixel (Figs. 1-3, 1, plurality of pixels), a second portion (Fig. 4A, 110 first vertical portion; annotated Figure 4A) disposed in a second pixel area (another pixel adjacent in a row direction, [0077]; annotated Figure 4A) including a second pixel (Figs. 1-3, 1, plurality of pixels), and a first connection portion (Fig. 4A, 120, second vertical portion; annotated Figure 4A) connecting the first portion and the second portion, and the first portion and the second portion have a shape symmetrical (annotated Figure 4A; [0077]) to each other based on a boundary (annotation Figure 4A; boundary defined by the column direction as a boundary between one pixel PXi and another pixel adjacent in the row direction is defined as a reference line, [0077]) between the first pixel area and the second pixel area;
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a second semiconductor layer (Figs. 4A-4D, 410, upper semiconductor pattern) disposed on the first semiconductor layer (Figs. 4A-4D/Fig. 5, 100, lower semiconductor layer), and comprising a first portion (annotated Figure 4C) disposed in the first pixel area (PXi, one pixel, [0077]; annotated Figure 4A/4C), a second portion (annotated Figure 4C) disposed in the second pixel area (another pixel adjacent in a row direction, [0077]; annotated Figure 4A/4C), and a connection portion (annotated Figure 4C) connecting the first portion and the second portion, and the first portion and the second portion have a shape symmetrical (annotated Figure 4C; [0077]) to each other based on the boundary (annotation Figure 4A; boundary defined by the column direction as a boundary between one pixel PXi and another pixel adjacent in the row direction is defined as a reference line, [0077]) between the first pixel area and the second pixel area.
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SONG does not explicitly disclose a display device comprising:
a bias voltage line disposed on the first semiconductor layer, electrically connected to the first connection portion of the first semiconductor layer, and extending in a second direction intersecting the first direction; and
a reference voltage line disposed on the second semiconductor layer, electrically connected to the connection portion of the second semiconductor layer, and extending in the second direction.
MINZUAN teaches in Figures 2A-2D, a display device (Fig. 1, 100) comprising:
a bias voltage line (Figs. 2A-2D, Vdd, operating voltage, [0120]) disposed on the first semiconductor layer (Fig. 4A, 404/409, first/second semiconductor layer is referred as a top gate structure having first gate electrode, G1 and second gate electrode, G2, [0114]), electrically connected to the first connection portion (Fig. 4A, 442, drain electrode) of the first semiconductor layer (Figs. 2A-2D as each pixel P11~Pmn in Fig. 1, [0102], in one embodiment, when the first source/drain electrode 441, Refer Fig. 4A, receives data signal (e.g. D1), the third source/drain electrode 443 receives an operating voltage, Vdd, [0120]; the first gate electrode G1 and the third gate electrode, G3 receive a scan signal, (e.g. S1); the first transistor, the second transistor and the third transistor (404/409/410 as in Fig. 4A) may be used as the switching transistor, 210, the driving transistor, 220 and the reset transistor, 230 respectively, as in Fig. 2A, [0120]), and extending in a second direction intersecting a first direction (annotated Figure 2A); and
a reference voltage line (Figs. 2A-2D, Vref, reference voltage, [0120]) disposed on the second semiconductor layer (Fig. 4A, 409/410, second/third semiconductor layer is referred as upper gate electrode structure having second gate electrode, G2 and third gate electrode, G3, [0114]), electrically connected to the connection portion (Fig. 4A, 447, Connection electrode) of the second semiconductor layer (Figs. 2A-2D as each pixel P11~Pmn in Fig. 1, [0102], in one embodiment, the fifth source/drain 446 receives a reference voltage, Vref, [0120]; the first gate electrode G1 and the third gate electrode, G3 receive a scan signal, (e.g. S1); the first transistor, the second transistor and the third transistor (404/409/410 as in Fig. 4A) may be used as the switching transistor, 210, the driving transistor, 220 and the reset transistor, 230 respectively, as in Fig. 2A, [0120]), and extending in the second direction (annotated Figure 2.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified SONG to incorporate the teachings of MINZUAN, such that a display device comprising: a bias voltage line disposed on the first semiconductor layer, electrically connected to the first connection portion of the first semiconductor layer, and extending in a second direction intersecting the first direction; and a reference voltage line disposed on the second semiconductor layer, electrically connected to the connection portion of the second semiconductor layer, and extending in the second direction. The operating voltage, Vdd, the operating voltage, Vss, the reference voltage, Vref and preset voltage, SCM may be provided by the gate driver, 110, the source drive, or other chips of the display device the pixel P11~Pmn each having a storage capacitor for storing a driving voltage and the driving voltage is used for light the corresponding light emitting diode (MINZUAN, [0102], [0106]).
SONG as modified by MINZUAN does not explicitly disclose a display device comprising: the bias voltage line providing a bias voltage to each of the first and second pixels; and the reference voltage line providing a reference voltage to each of the first and second pixels.
TZENG teaches a display device (Fig. 9, 20, display panel) comprising: the bias voltage line (Fig. 9, PL2, second power line) providing a bias voltage (high voltage level, [0048]) to each of the first (Fig. 9, PX1, pixel structure) and second pixels (Fig. 9, PX2, pixel structure); and the reference voltage line (Fig. 9, PL1, first power line, [0048]) providing a reference voltage (ground voltage level, [0048]) to each of the first (Fig. 9, PX1, pixel structure) and second pixels (Fig. 9, PX2, pixel structure).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have SONG as modified by MINZUAN to incorporate the teachings of TZENG, such that a display device comprising: the bias voltage line providing a bias voltage to each of the first and second pixels; and the reference voltage line providing a reference voltage to each of the first and second pixels, so that the fixed or floating potentials improve the resolution with the layout space defined by the display panel (TZENG, [0004], [0048]).
Regarding Claim 2, SONG as modified by MINZUAN and TZENG teaches the display device of claim 1.
SONG further teaches in Figures 4A-4D, the display device (Figure 1, 60), further comprising:
a first gate electrode ([0044-0045]) disposed on the first semiconductor layer (Fig. 4A, 100, lower semiconductor layer), wherein
a portion of the first gate electrode overlaps the first portion (annotated Figure 4A) of the first semiconductor layer to define a first bias transistor (Fig. 4A, T1 [0044-0045]) in a plan view (Fig. 4A), and another portion of the first gate electrode ([0044-0045]) overlaps the second portion (annotated Figure 4A) of the first semiconductor layer to define a second bias transistor (Fig. 4A, T1 [0044-0045]) in the plan view.
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MINZUAN further teaches in Figures 2A-2D, a display device (Fig. 1, 100), further comprising: a first gate electrode (Fig. 4A, G1) disposed on the first semiconductor layer (Fig. 4A, 404), wherein
a portion of the first gate electrode (Fig. 4A, G1) overlaps ([0113]) the first portion (annotated Figure 4A) of the first semiconductor layer (Fig. 4A, 404) to define a first bias transistor (annotated Figure 4A; Figs. 2A-2D as each pixel P11~Pmn in Fig. 1, [0102], in one embodiment, when the first source/drain electrode 441, Refer Fig. 4A, receives data signal (e.g. D1), the third source/drain electrode 443 receives an operating voltage, Vdd, [0120]; the first gate electrode G1 and the third gate electrode, G3 receive a scan signal, (e.g. S1); the first transistor, the second transistor and the third transistor (404/409/410 as in Fig. 4A) may be used as the switching transistor, 210, the driving transistor, 220 and the reset transistor, 230 respectively, as in Fig. 2A, [0120]), and another portion of the first gate electrode (Fig. 4A, G1) overlaps the second portion (annotated Figure 4A) of the first semiconductor layer to define a second bias transistor (annotated Figure 4A; Figs. 2A-2D as each pixel P11~Pmn in Fig. 1, [0102], in one embodiment, when the first source/drain electrode 441, Refer Fig. 4A, receives data signal (e.g. D1), the third source/drain electrode 443 receives an operating voltage, Vdd, [0120]; the first gate electrode G1 and the third gate electrode, G3 receive a scan signal, (e.g. S1); the first transistor, the second transistor and the third transistor (404/409/410 as in Fig. 4A) may be used as the switching transistor, 210, the driving transistor, 220 and the reset transistor, 230 respectively, as in Fig. 2A, [0120]).
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Regarding Claim 3, SONG as modified by MINZUAN and TZENG teaches the display device of claim 2.
SONG further teaches in Figures 4A-4D, a display device (Figure 1, 60), wherein the first connection portion (annotated Figure 4A) of the first semiconductor layer (Fig. 4A, 100, lower semiconductor layer) is a source area ([0044-0045]) of the first bias transistor (Fig. 4A, T1 [0044-0045]; annotated Figure 4A) and a source area of the second bias transistor (Fig. 4A, T2 [0044-0045]; annotated Figure 4A).
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MINZUAN further teaches in Figures 2A-2D, a display device (Fig. 1, 100), wherein the first connection portion (annotated Figure 4A) of the first semiconductor layer (Fig. 4A, 404) is a source area (Fig. 4A, S/D1, 441) of the first bias transistor (annotated Figure 4A) and a source area (Fig. 4A, S/D2, 442) of the second bias transistor (annotated Figure 4A).
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Regarding Claim 4, SONG as modified by MINZUAN and TZENG teaches the display device of claim 2.
SONG further teaches in Figures 4A-4D, a display device (Figure 1, 60), further comprising: an emitting initialization control line (Fig. 1, EL1 to ELn, emission control lines, [0028-0029]) disposed on the second semiconductor layer (Figs. 4A-4B, 220, emission control line), extending in the first direction (Fig. 4B, row direction, [0028]), and electrically connected to the first gate electrode (Figs. 1/4B, 220, [0044-0045], [0089-0094; annotated Figure 4B]).
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Regarding Claim 5, SONG as modified by MINZUAN and TZENG teaches the display device of claim 1.
SONG further teaches in Figures 4A-4D, a display device (Figure 1, 60), further comprising: an upper gate electrode ([0044-0045]) disposed on the second semiconductor layer (Figs. 4A-4D, 410, upper semiconductor pattern), a portion of the upper gate electrode overlaps the first portion (annotated Figure 4D) of the second semiconductor layer to define a first reference transistor (Fig. 4A, T4 [0044-0045]) in a plan view, and another portion of the upper gate electrode ([0044-0045]) overlaps the second portion (annotated Figure 4D) of the second semiconductor layer to define a second reference transistor (Fig. 4A, T4 [0044-0045]) in the plan view.
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Regarding Claim 6, SONG as modified by MINZUAN and TZENG teaches the display device of claim 5.
SONG further teaches in Figures 4A-4D, a display device (Figure 1, 60), further comprising: a lower gate electrode ([0044-0045]) disposed below the second semiconductor layer (Figs. 4A-4D, 410/420, upper semiconductor pattern), a portion of the lower gate electrode overlaps the first portion of the second semiconductor layer (annotated Figure 4D) and the portion of the upper gate electrode in the plan view, and another portion of the lower gate electrode overlaps the second portion (annotated Figure 4D) of the second semiconductor layer and the another portion of the upper gate electrode in the plan view.
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MINZUAN further teaches in Figures 2A-2D, a display device (Fig. 1, 100), further comprising: a lower gate electrode (Fig. 4A, G2) disposed below the second semiconductor layer (Figs. 4A, 409), a portion of the lower gate electrode overlaps the first portion of the second semiconductor layer (annotated Figure 4A) and the portion of the upper gate electrode (Fig. 4A, G3), and another portion of the lower gate electrode overlaps the second portion (annotated Figure 4A) of the second semiconductor layer and the another portion of the upper gate electrode.
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Regarding Claim 7, SONG as modified by MINZUAN and TZENG teaches the display device of claim 5.
MINZUAN further teaches in Figures 2A-2D, a display device (Fig. 1, 100), wherein the connection portion (Fig. 4A, 447) of the second semiconductor layer (Fig. 4A, 409) is a drain area (Fig. 4A, S/D3) of the first reference transistor (annotated Figure 4A) and a drain area (Fig. 4A, S/D3) of the second reference transistor (annotated Figure 4A).
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Regarding Claim 8, SONG as modified by MINZUAN and TZENG teaches the display device of claim 5.
MINZUAN further teaches in Figures 2A-2D, a display device (Fig. 1, 100), further comprising: a reference voltage control line (Fig. 2A, Vref) disposed on the second semiconductor layer (Fig. 4A, 409), extending in the first direction (annotated Figure 2A), and electrically connected to the upper gate electrode [0120].
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Regarding Claim 9, SONG as modified by MINZUAN and TZENG teaches the display device of claim 1.
MINZUAN further teaches in Figures 2A-2D, a display device (Fig. 1, 100), wherein the first semiconductor layer comprises a silicon semiconductor ([0112]), and the second semiconductor layer comprises an oxide semiconductor ([0004], [0125]).
Regarding Claim 12, SONG teaches in Figures 4A-4D, a display device (Figure 1, 60), comprising:
a first semiconductor layer (Fig. 4A, 100, lower semiconductor layer) disposed on a substrate (Fig. 5, 810), and comprising a first portion (Fig. 4A, 110 first vertical portion; annotated Figure 4A) disposed in a first pixel area (PXi, one pixel, [0077]; annotated Figure 4A) including a first pixel (Figs. 1-3, 1, plurality of pixels), a second portion (Fig. 4A, 110 first vertical portion; annotated Figure 4A) disposed in a second pixel area (another pixel adjacent in a row direction, [0077]; annotated Figure 4A) including a second pixel (Figs. 1-3, 1, plurality of pixels), and a first connection portion (Fig. 4A, 120, second vertical portion; annotated Figure 4A) connecting the first portion and the second portion, the first portion and the second portion have a shape symmetrical (annotated Figure 4A; [0077]) to each other based on a boundary (annotation Figure 4A; boundary defined by the column direction as a boundary between one pixel PXi and another pixel adjacent in the row direction is defined as a reference line, [0077]) between the first pixel area and the second pixel area;
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a second semiconductor layer (Figs. 4A-4D, 410, upper semiconductor pattern) disposed on the first semiconductor layer (Figs. 4A-4D/Fig. 5, 100, lower semiconductor pattern), and comprising a first portion (annotated Figure 4C) disposed in the first pixel area (PXi, one pixel, [0077]; annotated Figure 4A/4C), a second portion (annotated Figure 4C) disposed in the second pixel area (another pixel adjacent in a row direction, [0077]; annotated Figure 4A/4C), a connection portion (annotated Figure 4C) connecting the first portion and the second portion, a third portion (annotated Figure 4C) disposed in the first pixel area, and a fourth portion (annotated Figure 4C) disposed in the second pixel area and spaced apart from the third portion (annotated Figure 4C), the first portion and the second portion have a shape symmetrical (annotated Figure 4C; [0077]) to each other based on the boundary between the first pixel area and the second pixel area, and the third portion and the fourth portion have a shape symmetrical (annotated Figure 4C; [0077]) to each other based on the boundary (annotation Figure 4A; boundary defined by the column direction as a boundary between one pixel PXi and another pixel adjacent in the row direction is defined as a reference line, [0077]) between the first pixel area and the second pixel area;
an initialization voltage line (Figs. 1/4C, an initialization voltage line 330 supplying an initialization voltage (‘VINT’ in Figure 3) [0097-0099], [0112-0114], [0420]) disposed on the second semiconductor layer (Figs. 4A-4D, 410, upper semiconductor pattern), and electrically connected (Figs. 1/4C, [0097-0099], [0112-0114], [0420]) to the third portion (annotated Figure 4D; [0120]) of the second semiconductor layer and the fourth portion (annotated Figure 4D; [0120]) of the second semiconductor layer (Figs. 4A-4D, 410, upper semiconductor pattern), the initialization voltage line (Figs. 1/4C, an initialization voltage line 330 supplying an initialization voltage (‘VINT’ in Figure 3) [0097-0099], [0112-0114], [0420]) providing an initialization voltage ([0097]) to each of the first (Figs. 1-3, 1, plurality of pixels) and second pixels (Figs. 1-3, 1, plurality of pixels).
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SONG does not explicitly disclose a display device comprising:
a reference voltage line disposed on the second semiconductor layer, electrically connected to the connection portion of the second semiconductor layer, and extending in the second direction.
MINZUAN teaches in Figures 2A-2D, a display device (Fig. 1, 100) comprising:
a reference voltage line (Figs. 2A-2D, Vref, reference voltage, [0120]) disposed on the second semiconductor layer (Fig. 4A, 409/410, second/third semiconductor layer is referred as upper gate electrode structure having second gate electrode, G2 and third gate electrode, G3, [0114]), electrically connected to the connection portion (Fig. 4A, 447, Connection electrode) of the second semiconductor layer (Figs. 2A-2D as each pixel P11~Pmn in Fig. 1, [0102], in one embodiment, the fifth source/drain 446 receives a reference voltage, Vref, [0120]; the first gate electrode G1 and the third gate electrode, G3 receive a scan signal, (e.g. S1); the first transistor, the second transistor and the third transistor (404/409/410 as in Fig. 4A) may be used as the switching transistor, 210, the driving transistor, 220 and the reset transistor, 230 respectively, as in Fig. 2A, [0120]), and extending in the second direction (annotated Figure 2A); and
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified SONG to incorporate the teachings of MINZUAN, such that a display device comprising: a reference voltage line disposed on the second semiconductor layer, electrically connected to the connection portion of the second semiconductor layer, and extending in the second direction sot that operating voltage, Vdd, the operating voltage, Vss, the reference voltage, Vref and preset voltage, SCM may be provided by the gate driver, 110, the source drive, or other chips of the display device the pixel P11~Pmn each having a storage capacitor for storing a driving voltage and the driving voltage is used for light the corresponding light emitting diode (MINZUAN, [0102], [0106], [0120]).
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SONG as modified by MINZUAN does not explicitly disclose the display device comprising: the reference voltage line providing a reference voltage to each of the first and second pixels.
TZENG teaches a display device (Fig. 9, 20, display panel) comprising: the reference voltage line (Fig. 9, PL1, first power line, [0048]) providing the reference voltage (ground voltage level, [0048]) to each of the first (Fig. 9, PX1, pixel structure) and second pixels (Fig. 9, PX2, pixel structure).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have SONG as modified by MINZUAN to incorporate the teachings of TZENG, such that a display device comprising: the reference voltage line providing a reference voltage to each of the first and second pixels, so that the fixed or floating potentials improve the resolution with the layout space defined by the display panel (TZENG, [0004], [0048]).
Claim(s) 10,-11, and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over SONG in view of MINZUAN, further in view of TZENG, and further in view of Kim Sun-Ho et al, (hereinafter SUN-HO), WO 2020145502 A1.
Regarding Claim 10, SONG as modified by MINZUAN and TZENG teaches the display device of claim 1.
SONG further teaches in Figures 4A-4D, the display device (Figure 1, 60), further comprising: an inorganic insulation layer ([0106]) disposed between the first semiconductor layer (Fig. 4A, 404/409, first/second semiconductor layer is referred as a top gate structure having first gate electrode, G1 and second gate electrode, G2, [0114]), and the bias voltage line (Figs. 2A-2D, Vdd, operating voltage, [0120]).
SONG as modified by MINZUAN and TZENG does not teach, the display device, further comprising: an inorganic insulation layer having a groove surrounding the first pixel area and the second pixel area.
SUN-HO teaches a display device ([0019]), further comprising: an inorganic insulation layer having a groove surrounding the first pixel area and the second pixel area [0080-0089].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have SONG as modified by MINZUAN and TZENG to incorporate the teachings of SUN-HO, such that the display device, further comprising: an inorganic insulation layer having a groove surrounding the first pixel area and the second pixel area, so that grooves of the inorganic insulating layer can serve as an etching stop layer (SUN-HO, [0089]).
Regarding Claim 11, SONG as modified by MINZUAN, TZENG, and SUN-HO teaches the display device of claim 10.
SUN-HO teaches a display device ([0019]) of claim 10, further comprising: an organic insulation layer disposed on the inorganic insulation layer, and filling the groove of the inorganic insulation layer ([0087]).
Regarding Claim 13, SONG as modified by MINZUAN and TZENG teaches the display device of claim 11.
SONG further teaches in Figures 4A-4D, a display device (Figure 1, 60), wherein the initialization voltage line (Fig. 3/4C, VINT, 330, [0097]) comprises:
a horizontal initialization voltage line electrically connected (Figs. 1/4C, an initialization voltage line 330 supplying an initialization voltage (‘VINT’ in Figure 3) [0097-0099], [0112-0114], [0420]) to the third portion (annotated Figure 4D; [0120]) of the second semiconductor layer (Figs. 4A-4D, 410, upper semiconductor pattern) and the fourth portion (annotated Figure 4D; [0120]) of the second semiconductor layer, and extending in the first direction (the initialization voltage line 330 may extend to the neighboring pixel beyond the boundary of the pixel PXi along the row direction, [0098]); and
SONG as modified by MINZUAN and TZENG does not explicitly disclose a display device, wherein the initialization voltage line comprises: a vertical initialization voltage line electrically connected to the third portion of the second semiconductor layer.
SUN-HO teaches a display device ([0019]), wherein the initialization voltage line comprises: a vertical initialization voltage line (Figs 3/8, 131, VINT) electrically connected to the third portion (Fig. 18, Transistors T4/T7, annotated Figure 18, [0062]) of the second semiconductor layer (Figs. 4/6/11, AS1 to AS7, [0102]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have SONG as modified by MINZUAN and TZENG to incorporate the teachings of SUN-HO, such that a display device, wherein the initialization voltage line comprises: a vertical initialization voltage line electrically connected to the third portion of the second semiconductor layer, so that the initialization voltage connection line can connect a plurality of pixels arranged in the first direction and thus serve to supply electrical signals to a plurality of pixels (SUN-HO, [0133-0135]).
Regarding Claim 14, SONG as modified by MINZUAN and TZENG teaches the display device of claim 13.
SONG further teaches in Figures 4A-4D, a display device (Figure 1, 60), further comprising: a first bridge electrode (Fig. 4H, 640, data bridge electrode, [0124]) disposed on the second semiconductor layer (Figs. 4A-4D, 410, upper semiconductor pattern), electrically connecting (Fig. 3, DATA line is electrically connected to transistor, T2) the third portion (annotated Figure 4H) of the second semiconductor layer and the first portion (annotated Figure 4H) of the first semiconductor layer (Fig. 4A, 100, lower semiconductor layer), and electrically connected to each of the horizontal initialization voltage line and the vertical initialization voltage line (Fig. 3, DATA line connected VINT; Figs. 4C/4H, 330/640 VINT/Bridge electrode); and a second bridge electrode (Fig. 4H, 640) disposed on the second semiconductor layer, electrically connecting the fourth portion of the second semiconductor layer (Figs. 4A-4D, 410, upper semiconductor pattern) and the second portion (annotated Figure 4H) of the first semiconductor layer (Fig. 4A, 100, lower semiconductor layer), and electrically connected to the horizontal initialization voltage line (Fig. 3, DATA line connected VINT; Figs. 4C/4H, 330/640 VINT/Bridge electrode).
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Claim(s) 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over SONG, in view of Hyunchol Bang et al, (hereinafter BANG), US 20190280076 A1, further in view of MINZUAN, and further in view of TZENG.
Regarding Claim 15, SONG teaches in Figures 4A-4D, a display device (Figure 1, 60), comprising:
a first semiconductor layer (Fig. 4A, 100, lower semiconductor layer) disposed on a substrate (Fig. 5, 810), and comprising a first portion (Fig. 4A, 110 first vertical portion; annotated Figure 4A), disposed in a first pixel area (PXi, one pixel, [0077]; annotated Figure 4A) including a first pixel (Figs. 1-3, 1, plurality of pixels), a second portion (Fig. 4A, 110 first vertical portion; annotated Figure 4A) disposed in a second pixel area (another pixel adjacent in a row direction, [0077]; annotated Figure 4A) including a second pixel (Figs. 1-3, 1, plurality of pixels), and a first connection portion (Fig. 4A, 120, second vertical portion; annotated Figure 4A) connecting the first portion and the second portion, the first portion and the second portion have a shape symmetrical (annotated Figure 4A; [0077]) to each other based on a boundary (annotation Figure 4A; boundary defined by the column direction as a boundary between one pixel PXi and another pixel adjacent in the row direction is defined as a reference line, [0077]) between the first pixel area and the second pixel area;
a power voltage line (Figs. 1/3/4C, ELVDD/ELVSS, first supply voltage line/first power supply voltage/second power supply voltage, [0029], [0037], [0047]) disposed on the first semiconductor layer (Fig. 4A, 100, lower semiconductor layer), and electrically connected to the second connection portion of the first semiconductor layer (Figs. 1/3/4A/4C; annotated Figures 3/4A; see ELVDD connected to transistors T1, T5, T6 and T7 and compare with Figure 4C that these transistors are within the 100, lower semiconductor layer).
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SONG does not explicitly disclose a display device comprising:
a second connection portion connecting the first portion and the second portion and spaced apart from the first connection portion.
BANG teaches in Figure 11, a display device (Fig. 1, 10, display apparatus) comprising:
a second connection portion connecting the first portion and the second portion and spaced apart from the first connection portion (annotated Figure 11).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified SONG to incorporate the teachings of BANG, such that a display device comprising: a second connection portion connecting the first portion and the second portion and spaced apart from the first connection portion, so that the pixel circuits of a pair of pixels PX arranged in the same row and adjacent columns may be laterally symmetric with each other (BANG, [0132]).
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SONG as modified by BANG does not explicitly disclose a display device comprising:
a bias voltage line disposed on the first semiconductor layer, electrically connected tsso the first connection portion of the first semiconductor layer, and extending in a second direction intersecting the first direction; and
MINZUAN teaches in Figures 2A-2D, a display device (Fig. 1, 100) comprising:
a bias voltage line (Figs. 2A-2D, Vdd, operating voltage, [0120]) disposed on the first semiconductor layer (Fig. 4A, 404/409, first/second semiconductor layer is referred as a top gate structure having first gate electrode, G1 and second gate electrode, G2, [0114]), electrically connected to the first connection portion (Fig. 4A, 442, drain electrode) of the first semiconductor layer (Figs. 2A-2D as each pixel P11~Pmn in Fig. 1, [0102], in one embodiment, when the first source/drain electrode 441, Refer Fig. 4A, receives data signal (e.g. D1), the third source/drain electrode 443 receives an operating voltage, Vdd, [0120]; the first gate electrode G1 and the third gate electrode, G3 receive a scan signal, (e.g. S1); the first transistor, the second transistor and the third transistor (404/409/410 as in Fig. 4A) may be used as the switching transistor, 210, the driving transistor, 220 and the reset transistor, 230 respectively, as in Fig. 2A, [0120]), and extending in a second direction intersecting a first direction (annotated Figure 2A). and
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have SONG as modified by BANG to incorporate the teachings of MINZUAN, such that a display device comprising: a bias voltage line disposed on the first semiconductor layer, electrically connected to the first connection portion of the first semiconductor layer, and extending in a second direction intersecting the first direction so that the operating voltage, Vdd, the operating voltage, Vss, the reference voltage, Vref and preset voltage, SCM may be provided by the gate driver, 110, the source drive, or other chips of the display device the pixel P11~Pmn each having a storage capacitor for storing a driving voltage and the driving voltage is used for light the corresponding light emitting diode (MINZUAN, [0102]. [0106]).
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SONG as modified by BANG and MINZUAN does not explicitly disclose a display device comprising: the power voltage line providing a power voltage to each of the first and second pixels; and the bias voltage line providing a bias voltage to each of the first and second pixels.
TZENG teaches a display device (Fig. 9, 20, display panel) comprising: the power voltage line (Fig. 9, PL, included first power line and second power line) providing a power voltage (high voltage level, [0048]) to each of the first (Fig. 9, PX1, pixel structure) andss second pixels (Fig. 9, PX1, pixel structure); and the bias voltage line (Fig. 9, PL2, secossnd power line) providing a bias voltage (high voltage level, [0048]) to each of the first (Fig. 9, PX1, pixel structure) and second pixels (Fig. 9, PX2, pixel structure).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have SONG as modified by BANG, and MINZUAN to incorporate the teachings of TZENG, such that a display device comprising the power voltage line providing a power voltage to each of the first and second pixels; and the bias voltage line providing a bias voltage to each of the first and second pixels, so that the fixed or floating potentials improve the resolution with the layout space defined by the display panel (TZENG, [0004], [0048]).
Regarding Claim 16, SONG as modified by BANG, MINZUAN, and TZENG teaches the display device of claim 15.
SONG further teaches in Figures 4A-4D, the display device (Figure 1, 60), wherein the power voltage line (Figs. 1/3/4C, ELVDD/ELVSS, first supply voltage line/first power supply voltage/second power supply voltage, [0029], [0037], [0047]) further comprises: a horizontal power voltage line electrically connected to the second connection portion (Figs. 1/3/4A/4C; annotated Figures 3/4A; see ELVDD connected to transistors T1, T5, T6 and T7 and compare with Figure 4C that these transistors are within the 100, lower semiconductor layer) of the first semiconductor layer (Fig. 4A, 100, lower semiconductor layer), and extending in the first direction (Fig. 4L, column/row direction); and a vertical power voltage line electrically contacting the horizontal power voltage line (Figs. 1/3/4A/4C; annotated Figures 3/4A; see ELVDD connected to transistors T1, T5, T6 and T7 and compare with Figure 4C that these transistors are within the 100, lower semiconductor layer), and extending in the second direction (Fig. 4L, column/row direction).
Regarding Claim 17, SONG as modified by BANG, MINZUAN, and TZENG teaches the display device of claim 15.
SONG further teaches in Figures 4A-4D, the display device (Figure 1, 60), further comprising: a second gate electrode (annotated Figure 4A, Transistor T2 position) disposed on the first semiconductor layer (Fig. 4A, 100), a portion of the second gate electrode overlaps (annotated Figure 4A) the first portion (annotated Figure 4A, 110) of the first semiconductor layer to define a first emitting control transistor (Fig. 3, the first transistor T1 is connected to the anode electrode of the organic diode OLED via the sixth transistor, T6, [0047]) in a plan view (annotated Figure 4A), and another portion of the second gate electrode (annotated Figure 4A, Transistor T2 position) overlaps the second portion (annotated Figure 4A, 110) of the first semiconductor to define a second emitting control transistor (Fig. 3, the first transistor T1 receives the data signal according to the switching operation of the second transistor and supplies the driving current Id to the OLED [0047]) in the plan view (annotated Figure 4A).
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Regarding Claim 18, SONG as modified by BANG, MINZUAN, and TZENG teaches the display device of claim 17.
BANG further teaches in Figure 11, the display device (Fig. 1, 10, display apparatus), wherein the second connection portion (annotated Figure 11) of the first semiconductor layer ([0139]) is a source area of the first emitting control transistor and a source area of the second emitting control transistor (annotated Figure 11, Transistors T4/T5 with source S4/S5, Fig. 2, T4 or T5 connected to emission control line, 137, EM).
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Regarding Claim 19, SONG as modified by BANG, MINZUAN, and TZENG teaches the display device of claim 17.
SONG further teaches in Figures 4A-4D, the display device (Figure 1, 60), further comprising: a first hold capacitor lower electrode (Fig. 3/4C, Cst/340, storage capacitor, [0041]; annotated Figure 4C) disposed in the first pixel area (Fig. 3, 1, pixel, PXi, annotated Figure 4C), and spaced apart from the second gate electrode (Fig. 4B, 240; annotated Figure 4C);
a second hold capacitor lower electrode (Fig. 3/4C, Cst/340, storage capacitor, [0041]; annotated Figure 4C) disposed in the second pixel area (Fig. 3, 1, pixel, PXi, annotated Figure 4C), and spaced apart from the second gate electrode (Fig. 4B, 240; annotated Figure 4C) and the first hold capacitor lower electrode and the second hold capacitor lower electrode have a shape symmetrical to each other based on the boundary between the first pixel area and the second pixel area (annotated Figure 4C).
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BANG further teaches in Figure 11, the display device (Fig. 1, 10, display apparatus), a hold capacitor upper electrode (Figs. 4/11, Cst2/Cst) disposed on the first hold capacitor lower electrode (Figs. 4/11, Cst1/Cst) and the second hold capacitor lower electrode (Figs. 4/11, Cst2/Cst), and comprising a first portion overlapping the first hold capacitor lower electrode in a plan view (annotated Figure 11), a second portion overlapping the second hold capacitor lower electrode in the plan view (annotated Figure 11), and a connection portion connecting the first portion and the second portion (annotated Figure 11).
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Regarding Claim 20, SONG as modified by BANG, MINZUAN, and TZENG teaches the display device of claim 19.
SONG further teaches in Figures 4A-4D, a display device (Figure 1, 60), further comprising: a bridge electrode (Fig. 4H, 620/630/640, [0124]) disposed on the hold capacitor upper electrode, connecting the hold capacitor upper electrode and the second connection portion of the first semiconductor layer (annotated Figure 4H), and electrically connected to the power voltage line (Figs. 1/3, ELVDD/ELVSS).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20160190173 A1 – Figure 4
STATEMENT OF RELEVANCE – Schematic illustration of the power electrode at the connection portion (33) between the two transistors (34) and (35) to form a pixel circuit (Fig. 2).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812 /CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812
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