Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The amendment filed on 1/21/2026 has been fully considered and made of record in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/17/2026 was filed before the mailing date of the Final rejection on 4/16/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments with respect to claims 8 and 10-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 8-13 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2021/0057502) in view of Park et al. (US 2021/0280659).
With respect to Claim 8, Kim discloses a substrate (i.e. BSL) and a first transistor
(i.e. T1) disposed on the substrate. A light emitting diode (i.e. EL) disposed on the first
transistor and connected to the first transistor T1. At least one switching transistor (i.e.
Tsw) disposed on the substrate. The at least one switching transistor includes an active
layer (i.e. ACT) including a first conductive area CDR1, a second conductive area
CDR2, a first channel area CHR1, a second channel area CHR2, and a common
conductive area CSDR. The first conductive area and the second conductive area are
spaced apart from each other. The first channel area CHR1 and the second channel
area CHR2 are positioned between the first conductive area and the second conductive
area. The common conductive area CSDR are positioned between the first channel
area and the second channel area. A lower pattern CDP disposed under the active
layer ACT and overlapping the common conductive area CSDR and a portion the
second channel area (see paragraphs 85 and 161-172; Figs. 8 and 11).
Kim discloses the claimed invention except for a lower pattern that does not overlap the first channel area when viewed in a thickness direction of the substrate.
However, Park discloses a lower pattern (i.e. BML2) that does not overlap the first channel area (i.e. ACT 1) when viewed in a thickness direction of the substrate (i.e. SUB) (see Fig.15). Thus, Kim and Park have substantially the same environment of a lower pattern below the active layer while the lower pattern overlaps the second channel area. Therefore, one skilled in the art before the effective filing date of the claimed invention to incorporate the lower pattern under the active layer of Kim, since the lower pattern would facilitate in blocking light incident upon the first and second transistors as taught by Park.
With respect to Claim 9, Kim discloses wherein the lower pattern CDP is spaced
apart from the first channel area in a plan view (see Fig. 8).
With respect to Claim 10, Kim discloses the at least one switching transistor
includes a first sub-transistor T3_1 and a second sub-transistor T3_2 which are
connected to each other (see paragraph 162, Figs. 4A-4D).
With respect to Claim 11, Kim discloses the first sub-transistor includes the first
channel area CHR1 and a first gate electrode overlapping the first channel area (see
Fig. 8).
With respect to Claim 12, Kim discloses the second sub-transistor includes the
second channel area CHR2 and a second gate electrode overlapping the second
channel area (see Fig. 8).
With respect to Claim 13, Kim discloses an upper pattern GE_1, GE2_1disposed
on the active layer, overlapping the common conductive area CSDR, and spaced apart
from the first channel area CHR1 and the second channel area CHR2 in a plan view
(see Fig. 8)
With respect to Claim 15, Kim discloses a power supply line disposed on the at
least one switching transistor (see paragraph 156, 157, and 210).
With respect to Claim 16, Kim discloses the power supply line is connected to the
lower pattern and the upper pattern (see paragraph 113 and 114; Fig. 8).
With respect to Claim 17, Kim discloses the active layer further includes an active
pattern ACT extending from the first channel area and the second channel area. The
first transistor includes the active pattern and a first electrode disposed on the active
pattern ACT and overlapping the active pattern (see Fig. 8).
With respect to Claim 18, Kim discloses the at least one switching transistor
includes at least one selected from a second transistor T2, a third transistor T3, and a
fourth transistor T4. The second transistor includes a second electrode spaced apart
from the first electrode, the third transistor includes a third electrode spaced apart from
the first electrode and the second electrode, and the fourth transistor includes a fourth
electrode spaced apart from the first electrode, the second electrode, and the third
electrode (see paragraphs 98-106; Figs. 4A-4D).
With respect to Claim 19, Kim discloses the third transistor T3 is defined by the
first channel area, the second channel area, and the common conductive area, and the
first electrode is connected to the first channel area (see paragraphs 162, 202).
With respect to Claim 20, Kim discloses the fourth transistor T4 is defined by the
first channel area, the second channel area, and the common conductive area, and the
first electrode is connected to the first channel area (see paragraphs 162, 202)
Allowable Subject Matter
8. Claim 14 is objected to as being dependent upon a rejected base claim, but
would be allowable if rewritten in independent form including all of the limitations of the
base claim and any intervening claims.
The following is a statement of reasons for the indication of allowance subject
matter: none of the prior art of record does not teach or suggest the combination of the
lower pattern defines a first capacitor with the common conductive area and the upper
pattern defines a second capacitor with the common conductive area in claim 14.
The prior art made of record and not relied upon is cited primarily to show the
product of the instant invention.
Conclusion
9. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/April 16, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897
Prosecution Insights