DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous rejection: 1 through 20 rejected
Present rejection: Claims 1 through 5, 7, 8, 9, and 11 through 20.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation "the second IC die" in line 6. There is insufficient antecedent basis for this limitation in the claim. The claim previously recited “a second one of the IC dies” in line 4.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koganti (US 10886921) in view of Goto (US 2021/0313004).
Regarding claim 1.
Koganto teaches:
An integrated circuit (IC) device, comprising:
a first IC die (fig 2:104; [column 7 lines 25-30]) comprising functional circuitry (fig 2:224; [column 9 lines 25-30]) and configurable interface circuitry (fig 2:234; [column 9 lines 50-55]), wherein the configurable interface circuitry (fig 2:234; [column 9 lines 50-55] and configured by configuration logic (fig 2:254[column 10 lines 15-20]) comprises;
configuration memory (fig 2; [column 12 lines 40-45]) configured to store configuration values (state data of configuration data[column 12 lines 25-30] which is used by the configuration logic [column 10 lines 25-30] to configure the interface circuitry [column 12 lines 50-55]);
output circuitry configured to route an output node of the functional circuitry (fig 2:224; [column 9 lines 25-30]) to a selectable one of the first IC die based on the configuration values (; [column 12 lines 20-40]).;
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Koganti does not teach multiple nodes of the first IC die.
Goto teaches:
output circuitry (fig 1:sel2; [para 0052]) configured to route an output node of the functional circuitry (fig 1:MCA2,RCA2; [para 0048]) to a selectable one of multiple output nodes of the first IC die (fig 1:MD2; [para 0052]) based on the configuration;
and input circuitry (fig 1:MUX2; [para 0054]) configured to route a selectable one of an output node of the first IC die (fig 1:MD2; [para 0052]) and an input node of the first IC die (fig 1:MD2; [para 0052]) to-the functional circuitry (fig 1:MCA2,RCA2; [para 0052]) based on the configuration.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the circuitry to comprise numerous nodes and connections in order that more data can be transferred between devices, mere duplication of parts has no patentable significance. MPEP 2144.VI.B. Further, circuitry routing signals from the functional circuitry output to the function circuitry input in order that a redundant cell region can be used to repair in case a region fails (paragraph 6).
Regarding claim 2.
Koganti in view of Goto teaches the IC device of claim 1, further
Goto teaches:
a first set of the output nodes of the first IC die (fig 1:MD2; [para 0028]) are configured to align with input nodes of a second IC die (fig 1:MD1; [para 0028]);
and a first set of input nodes of the first IC die (fig 1:MD2; [para 0028]) are configured to align with output nodes of the second IC die (fig 1:MD1; [para 0028]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide more connections between die to increase communication, aligning the input and output nodes amongst die enables the correct nodes to connect and thereby enable transmission of data. Further, mere duplication of parts has no patentable significance. MPEP 2144.VI.B.
Regarding claim 3.
Koganti in view of Goto teaches the IC device of claim 2, further
Goto teaches:
a second set of output nodes of the first IC die (fig 1:MD2; [para 0028]) are configured to align with input nodes of a third IC die (fig 1:MD3; [para 0028]);
and a second set of input nodes of the first IC die (fig 1:MD2; [para 0028]) are configured to align with output nodes of the third IC die (fig 1:MD3; [para 0028]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide more connections between die to increase communication, aligning the input and output nodes amongst die enables the correct nodes will connect and thereby enable transmission of data. Further, mere duplication of parts has no patentable significance. MPEP 2144.VI.B.
Claim(s) 4, 5, 7, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koganti (US 10886921) in view of Goto (US 2021/0313004) as applied to claim 1 and further in view of Teller (US 2004/0240283).
Regarding claim 4.
Koganti in view of Goto teaches the IC device of claim 1, above.
Koganti in view of Goto does not teach the number of inputs from the functional circuitry to the multiplexers.
Teller teaches:
the output circuitry (fig 9; [para 0060]) comprises multiplexer circuitry (fig 9:2a-2d; [para 0060]) configured to receive m inputs (fig 9:; [para 0060]) from the functional circuitry (fig 9:memory; [para 0060]) and to route n (fig 9:11a-d; [para 0060]) of the inputs to respective ones of the selectable output nodes (fig 9:16; [para 0060]) of the first IC die (fig 4,9:chip; [para 0060]); m and n are positive integers; m is greater than n; and n is greater than one.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for there to be more inputs than outputs and more outputs than 1 in order to increase the functionality of the device be providing more data paths. Further, mere duplication of parts has no patentable significance. MPEP 2144.VI.B.
Regarding claim 5.
Koganti in view of Goto in view of Teller teaches the IC device of claim 4, further
Teller teaches:
m equals 32 (fig 9:3; [para 0060]);
and n equals 4 (fig 9:11a-d; [para 0060]).
Differences in the number of inputs and outputs will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such input and output numbers are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph), and these numbers of inputs and outputs has been used in similar devices in the art (see, e.g., Teller) it would have been obvious to one of ordinary skill in the art to use these values in the device.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 7.
Koganti in view of Goto in view of Teller teaches the IC device of claim 4, further
Teller teaches:
wherein the multiplexer circuitry comprises: a first set of n multiplexer circuits (fig 9:2a-2d; [para 0060]), each configured to receive a respective subsets of the m inputs (fig 9:; [para 0060]) from the functional circuitry (fig 9:memory; [para 0060]);
and a second set of n multiplexer circuits (fig 9:9a-9d; [para 0060]), each configured to receive n outputs (fig 9:7a-7d; [para 0060]) of the first set of multiplexer circuits (fig 9:2a-2d; [para 0060]) and to provide an output (fig 9:11a-11d; [para 00060]) to a respective selected one of the n output nodes (fig 9:16; [para 0060]) of the first IC die;
wherein the multiplexer circuits of the first (fig 9:2a-2d; [para 0060]) and second sets of multiplexer circuits (fig 9:9a-9d; [para 0060]) are individually controllable (fig 9:3,19; [para 0060,0062]) based on the configuration values (fig 9:4,20; [para 0060,0062]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for there to be layers of controllable multiplexer controlling numerous data paths to increase the functionality of the device be providing more data paths. Further, mere duplication of parts has no patentable significance. MPEP 2144.VI.B.
Regarding claim 8.
Koganti in view of Goto in view of Teller teaches the IC device of claim 7, further
Goto teaches:
the output circuitry further comprises a bus (fig 1:DT3; [para 0029]);
the n outputs of the first set of multiplexer circuits (fig 1:sel3; [para 0032]) are coupled to respective bit lines of the bus (fig 1:DT3; [para 0029]);
and the bit lines of the bus are coupled to respective inputs of each multiplexer of the second set of n multiplexer circuits (fig 1:mux3; [para 0032]).
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Teller teaches:
the output circuitry further comprises a bus (fig 9:17; [para 0060]);
the outputs of the first set of multiplexer circuits (fig 9:2a-2d; [para 0060]) are coupled to respective bit lines (fig 9:16; [para 0060]) of the bus (fig 9:17; [para 0060]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koganti (US 10886921) in view of Goto (US 2021/0313004) in view of Teller (US 2004/0240283) as applied to claim 8 and further in view of Kirsch (US 2017/0243623).
Regarding claim 9.
Koganti in view of Goto in view of Teller teaches the IC device of claim 8, above:
Teller teaches:
the first set of n multiplexer circuits comprises multiplexer circuits (fig 9:2a-2d; [para 0060]);
and the second set of n multiplexer circuits comprises 4:1 multiplexer circuits (fig 9:9a-9d; [para 0060]).
Koganti in view of Goto in view of Teller does not teach an 8:1 multiplexer.
Kirsch teaches:
an 8:1 multiplexer (fig 17; [para 0091])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the multiplexer to comprise 8:1 in order to increase the amount of the data the device can handle by controlling more lines of data.
Claim(s) 11, 13, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koganti (US 10886921) in view of Goto (US 2021/0313004).
Regarding claim 11.
Koganti teaches:
An integrated circuit (IC) device, comprising:
first (fig 2:106; [column 7 lines 25-30]) and second (fig 2:108; [column 7 lines 25-30]) IC dies in a stacked configuration (fig 2; [column 7 lines 20-25]), wherein: the first IC die (fig 2:106; [column 7 lines 25-30]) comprises first functional circuitry (fig 2:226; [column 9 lines 25-30]), first configurable interface circuity (fig 2:236; [column 9 lines 50-55] configured by configuration logic (fig 2:254; [column 10 lines 15-20])), and first configuration memory (fig 2; [column 12 lines 40-45])configured to store first configuration values (state date of configuration date [column 12 lines 25-30] which is used by the configuration logic [column 10 lines 25-30] to configure the interface circuitry [column 12 lines 55-55]);
and the first configurable interface circuity (fig 2:236; [column 9 lines 50-55]) is configured to route an output node of the first functional circuitry to a selectable one nodes of the first IC die based on the configuration values (; [column 12 lines 20-40])., .
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Koganti does not teach multiple nodes
Goto teaches:
the interface circuity (fig 1:sel 2; [para 0052]) is configured to route output node of the first functional circuitry (fig 1:MCA2,RCA2; [para 0048]) to a selectable one of multiple output nodes of the first IC die (fig 1:MD2; [para 0052]), and to route a selectable one of an output node of the first IC die (fig 1:MD2; [para 0052]) and an input node of the first IC die (fig 1:MD2; [para 0052]) to an input node of the first functional circuitry (fig 1:MCA2,RCA2; [para 0048])based on configuration.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the circuitry to comprise numerous nodes and connections in order that more data can be transferred between devices, mere duplication of parts has no patentable significance. MPEP 2144.VI.B. Further, circuitry routing signals from the functional circuitry output to the function circuitry input in order that a redundant cell region can be used to repair in case a region fails (paragraph 6).
Regarding claim 13.
Koganti in view of Goto teaches the IC device of claim 11, above
Koganti teaches:
the second IC die (fig 2:108; [column 7 lines 25-30]) comprises second functional circuitry (fig 2:229; [column 9 lines 25-30]), second configurable interface circuitry (fig 2:238; [column 9 lines 50-55]), and second configuration memory (fig 2; [column 12 lines 40-45]) configured to store second configuration values (; [column 12 lines 3-40]);
and the second configurable interface circuity (fig 2:238; [column 9 lines 50-55])
Goto teaches:
the second IC die (fig 1:MD3; [para 0028]) comprises second functional circuitry (fig 1:MCA3,RCA3; [para 0037]), second configurable interface circuitry (fig 1:sel3,mux3; [para 0032]); and the second configurable interface circuity (fig 1:sel3,mux3; [para 0032]) is configured to route an output node of the second functional circuitry (fig 1:MCA3,RCA3; [para 0037]) to a selectable one of multiple output nodes of the second IC die (fig 3:MD3; [para 0028]) and to route a selectable one of an output node of the second IC die (fig 3:MD3; [para 0028])and an input node of the second IC die (fig 1:MD3; [para 0028]) to an input node of the second functional circuitry (fig 1:MCA3,RCA3; [para 0037]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the circuitry route signals from the functional circuitry output to the function circuitry input in order that a redundant cell region can be used to repair in case a region fails (paragraph 6). Further, mere duplication of parts (multiple nodes) has no patentable significance. MPEP 2144.VI.B.
Regarding claim 14
Koganti in view of Goto teaches the IC device of claim 11, further
Goto teaches:
a first set of the output nodes of the first IC die (fig 1:MD2; [para 0028]) are configured to align with input nodes of a second IC die (fig 1:MD1; [para 0028]);
and a first set of input nodes of the first IC die (fig 1:MD2; [para 0028]) are configured to align with output nodes of the second IC die (fig 1:MD1; [para 0028]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide more connections between die to increase communication, aligning the input and output nodes amongst die enables the correct nodes will connect and thereby enable transmission of data. Further, mere duplication of parts has no patentable significance. MPEP 2144.VI.B.
Regarding claim 15.
Koganti in view of Goto teaches the IC device of claim 14, further
Koganti teaches
a third IC die (fig 2:104; [column 7 lines 25-30]) in the stacked configuration, : .
Goto teaches:
comprising a third IC die (fig 1:MD3; [para 0028]) in the stacked configuration (fig 1; [para 0028]), wherein: a second set of the output nodes of the first IC die (fig 1:MD2; [para 0028]) are configured to align with input nodes of the third IC die (fig 1:MD3; [para 0028]]); and a second set of the input nodes of the first IC die (fig 1:MD2; [para 0028]) are configured to align with output nodes of the third IC die (fig 1:MD3; [para 0028]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide more connections between die to increase communication, aligning the input and output nodes amongst die enables the correct nodes will connect and thereby enable transmission of data. Further, mere duplication of parts has no patentable significance. MPEP 2144.VI.B.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koganti (US 10886921) in view of Goto (US 2021/0313004) as applied to claim 11 and further in view of Teller (US 2004/0240283).
Regarding claim 12.
Koganti in view of Goto teaches the IC device of claim 11, above
Koganti in view of Goto does not detail the structure of configurable interface circuitry
Teller teaches
the configurable interface circuitry comprises multiplexer circuitry (fig 9:2a-2d; [para 0060]) configured to receive m inputs from the functional circuitry (fig 9:memory; [para 0060]) and to route n of the inputs to respective ones of the selectable output nodes (fig 9:16; [para 0060]) of the first IC die (fig 9; [para 0060]); m and n are positive integers; m is greater than n; and n is greater than one.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for there to be more inputs than outputs and more outputs than 1 in order to increase the functionality of the device be providing more data paths. Further, mere duplication of parts has no patentable significance. MPEP 2144.VI.B.
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koganti (US 10886921) in view of Goto (US 2021/0313004).
Regarding claim 16.
Koganti teaches
An integrated circuit (IC) device, comprising:
multiple IC dies (fig 2:104,106,108; [column 7 lines 25-30]) in a stacked configuration (fig 2; [column 7 lines 20-25]), wherein each of the IC dies (fig 2:104,106,108; [column 7 lines 25-30]) comprises functional circuitry (fig 2:224,226,228; [column 9 lines 20-30]), and configurable interface circuity (fig 2:234,236,238; [column 9 lines 40-45] configured by configuration logic (fig 2:254; [column 10 lines 15-20]), and configuration memory (fig 2; [column 12 lines 40-45]) configured to store configuration values (state date of configuration data; [column 12 lines 25-30] which is used by the configuration logic [column 10 lines 25-30] to configure the interface circuitry [column 12 lines 50-55]), and wherein the configurable interface circuity (fig 2:236; [column 9 lines 40-45]) of a first one of the IC dies (fig 2:106; [column 7 lines 25-30]) comprises;
output circuitry configured based on the configuration values (; [column 12 lines 20-40]);
and input circuitry based on the configuration values (; [column 12 lines 20-40]).
Koganti does not detail the node routing.
Goto teaches:
output circuitry (fig 1:SEL2; [para 0052]) configured to route n output nodes of the functional circuitry (fig 1:MCA2,RCA2; [para 0035]) of the first IC die (fig 1:MD2; [para 0028]) to respective selectable ones of n output nodes of the first IC die (fig 1:MD2; [para 0028]);
and input circuitry (fig 1:MUX2; [para 0071]) configured to route a selectable one of an output node of the first IC die (fig 1:MD2; [para 0028]) and an input node of the first IC die (fig 1:MD2; [para 0028]) to the functional circuitry of (fig 1:MCA2,RCA2; [para 0035])the first IC die (fig 1:MD2; [para 0028]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the circuitry route signals from the functional circuitry output to the function circuitry input in order that a redundant cell region can be used to repair in case a region fails (paragraph 6). Further, mere duplication of parts (multiple nodes) has no patentable significance. MPEP 2144.VI.B.
Regarding claim 17.
Koganti in view of Goto teaches the IC device of claim 16, further
Goto teaches:
a first set of the output nodes of the first IC die (fig 1:MD2; [para 0028]) are configured to align with input nodes of a second one of the IC dies (fig 1:MD1; [para 0028]);
and a first set of input nodes of the first IC die (fig 1:MD2; [para 0028]) are configured to align with output nodes of the second IC die (fig 1:MD1; [para 0028]) based on configuration.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide more connections between die to increase communication, aligning the input and output nodes amongst die enables the correct nodes will connect and thereby enable transmission of data. Further, mere duplication of parts has no patentable significance. MPEP 2144.VI.B.
Claim(s) 18, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koganti (US 10886921) in view of Goto (US 2021/0313004) as applied to claim 16 and further in view of Teller (US 2004/0240283)
Regarding claim 18.
Koganti in view of Goto teaches the IC device of claim 16, above
Koganti in view of Goto does not teach number of inputs for the multiplexers in the interface circuitry
Teller teaches:
the output circuitry (fig 9; [para 0060]) comprises: multiplexer circuitry (fig 9:2a-2d; [para 0060]) configured to receive m inputs from the functional circuitry (fig 9:memory; [para 0060])and to route a selectable subset of n of the m inputs to the respective ones of the n output nodes (fig 9:16; [para 0060]) of the first IC die (fig 4,9:chip; [para 0060]);
m and n are positive integers; m is greater than n; and n is greater than one.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for there to be more inputs than outputs and more outputs than 1 in order to increase the functionality of the device be providing more data paths. Further, mere duplication of parts has no patentable significance. MPEP 2144.VI.B.
Regarding claim 19.
Koganti in view of Goto in view of Teller teaches the IC device of claim 18, above
Teller teaches:
the multiplexer circuitry comprises:
a first set of n multiplexer circuits (fig 9:2a-2d; [para 0060]), each configured to receive a respective subsets of the m inputs from the functional circuitry (fig 9:memory; [para 0060]) of the first IC die (fig 4:chip; [para 0060]);
and a second set of n multiplexer circuits (fig 9:9a-9d; [para 0060]), each configured to receive n outputs of the first set of multiplexer circuits (fig 9:2a-2d; [para 0060]) and to provide an output to a respective selected one of the n output nodes (fig 9:16; [para 0060]) of the first IC die (fig 4:chip; [para 0060]);
wherein the multiplexer circuits of the first (fig 9:2a-2d; [para 0060]) and second (fig 9:9a-9d; [para 0060]) sets of multiplexer circuits are individually controllable based on the configuration values (fig 9:4,20; [para 0061,0062]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for to provide sets of individually controllable multiplexers in order to increase the functionality of the device be providing more data paths. Further, mere duplication of parts has no patentable significance. MPEP 2144.VI.B.
Regarding claim 20.
Koganti in view of Goto in view of Teller teaches the IC device of claim 19, above
Goto teaches:
the output circuitry further comprises a bus (fig 1:DT3; [para 0029]);
the n outputs of the first set of multiplexer circuits (fig 1:sel3; [para 0032]) are coupled to respective bit lines of the bus (fig 1:DT3; [para 0029]);
and the bit lines of the bus (fig 1:DT3; [para 0029]) are coupled to respective inputs of each multiplexer of the second set of n multiplexer circuits (fig 1:mux3; [para 0032]).
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Teller teaches:
the output circuitry further comprises a bus (fig 9:17; [para 0060]);
the outputs of the first set of multiplexer circuits (fig 9:2a-2d; [para 0060]) are coupled to respective bit lines (fig 9:16; [para 0060]) of the bus (fig 9:17; [para 0060]).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Newly applied reference combination Koganti (US 10886921) in view of Goto (US 2021/0313004) anticipates the claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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