DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 2021/0233931 A1, hereinafter Lai ‘931), in view of the following arguments.
With respect to Claim 1 Lai ‘931 discloses a memory device (Fig 1-3, 4A-10A), comprising:
a stack structure (10, Fig 1, Para [0015]) disposed above a substrate (Para [0015] discloses substrate under dielectric 102 in Fig 1)), wherein the stack structure (10) comprises a plurality of stacks (A and B, Fig 1, Para [0015]) and a plurality of isolation layers (110, Fig 1, Para [0015]) alternating with each other (Fig 1 and Para [0015] disclose layers 110 and A and B alternating), and each stack (A and B) comprises:
a first source and drain layer (106A-1, Fig 1, Para [0015] discloses 106A-1 as N-type of P-type dope polycrystalline semiconductor material);
an insulating layer (108A, Fig 1, Para [0015]), disposed on the first source and drain layer (106A-1)(Fig 1 discloses 108A over 106A-1);
a second source and drain layer (106A-2, Fig 1, Para [0015] discloses 106A-1 as N-type of P-type dope polycrystalline semiconductor material), disposed on the insulating layer (108A)(Fig 1 discloses 106A-2 over 108A); and
a channel layer (132, Fig 8A, Para [0025]), disposed on a sidewall of the insulating layer (108A)(Fig 8A discloses 132 on side wall of 108A (Note: 108A’ in Fig 8A is the nomenclature of the recessed 108A per Para [0025]), wherein a lower surface (bottom of 132) of the channel layer (132) is connected to the first source and drain layer (106A-1)( Fig 1, Para [0030] discloses 132 contacting 106A-1), and an upper surface (top of 132) of the channel layer (132) is connected to the second source and drain layer (106A-2)( Fig 1, Para [0030] discloses 132 contacting 106A-2);
a gate pillar (145, Fig 9A, Para [0027]), extending through the stack structure (A and B)(Fig 9A discloses 145 extending through stack); and
a charge storage structure (140, Fig 9A, Para [0026] discloses 140 as an ONO charge storage layer), disposed between the channel layer (132) and the gate pillar (145)(Fig 9A discloses 140 between 132 and 145),
But Lai ‘931 fails to explicitly disclose wherein the first source and drain layer includes an interface therein, and the second source and drain layer includes an interface therein.
Nevertheless, in an embodiment (Fig 1-3, 4A-10A of Lai ‘931), Lai ‘931 teaches wherein the first source and drain layer (106A-1) includes an interface therein (Para [0016] discloses layers within film stacks A and B (which includes 106A-1) of Fig 1 as deposited by an ALD process which would impart an interface as described below), and the second source and drain layer (106A-2) includes an interface therein (Para [0016] discloses layers within film stacks A and B (which includes 106A-2) of Fig 1 as deposited by an ALD process which would impart an interface as described below).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the teaching of Lai ‘931’s further embodiment where an ALD process is used to create first and second source and drain layers including an interface therein into Lai’ ‘931’s device. The embodiment of Lai ‘931 (taught in Para [0016]) presents using ALD to deposit the layers of stacks A and B, which include source and drain layers 106-1 and 106-2. A person of ordinary skill in the art would recognize that ALD is a process which deposits material in layers with precise thickness control. The ordinary artisan then would have been motivated to modify Lai ‘931 to use the ALD process taught in the further embodiment of Lai ‘931 as it improves the manufacturing process by enabling precise thickness control for the layers in the stack of Lai ‘931. For purposes of this Office Action, Examiner treats a first subset of a plurality of the ALD process deposited layers to form first source and drain layers 106-1 and a second subset of a plurality of the ALD process deposited layers to form first source and drain layers 106-1. An interface will exist between the first subset of the plurality of layers and the second subset of the plurality of layers. Similarly Examiner treats a first subset of a plurality of the ALD process deposited layers to form second source and drain layers 106-2 and a second subset of a plurality of the ALD process deposited layers to form second source and drain layers 106-2. An interface will exist between the first subset of the plurality of layers and the second subset of the plurality of layers. Therefore using the ALD process to deposit the first and second subset of layers of first source and drain layers 106-1 taught by this embodiment will result in the first source and drain layer 106-1 including an interface therein and using the ALD process to deposit the first and second subset of layers of second source and drain layers 106-2 taught by this embodiment will result in the second source and drain layer 106-2 including an interface therein.
With respect to Claim 3 Lai ‘931 discloses all limitations of the memory device according to claim 1,and Lai ‘931 further discloses wherein a sidewall (left side of 106A-1) of the first source and drain layer (106A-1) and the second source and drain layer (106A-2) is aligned with a sidewall (left side of 132) of the channel layer (132)(Fig 9A discloses left side of 132 is aligned with left side of 106A-1 and left side of 106A-2).
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With respect to Claim 4 Lai ‘931 discloses all limitations of the memory device according to claim 1, but Lai ‘931 fails to explicitly disclose further comprising:
a metal interconnect structure, disposed between the stack structure and the substrate,
wherein the gate pillar is electrically connected to a metal interconnect of the metal interconnect structure.
Nevertheless, in a related endeavor (Fig 1-16C of Lai ‘780), Lai ‘780 teaches further comprising:
a metal interconnect structure (414, Fig 16B of Lai ‘780, Para [0036]), disposed between the stack structure (Stack structure disclosed in annotated Fig 16B of Lai ‘780 and Para [0045]) and the substrate (402, Fig 16B of Lai ‘780, Para [0035] discloses substrate 402 (not labeled in Fig 16B of Lai ‘780) in structure 414),
wherein the gate pillar (1002, Fig 16B of Lai ‘780, Para [0052]) is electrically connected to a metal interconnect (420, Fig 9A of Lai ‘780, Para [0051] discloses pillar electrically connected to via 420 of structure 414) of the metal interconnect structure (414).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lai ‘780’s a metal interconnect structure, disposed between the stack structure and the substrate, wherein the gate pillar is electrically connected to a metal interconnect of the metal interconnect structure into Lai ‘931’s device. Lai ‘931 discloses in Para [0015] that the dielectric layer 102 is connected to an interconnect structure, but Lai ‘931 does not give details of that connection or structure. Therefore the ordinary artisan would have been motivated to find details on an interconnect structure and how to connect to that interconnect structure. Lai ‘780, as described above, teaches connecting the stack structure to a metal interconnect structure. The ordinary artisan would have been motivated modify Lai ‘931 in the manner set forth above, at least, because as Lai ‘780 teaches in Para [0015] the connection of the memory structure to the peripheral region allows a wide range of functionalities to the device.
As incorporated, the metal interconnect structure (414) and the gate pillar being electrically connected to the metal interconnect structure of Lai ‘780 would be incorporated under layer 102 of Lai ‘931 and the gate pillar (145) of Lai ‘931 would be connected to the interconnect structure.
With respect to Claim 13 Lai ‘931 discloses all limitations of the memory device according to claim 1, but Lai ‘931 fails to explicitly disclose wherein the gate pillar is arranged in an array, and the gate pillar of two adjacent columns is configured to be either staggered or aligned.
Nevertheless, in a related endeavor (Fig 1-16C of Lai ‘780), Lai ‘780 teaches wherein the gate pillar (1002, Fig 16B of Lai ‘780, Para [0052]) is arranged in an array (array of gate pillars disclosed in Fig 16C of Lai ‘780, array shown through pillar contacts 1502 as disclosed in Para [0058] of Lai ‘780), and the gate pillar (1002) of two adjacent columns is configured to be either staggered or aligned (Fig 16C of Lai ‘780 discloses adjacent columns of gate pillars is aligned).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lai ‘780’s wherein the gate pillar is arranged in an array, and the gate pillar of two adjacent columns is configured to be e aligned into Lai ‘931’s device. Lai ‘931 discloses in Para [0029] that an interconnect structure formed over the stack, but Lai ‘931 does not give details of that structure. Therefore the ordinary artisan would have been motivated to find details of a top interconnect structure and how to connect to that interconnect structure. Lai ‘780, as described above, teaches connecting the gate pillars in an array through conductive contacts. The ordinary artisan would have been motivated modify Lai ‘931 in the manner set forth above, at least, because Lai ‘780 teaches a method to connect the stack to additional input/output functionality and an array arrangement supports an efficient production process as conductive structures between vias can be straight.
As incorporated, the teaching of forming the gate pillars in an array of Lai ‘780 would be incorporated as the arrangement of the gate pillars (145) of Lai ‘931.
With respect to Claim 15 Lai ‘931 discloses all limitations of the memory device according to claim 1, and Lai ‘931 further discloses wherein, in a X-direction, a width (W2, Fig 6A, Para [0023]) of the insulating layer (108A) is smaller than both a width (W1, Fig 6A, Para [0023]) of the first source and drain layer (106A-1) and a width (W1, Fig 6A, Para [0023]) of the second source and drain layer (106A-2)(Fig 6A and Para [0023] disclose width of 108A is reduced to be smaller than the width of layers 106A-1 and 106A-2).
With respect to Claim 16 Lai ‘931 discloses all limitations of the memory device according to claim 1, and Lai ‘931 further discloses wherein the charge storage structure (140) extends continuously in a Z-direction (Fig 9A discloses 140 extends continuously in a Z direction) and surrounds a sidewall of the gate pillar (145)(Fig 9A and Para [0027] discloses 140 formed over sidewalls of trench 137 and then 145 is deposited over 140 so 140 surrounds the sidewalls of 145).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lai ‘931 in view of Wu et al. (US 9,230,985 B1, hereinafter Wu ‘985), in view of the following arguments.
With respect to Claim 12 Lai ‘931 discloses all limitations of the memory device according to claim 1, but Lai ‘931 fails to explicitly disclose wherein a doping concentration of both the first source and drain layer and the second source and drain layer is in a range of E12 atoms/cm3 to E21 atoms/cm3.
Nevertheless, in a related endeavor (Fig 1 of Wu ‘985), Wu ‘985 teaches wherein a doping concentration of both the first source and drain layer (501a, Fig 1 of Wu ‘985, Col 3, Lines 54-55) and the second source and drain layer (501b, Fig 1 of Wu ‘985, Col 3, Lines 54-55) is in a range of E12 atoms/cm3 to E21 atoms/cm3 (Col 3, Lines 54-55 disclose a doping concentration for source/drain regions of 7X1020/cm3.
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Wu ‘985’s doping concentration of both the first source and drain layer and the second source and drain layer is in a range of E12 atoms/cm3 to E21 atoms/cm3 into Lai ‘931’s device. Lai ‘931 discloses in Para [0015] that the source/drain layers (106A-1 and 106A-2) are doped polysilicon, but Lai ‘931 does not give details of the doping concentration. Therefore the ordinary artisan would have been motivated to find details of source/drain layers and Wu ‘985, as described above, teaches source and drain doping concentrations for non-volatile memory stacks. The ordinary artisan would have been motivated modify Lai ‘931 in the manner set forth above, at least, because as Wu ‘985 teaches in Col 3, Lines 54-57, the taught source drain concentrations provide concentrations that provide for proper operation of the transistor device.
As incorporated, the source/drain doping concentrations taught by Wu ‘985 would be incorporated in the source/drain layers (106A-1 and 106A-2) of Lai ‘931.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lai ‘931 in view of Lai ‘780 in further view of Lee (US 2011/0198687 A1, hereinafter Lee ‘687), in view of the following arguments.
With respect to Claim 14 Lai ‘931 as modified by Lai ‘780 discloses all limitations of the memory device according to claim 13, but Lai ‘931 as modified by Lai ‘780 fails to explicitly disclose further comprising: an insulating filling layer disposed between the gate pillar of two adjacent columns.
Nevertheless in a related endeavor (Fig 16(a)-16(f) of Lee ‘687), Lee ‘687 teaches further comprising: an insulating filling layer (22, Fig 16(c) of Lee ‘687, Para [0137]) disposed between the gate pillar (6, Fig 16(c) of Lee ‘687, Para [0137]) of two adjacent columns (two columns of 6 as show in Fig 16(c) of Lee ‘687)(Para [0137] and Fig 16(c) of Lee ‘687 discloses an insulating material filling spaces between two adjacent gate pillar columns after the fill of those control electrode columns).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘687’s wherein an insulating filling layer disposed between the gate pillar of two adjacent columns into Lai ‘931’s device. The ordinary artisan would have been motivated modify Lai ‘931 in the manner set forth above, at least, because as Lee ‘687 teaches in Para [0137] forming the insulating films between the conductive pillars provides electrical separation which can reduce parasitic capacitance.
As incorporated, the insulating filling layer (22) disposed between the gate pillar of two adjacent columns as taught by Lee ‘687 would be incorporated as an insulating layer between two adjacent gate pillars (145) of Lai ‘931.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898