Attorney’s Docket Number: 093671-US-PA-0C1
Filing Date: 12/19/2022
Priority Date: 7/30/2020 (US 16/942,781)
Inventors: Liao et al.
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the amendment filed on 11/18/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis for a rejection (i.e., changing from AIA to pre-AIA ) will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 11/18/2025 in reply to the Office action in paper no. 6, mailed on 7/29/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-3 and 5-21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed inventions absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over van Dal (US 20120319211) in view of Ching (US 20190164840) and Cheng (US 2019/0035917).
Regarding claim 15, van Dal (see, e.g., figs. 6-7D and 10A) shows most aspects of the instant invention including a structure comprising:
A substrate 402 comprising semiconductor fins 406 extending in a first direction, wherein the fins include a top surface and side surfaces, and
A second dielectric layer and a gate electrode 410 sequentially disposed on and covering the top and side surfaces of the fins
Van Dal teaches that the second dielectric layer is a gate dielectric that may include materials such as SiO2, Si3N4, HfSiON, and/or HfSiO, thereby suggesting that the gate dielectric may comprise more than one layer (see, e.g., Van Dal: ¶0046/ll.3-4). However, he fails to explicitly show a liner and the gate dielectric also including a first dielectric layer, wherein the widths in the first direction of the liner and the first dielectric layer are greater than the widths of the second dielectric layer and the gate electrode.
Ching teaches that forming a liner 114 on the fins, prior to the gate dielectric 116, will protect the fins and improve the performance and reliability of the structure (see, e.g., Ching: ¶0059). The width of the liner 114 in the first direction Y is greater than the widths of the layers of the gate dielectric 116 and the gate electrode 118 (see, e.g., fig. 1A). Ching further teaches that the gate dielectric layer 116 may include more than one dielectric layer (see, e.g., Ching: ¶0049).
Cheng (see, e.g., fig. 26), like Ching, teaches forming a liner 702 on the fin 214, and forming a gate dielectric layer 704 on the liner. Cheng also teaches that the gate dielectric layer 704 may include multiple dielectric layers (see, e.g., Cheng: ¶0036). This teaches that single- and multi-layer gate dielectrics are interchangeable equivalent options in the semiconductor art, and selecting between them is a matter of routine experimentation based on desired electrical properties and design requirements.
Taken together, Ching and Cheng are evidence showing that one of ordinary skill in the art would have known at the time of filing the invention that single and multi-layer gate dielectrics were equivalents with no unpredictable change in their performance. That is, both structures would yield the predictable result of electrically coupling the gate electrode to the semiconductor fin.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the gate dielectric of van Dal comprising a single-layer or a multi-layer that includes first and second dielectric layers because these structures were recognized as equivalents in the semiconductor art, as taught by Ching and Cheng, and both would yield the predictable result of electrically coupling the gate electrode to the fin. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
It would also have been obvious at the time of filing the invention to one of ordinary skill in the art to include the liner of Ching in the structure of van Dal to improve the performance and reliability of the structure.
Regarding claim 16, Ching (see, e.g., fig. 2A) teaches that the thickness of the liner 114A2 on the side surfaces of the fins is smaller than the liner 114A1 on the top surface of the fins.
Regarding claim 17, Ching (see, e.g., fig. 2A) and Chen (see, e.g., fig. 26) show that the thicknesses of their gate dielectric layers 116,704 on the side surfaces of their fins 106,214 is equal to their thicknesses on the top surface of the fins. Ching and Chen show that the gate dielectric layer includes the first dielectric layer (see paragraphs 8-11 above).
Regarding claim 18, van Dal (see, e.g., fig. 10A) shows the structure further comprising a capping layer 409 covering the fins 406 and located under the gate dielectric. Ching (see, e.g., fig. 1A) shows that the liner 114 is under the gate dielectric 116.
Regarding claim 19, van Dal (see, e.g., fig. 10A) shows that the bottom surface of the capping layer 409 is aligned with an insulator 204. Ching (see, e.g., fig. 2A) shows that the bottom surface of the liner 114 is aligned with the insulator 104.
Regarding claim 20, van Dal (see, e.g., fig. 10A) shows the structure further comprising insulators 204 disposed on the substrate 402 and located underneath the capping layer 409. Ching (see, e.g., fig. 2A) shows that the insulators 104 are disposed on the substrate 102 and underneath the liner structure 114.
Allowable Subject Matter
Claims 1-3, 5-14 and 21 are allowed.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MDP/mdp
March 17, 2026