DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US PG Pub 2022/0344280 to Hsieh et al (hereinafter Hsieh) in view of US PG Pub 2020/0098707 to Chen et al (hereinafter Chen).
Regarding Claims 1 and 20, Hsieh disclsoes a semiconductor structure comprising:
a first bonding dielectric layer (Fig. 2, 212) located on a surface of a wafer (211);
a second bonding dielectric layer (215) located on, and having a bonding interface with, the first bonding dielectric layer;
a device-containing region (molding similar to 170, Fig. 1 and containing chips 201-203) located on the second bonding dielectric layer; and
wherein at least one of the first bonding dielectric layer or the second bonding dielectric layer is a stress modulating pattern (221-1) containing bonding dielectric layer comprising a plurality of patterned structures (Fig. 2).
Hsieh does not disclose a device wafer located on the device-containing region. However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have included a device wafer on the device containing region. Hsieh notes that additional device layers and wafers can be included as seen in Fig. 14. Placing these layers over either side of the semiconductor package would have been an obvious design choice to one of ordinary skill in the art.
Hsieh does not disclose wherein each patterned structure of the plurality of patterned structures is spaced apart from the bonding interface by a bonding dielectric material of at least one of the first bonding dielectric layer or the second bonding dielectric layer.
Chen discloses a plurality of patterned structures (Fig. 4, 455/459) spaced apart from the bonding interface (460/470) by a bonding dielectric material (460) of at least one of a first bonding dielectric layer (460) or the second bonding dielectric layer (470).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the patterned structures of Hsieh to have been embedded in at least one of the first bonding dielectric layer or the second bonding dielectric layer. Hsieh notes that the depth of the trenches can vary depending on warpage relief [0058] but makes no requirement for the metal fill to be in contact with the second bonding layer. Embedding the patterned structures provides obvious benefits such as increases an average CTE for the bonding dielectric (Chen, [0020]) and/or preventing the patterned structures from being too proximate to active metallization layers in the circuit, thereby preventing parasitic capacitance.
Regarding Claim 2, the combination of Hsieh and Chen makes obvious the semiconductor structure of Claim 1, wherein only the first bonding dielectric layer is the stress modulating pattern containing bonding dielectric layer (Hsieh, Fig. 2; Chen, Fig. 4).
Regarding Claim 3, the combination of Hsieh and Chen makes obvious the semiconductor structure of Claim 2, wherein the plurality of patterned structures are entirely embedded in the first bonding dielectric layer, and are present on a topmost surface of the wafer (Hsieh, Fig. 2).
Regarding Claim 4, the combination of Hsieh and Chen makes obvious the semiconductor structure of Claim 2, wherein the plurality of patterned structures are embedded in both the first bonding dielectric layer and the wafer (Hsieh [0058]).
Regarding Claims 5-7, the combination of Hsieh and Chen makes obvious the semiconductor structure of Claim 1, wherein only the second bonding dielectric layer is the stress modulating pattern containing bonding dielectric layer or wherein both the first bonding dielectric layer and the second bonding dielectric layer are stress modulating pattern containing bonding dielectric layers since the insulator layer (Hsieh 212) can comprise a multilayer (Hsieh [0025]) and in such an embodiment first and second bonding dielectric layers would be part of a multilayer and have the modulating patterns within all or select layers.
Regarding Claim 8, the combination of Hsieh and Chen makes obvious the semiconductor structure of Claim 7, wherein the plurality of patterned structures that are present in the first bonding dielectric layer are entirely embedded in the first bonding dielectric layer, and are present on a topmost surface of the wafer (Hsieh Fig. 2).
Regarding Claim 9, the combination of Hsieh and Chen makes obvious the semiconductor structure of Claim 7, wherein the plurality of patterned structures that are present in the first bonding dielectric layer are embedded in both the first bonding dielectric layer and the wafer (Hsieh [0058]).
Regarding Claim 10, the combination of Hsieh and Chen makes obvious the semiconductor structure of Claim 7, wherein the plurality of patterned structures that are present in the second bonding dielectric layer are at least partially embedded in the second bonding dielectric layer, and are in contact with the device-containing region since the insulator layer (Hsieh 212) can comprise a multilayer [0025] and in such an embodiment first and second bonding dielectric layers would be part of a multilayer and have the modulating patterns within all or select layers.
Regarding Claim 11, the combination of Hsieh and Chen makes obvious the semiconductor structure of Claim 1, wherein the plurality of patterned structures are patterned metal structures (Hsieh [0062]).
Regarding Claim 12, the combination of Hsieh and Chen obvious the semiconductor structure of Claim 1, wherein the plurality of patterned structures are patterned dielectric structures (Hsieh [0062]).
Regarding Claim 13, the combination of Hsieh and Chen makes obvious the semiconductor structure of Claim 1, wherein the plurality of patterned structures are arranged in an orthogonal grid pattern (Hsieh Figs. 6-8).
Regarding Claim 14, the combination of Hsieh and Chen makes obvious the semiconductor structure of Claim 1, wherein the plurality of patterned structures are arranged in a polar grid pattern (Figs. 6-8).
Regarding Claim 15, the combination of Hsieh and Chen makes obvious the semiconductor structure of Claim 1, wherein the plurality of patterned structures are arrays of continuous or discontinuous lines, arranged with uniform or non-uniform density (Hsieh Figs. 6-8).
Regarding Claim 16, Hsieh makes obvious the semiconductor structure of Claim 15, further comprising:
a backside interlayer dielectric material layer (Hsieh 1415, Fig. 14) located on device-containing region and the device wafer, wherein wiring and/or contact structures are embedded in the backside interlayer dielectric material layer.
Regarding Claim 17, the combination of Hsieh and Chen makes obvious the semiconductor structure of Claim 16, further comprising:
a solder pad located on a surface of the wiring and/or contact structures; and
a solder bump located on each solder pad (Hsieh Fig. 14)
Regarding Claim 18, the combination of Hsieh and Chen makes obvious the semiconductor structure of Claim 1, wherein the device-containing region comprises at least one semiconductor device (Hsieh Chips 201-203).
Regarding Claim 19, the combination of Hsieh and Chen makes obvious the semiconductor structure of Claim 1, wherein a bonding interface exists between the first bonding dielectric layer and the second bonding dielectric layer (Hsieh Fig. 2).
Response to Arguments
Applicant’s arguments with respect to Claim(s) 1-20 have been considered but are moot because the new ground of rejection relies on a combination of Hsieh and Chen, which Applicant has not been able to address.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
