Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chang (Patent Application Publication 2022/0392503).
Claim 1. An apparatus, comprising: NAND memory (Memory 100 Fig 1, Flash memory taught in Chang [0022]); and circuitry coupled to the NAND memory (comprising controller 200 Fig 1) to provide duty cycle correction (to provide DCA through controller 210, Fig 1) for one or more write paths of the NAND memory (write path 130, Chang Fig 2).
Claim 2. The apparatus of claim 1, wherein the circuitry is further to: provide closed loop DCC for one or more data input write paths of the NAND memory (120 DCA is in closed loop through 102 Fig 2).
Claim 3. The apparatus of claim 1, further comprising DCC calibration logic coupled to the circuitry (120 Fig 2), wherein the circuitry is further to: adjust the DCC for one or more write paths (130 Fig 2) of the NAND memory based on a first signal from the DCC calibration logic (signal at input at 120 Fig 2).
Claim 4. The apparatus of claim 3, wherein the circuitry is further to: provide DCC for one or more read paths of the NAND memory (140 Fig 2); and adjust the DCC for one or more read paths of the NAND memory (using DCA 120) based on a second signal from the DCC calibration logic (based on another input at 120 Fig 2).
Claim 5. The apparatus of claim 3, wherein the DCC calibration logic is further to: compare a signal pattern on a write path of the NAND memory (130 Fig 2) against a reference pattern (against ref pattern for write code 101); determine a duty cycle comparison result based on the comparison (at output of 120); and provide a compensation code to the circuitry based on the duty cycle comparison result (DCA_CODE_RD from 102 based on the comparison at 120).
Claim 6. The apparatus of claim 5, wherein the DCC calibration logic is further to: determine if the duty cycle comparison result indicates sufficient DCC for the write path (write path 130 Fig 2); and, if so determined, lock the compensation code for the write path (code from 101 Fig 2 coming from mux 105 controlled by WR/WR Mode).
Claim 7. The apparatus of claim 1, wherein the NAND memory comprises three-dimensional NAND memory (claim 1 teach flash memory. NAND memory is three dimensional flash memory.).
Claim 8. A memory device, comprising: NAND memory (Memory 100 Fig 1, Flash memory taught in Chang [0022]); and interface circuitry coupled to the NAND memory (comprising controller 200 Fig 1) to provide a plurality of output data read paths and a plurality of input data write paths for the NAND memory (write paths through write path tree 130 and read paths through read path tree 140 Fig 1, Chang Fig 2), wherein the interface circuitry further comprises a plurality of write duty cycle correction (DCC) circuits (comprising duty controller 210 Fig 1 and dca 120 Fig 100) respectively coupled to the plurality of input data write paths (paths going through write path tree 140 Fig 2) for the NAND memory to provide DCC (from 120 DCA) for the plurality of input data write paths (input data write paths through 140 Fig 2).
Claim 9. The memory device of claim 8, wherein the interface circuitry is further to: train the plurality of write DCC circuits in response to a request from a host (training the plurality of write DCC circuits in response to a request from a host taught in Chang [0006]).
Claim 10. The memory device of claim 9, wherein, in response to the request, the interface circuitry is further to: supply a reference clock pattern at an input of a write path with a reference duty cycle (reference clock pattern at input of 120 which is at input of 130 Fig 2); determine a duty cycle difference between the reference duty cycle and an output duty cycle of a signal pattern at an output of the write path (120 determines a duty cycle difference between the reference duty cycle and an output duty cycle of a signal pattern at an output of 120 Fig 2); and adjust a corresponding write DCC circuit coupled to the write path to compensate for the duty cycle difference (DCA adjusts a corresponding write DCC circuit coupled to the write path at 130 Fig 2 to compensate for the duty cycle difference).
Claim 11. The memory device of claim 10 wherein the interface circuitry further comprises: DCC calibration logic coupled to the plurality of write DCC circuits to provide a compensation code (From 101 Fig 2) to the corresponding write DCC circuit (to 130) based on the duty cycle difference (based on the output of 120).
Claim 12. The memory device of claim 11, wherein the DCC calibration logic is further to: provide one of a first compensation code if the duty cycle difference indicates that the output duty cycle is higher than the reference duty cycle and a second compensation code if the duty cycle difference indicates that the output duty cycle is lower than the reference duty cycle (two different compensation codes can be stored in 101 or 102 Fig 2, Chang [0051]).
Claim 13. The memory device of claim 11, wherein the corresponding write DCC circuit comprises: a bleeder circuit to skew the input of the write path based on the compensation code (105 and 120 skew the input of the write path 130 based on the compensation code from 102 Fig 2).
Claim 14. The memory device of claim 11, wherein the interface circuitry further comprises: a plurality of read DCC circuits (DCA 120 and DCM 110) respectively coupled to the DCC calibration logic (coupled to duty controller 210 Fig 1) and to the plurality of output data read paths (at read path tree 140) for the NAND memory to provide DCC (from 120) for the plurality of output data read paths (through 140 Fig 2) based on respective compensation codes from the DCC calibration logic (based on codes from 102 Fig 2).
Claim 15. A system, comprising: a processor (controlling memory controller 200); and a NAND memory device coupled to the processor (Memory 100 Fig 1 coupled the processor to operate, Flash memory taught in Chang [0022]), the NAND memory device comprising: NAND memory cells (Memory 100 Fig 1, Flash memory taught in Chang [0022]); a controller to control access to the NAND memory cells (200 Fig 1); read circuitry including a read duty cycle correction (DCC) circuit to (proving DCC input to DCA 120 Fig 2) provide DCC for an output data read path for the NAND memory device (through read path 140 Fig 2); and write circuitry including a write DCC circuit to provide DCC for an input data write path for the NAND memory device (through write path 130 Fig 2).
Claim 16. The system of claim 15, wherein the NAND memory device further comprises: a DCC calibration engine (DCA 120 Fig 2) shared between the read DCC circuit and the write DCC circuit (shared between input of 120 and write path tree 130 Fig 2).
Claim 17. The system of claim 16, wherein the NAND memory device further comprises training circuitry to, in response to a request from the processor (training the plurality of write DCC circuits in response to a request from a host taught in Chang [0006]): supply a reference clock pattern at an input of the input data write path with a reference duty cycle (input of 120 Fig 2); determine a duty cycle difference between the reference duty cycle and an output duty cycle of a signal pattern at an output of the output data write path (determined by DCA 120 Fig 2); and adjust the write DCC circuit to compensate for the duty cycle difference based on information from the DCC calibration engine (DCA output adjust the write to 130 to compensate for the duty cycle difference based on information from 120 Fig 2).
Claim 18. The system of claim 17, wherein the DCC calibration engine is further to: provide a compensation code (From 101 Fig 2) to the write DCC (to 130) circuit based on the duty cycle difference (based on the output of 120).
Claim 19. The system of claim 18, wherein the DCC calibration engine is further to: provide one of a first compensation code if the duty cycle difference indicates that the output duty cycle is higher than the reference duty cycle and a second compensation code if the duty cycle difference indicates that the output duty cycle is lower than the reference duty cycle (two different compensation codes can be stored in 101 or 102 Fig 2, Chang [0051]).
Claim 20. The system of claim 18, wherein the write DCC circuit comprises: a bleeder circuit to skew the input of the input data write path based on the compensation code (105 and 120 skew the input of the write path 130 based on the compensation code from 102 Fig 2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/
Primary Examiner, Art Unit 2827