DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 03/25/2026 has been entered. Claims 1-14 and 16, remain pending in the application. Applicant’s amendments have overcome the claims and specification objections previously set forth in the Non-Final Office Action mailed on 01/29/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/05/2026 has been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Ko (United States Patent Application Publication Number, US 2009/0058455 A1) hereinafter referenced as Ko, in view of Antony Mowry et al., (United States Patent Number, US 8,212,184 B2) hereinafter referenced as Mowry, and in view of Jiaw-Ren Shih (United States Patent Application Publication, US 2017/0153287 A1), hereinafter referenced as Shih.
Regarding claim 1, Ko teaches a semiconductor structure, comprising: a polysilicon heater structure (Fig.1, element #12, paragraph [0027], rows1-5) disposed on a substrate (paragraph [0032], rows 1-2); and a device to be tested, disposed above a top of the heater structure(Fig.1, element #16), and not directly coupled through a continuous electrical path with the heater structure (paragraph [0029], rows 2-6), wherein the device to be tested is heated by a heat generated when the heater structure is applied with a voltage (paragraph [0028], rows 1-3), and wherein the device to be tested comprises a circuit pattern layer to be electrically tested (paragraph [029], rows 5-9).
Ko does not directly teach the heater structure is a gate layer structure. However, in Fig.5, Ko teaches the device to be tested is formed by metal 1 and metal 2 layers (Fig.5b) and the entire structure, including the heater and the device to be tested, is made on a wafer, in the same manufacturing steps of a semiconductor manufacturing process without a need for additional steps (paragraph [0032], rows 1-7). Therefore, the polysilicon heater structure, being a layer below the conductive layer metal 1, can be the same layer as the gate layer. Furthermore, Mowry teaches at least one gate structure (Fig.1h, element #121, column 10, rows 47-49), disposed on a substrate (Fig.1c, substrate element #101, column 9, rows 50-54), where the gate structure is formed of polysilicon (column 14, rows 21-22) and is used as a heater structure. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to combine the teachings of Mowry and Ko and disclose the heater structure is a gate structure. As disclosed by Mowry, the polysilicon gate layer is used to build transistors and circuits on the wafer and using the same polysilicon layer to build the heater can be performed in the same manufacturing steps without a need for additional steps, thus reducing costs.
The combination of Ko and Mowry does not teach the gate structure is a metal gate structure. Shih teaches a gate structure made of metal and used as a heater (Fig.1B, gate, element #103 of the heater element #11 is made of metal, paragraph [0021], rows 7-9). Thus, both references, Mowry and Shih, teach a gate structure that can be used as a heater. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the polysilicon gate disclosed by Mowry could have been replaced with a metal gate as disclosed by Shih, because both serve the same purpose of providing an electrically conductive material that can be used for heaters. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an electrically conductive material that can be used for heaters. Metal gates can withstand higher temperatures than polysilicon and are compatible with modern high-k dielectric materials used in modern semiconductor processes.
Regarding claim 3, the combination of Ko, Mowry and Shih teaches the semiconductor structure of claim 1 as set forth in the obviousness rejection. Mowry further teaches a resistance of the metal gate of the metal gate structure can be adjusted on the basis of length, while keeping the same configuration of the gate electrode or by avoiding lithography or implant steps in the formation of the gate electrode. Furthermore, Mowry teaches that a higher or lower resistance can be generated depending of the output power desired (column 11, rows 1-18). Therefore, it would have been obvious to someone of ordinary skill in the art, before the effective filing data of the claimed invention, to optimize the resistance of a metal gate through routine experimentation (MPEP 2144.05). The resistance is a result effective variable because it is important to optimize its value based on the application conditions for which the heater is being used, in order to be able to heat the device at the desired temperature.
Regarding claim 4, the combination of Ko, Mowry and Shih teaches the semiconductor structure of claim 1 as set forth in the obviousness rejection. Ko further teaches the semiconductor structure of claim 1, wherein from a top view of the substrate, the metal gate structure has a mesh shape on the substrate (Fig.4, bottom left corner).
Regarding claim 5, the combination of Ko, Mowry and Shih teaches the semiconductor structure of claim 1 as set forth in the obviousness rejection. Ko further teaches the semiconductor structure of claim 1, wherein from a top view of the substrate, the metal gate structure has a curved line shape on the substrate (Fig.4, upper right corner).
Regarding claim 6, the combination of Ko, Mowry and Shih teaches the semiconductor structure of claim 1 as set forth in the obviousness rejection. Ko further teaches the semiconductor structure of claim 1, wherein the at least one gate structure comprises a plurality of strip-shaped gate structures, and the plurality of strip-shaped gate structures are electrically connected to each other (Fig.4, bottom left corner).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Mowry Shih, and in view of David Dreifus et al., (United States Patent Number, US 5173761) hereinafter referenced as Dreifus.
Regarding claim 2, the combination of Ko, Mowry and Shih teaches the semiconductor structure of claim 1 as set forth in the obviousness rejection. The combination of Ko, Mowry and Shih does not teach the semiconductor structure of claim 1, wherein a line width of a metal gate of the metal gate structure does not exceed 2 um. Dreifus teaches wherein a line width of a metal gate of the metal gate structure is less than 1 um (column 6, rows 31-34). Therefore, the claimed range overlaps the range disclosed by the prior art, and a prima facie case of obviousness exists (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Dreifus and disclose a line width of a metal gate of the metal gate structure in the claimed range. Metal gate lines wider then 2um are not always compatible with the manufacturing processes of the newer and smaller semiconductor technology nodes and introduce mechanical stress during the planarization of the metal layer.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Mowry Shih, and in view of Wolfgang Walter (United States Patent Application Publication, US 2011/0042671 A1), hereinafter referenced as Walter.
Regarding claim 7, the combination of Ko, Mowry and Shih teaches the semiconductor structure of claim 1 as set forth in the obviousness rejection. The combination of Ko and Mowry does not teach the semiconductor structure of claim 1, wherein the metal gate structure comprises a gate dielectric layer and a work-function metal layer disposed on the substrate in sequence. Shih teaches wherein the metal gate structure comprises a gate dielectric layer (Fig.1B, element #104 is a dielectric layer, paragraph [0017], row 5) and a work-function metal layer (Fig.1B, gate, element #103 is made of metal, paragraph [0021], rows 7-9) disposed on the substrate in sequence (Fig.1B, element #130 is disposed on element #104, which is disposed on the substrate, element #101). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Shih and disclose the metal gate structure comprises a gate dielectric layer and a work-function metal layer disposed on the substrate in sequence. As disclosed by Shih, the layers arranged in this sequence form a transistor gate.
Walter also teaches wherein the metal gate structure (Fig.1, formed by element #104 paragraph [0034] rows 4-5, where M0 comprises a metal, paragraph [0063], row 4-7, and the portion of element #112 located under element #104, paragraph [0046], rows 5-8), comprises a gate dielectric layer (portion of element #112 located under element #104, paragraph [0046], rows 5-8) and a work-function metal layer (element #104 paragraph [0034] rows 4-5, where M0 comprises a metal, paragraph [0063], row 4-7) disposed on the substrate in sequence (Fig.1). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Walter and disclose the metal gate structure comprises a gate dielectric layer and a work-function metal layer disposed on the substrate in sequence. This is a standard layer sequence of an active transistor gate and, making the metal gate structure with the same layer structure, allows it and the gates of the transistors placed on the same substrate, to be manufactured using the same process steps. This eliminates the need for extra processing steps and the increase in cost associated with these steps.
Claims 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ko, in view of Mowry, Shih, Walter and in view of Chih-Kai Hsu, (United States Patent Application Publication Number, US 2016/0379839 A1) hereinafter referenced as Hsu.
Regarding claim 8, the combination of Ko, Mowry and Shih teaches the semiconductor structure of claim 1, as set forth in the obviousness rejection, and the combination of Ko, Mowry, Shih and Walter teaches the semiconductor structure of claim 7 as set forth in the obviousness rejection. The combination of Ko, Mowry, Shih and Walter does not teach the semiconductor structure of claim 7, wherein the metal gate structure comprises the gate dielectric layer, a bottom barrier layer, the work-function metal layer, a top barrier layer and a low-resistance metal layer disposed on the substrate in sequence. Hsu teaches wherein the metal gate structure (Fig.11, formed by elements #421 and #422, paragraph [0040], rows 6-7) comprises the gate dielectric layer (Fig.11, element #421, paragraph [0040], rows 6-7), a bottom barrier layer, the work-function metal layer, a top barrier layer and a low-resistance metal layer disposed on the substrate in sequence (paragraph [0042], rows 1-4). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hsu and disclose the metal gate structure comprises the gate dielectric layer, a bottom barrier layer, the work-function metal layer, a top barrier layer and a low-resistance metal layer disposed on the substrate in sequence. As disclosed by Hsu, the metal gate structure with the layer sequence claimed is commonly used for gate fabrication in FinFET technology to help reduce leakage and improve channel control, and would allow the use of the same process steps for fabricating the heater and the transistor gates.
Regarding claim 9, the combination of Ko, Mowry and Shih teaches the semiconductor structure of claim 1, as set forth in the obviousness rejection, the combination of Ko, Mowry, Shih and Walter teaches the semiconductor structure of claim 7 as set forth in the obviousness rejection, and the combination of Ko, Mowry, Shih, Walter and Hsu teaches the semiconductor structure of claim 8 as set forth in the obviousness rejection. Hsu further teaches wherein a material of the gate dielectric layer comprises hafnium oxide (paragraph [0041], rows 1-3).
Regarding claim 10, the combination of Ko, Mowry and Shih teaches the semiconductor structure of claim 1, as set forth in the obviousness rejection, the combination of Ko, Mowry, Shih and Walter teaches the semiconductor structure of claim 7 as set forth in the obviousness rejection, and the combination of Ko, Mowry, Shih, Walter and Hsu teaches the semiconductor structure of claim 8 as set forth in the obviousness rejection. Hsu further teaches wherein a material of the bottom barrier layer comprises TaN, TiN or a combination thereof (paragraph [0042], rows 4-6).
Regarding claim 11, the combination of Ko, Mowry and Shih teaches the semiconductor structure of claim 1, as set forth in the obviousness rejection, the combination of Ko, Mowry, Shih and Walter teaches the semiconductor structure of claim 7 as set forth in the obviousness rejection, and the combination of Ko, Mowry, Shih, Walter and Hsu teaches the semiconductor structure of claim 8 as set forth in the obviousness rejection. Hsu further teaches wherein a material of the work-function metal layer comprises TiAl, TiN or a combination thereof (paragraph [0042], rows 8-12).
Regarding claim 12, the combination of Ko, Mowry and Shih teaches the semiconductor structure of claim 1, as set forth in the obviousness rejection, the combination of Ko, Mowry, Shih and Walter teaches the semiconductor structure of claim 7 as set forth in the obviousness rejection, and the combination of Ko, Mowry, Shih, Walter and Hsu teaches the semiconductor structure of claim 8 as set forth in the obviousness rejection. Hsu further teaches wherein a material of the top barrier layer comprises TiN (paragraph [0042], rows 12-15).
Regarding claim 13, the combination of Ko, Mowry and Shih teaches the semiconductor structure of claim 1, as set forth in the obviousness rejection, the combination of Ko, Mowry, Shih and Walter teaches the semiconductor structure of claim 7 as set forth in the obviousness rejection, and the combination of Ko, Mowry, Shih, Walter and Hsu teaches the semiconductor structure of claim 8 as set forth in the obviousness rejection. Hsu further teaches wherein a material of the low-resistance metal layer comprises Al (paragraph [0042], rows 15-16).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Mowry, Shih, and in view of Olivier Le Neel, (United States Patent Application Publication Number, US 2013/0141834 A1) hereinafter referenced as Le Neel.
Regarding claim 14, the combination of Ko, Mowry, and Shih teaches the semiconductor structure of claim 1 as set forth in the obviousness rejection. The combination of Ko, Mowry, and Shih does not teach the semiconductor structure of claim 1, wherein the heat generated when the metal gate structure is applied with the voltage, increases an ambient temperature of the device to be tested to a temperature in a range of 200 0C to 400 0C. Le Neel teaches a heater (Fig.1, formed by elements # 104a and #104b and #106 of semiconductor, element #100, paragraph [0025], rows 1-3) that can be used to reach threshold temperatures in the range up to 600 °C, depending on the current /voltage applied and the desired temperature value (paragraph [0096], rows 1-3). Therefore, it would have been obvious to someone of ordinary skill in the art, before the effective filing data of the claimed invention, to optimize the heat generated by applying a voltage to the metal gate structure through routine experimentation (MPEP 2144.05). The heat generated is a result effective variable because it is important to optimize its value based on the application conditions for which the heater is being used, to be able to reach the desired temperature.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Mowry, Shih, and in view of Shelby Ferguson, (United States Patent Application Publication Number, US 2018/0174940 A1), hereinafter referenced as Ferguson.
Regarding claim 16, the combination of Ko, Mowry and Shih teaches the semiconductor structure of claim 1 as set forth in the obviousness rejection. The combination of Ko, Mowry, and Shih does not teach the semiconductor structure of claim 1 further comprising an interconnect structure disposed between the metal gate structure and the device to be tested, wherein the interconnect structure is electrically separated from the metal gate structure and the device to be tested. Ferguson teaches a semiconductor structure further comprising an interconnect structure (Fig.1, elements #112-1 and #112-2, paragraph [0034], rows 5-6) disposed between the heater (Fig.1, element #114-1 and #114-2, paragraph [0030], rows 4-5) and the device to be heated (Fig.1, element #100-1 and #100-2, paragraph [0032], rows 2-3), wherein the interconnect structure is electrically separated from the metal gate structure and the device to be tested (paragraph [0041], rows 1-11, the heater control unit, #130 can make electrical contact with the terminals of heater traces #114 or the interconnect traces #112 therefore elements #114 and #112 are not electrically connected; traces #112 have terminals connected to device #130 and not device #100). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ferguson and disclose further comprising an interconnect structure disposed between the metal gate structure and the device to be tested, wherein the interconnect structure is electrically separated from the metal gate structure and the device to be tested. As disclosed by Ferguson, the interconnect layer can be used as a temperature sensor.
Response to Arguments
Applicant’s arguments filed on 03/25/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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