DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the rejection of the claims under 35 USC 112(a), Applicant’s amendments resolve the prior issues of new matter in these claims. Accordingly, the rejection of claims 1, 3-4, 20-24 under 35 USC 112(a) is withdrawn.
RE: the rejection of the claims under 35 USC 103, Applicant's amendments and arguments have been considered but further search and consideration prompted the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, 21-22, 24-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20220020669A1 (“Mcknight-Macneil”) in view of US20050260795A1 (“Park”) further in view of US20180315914A1 (“Sasaoka”).
RE: Claim 1, Mcknight-Macneil discloses An embedded die package (100 in FIG. 7) comprising
a laminated body (layers in 100 including 110, 120-1, 120-2, 120-4, 130-1, 130-2 [0081]) and
a die (die 10, [0081]) comprising a power semiconductor device (10 is a power semiconductor die, [0081]),
the die being embedded within the laminated body (FIG. 7 shows 10 embedded in the laminated body), wherein:
the laminated body comprises a layer stack of a plurality of dielectric layers (110, 120-1, 120-2, 120-4 are dielectric layers, [0081]) and electrically conductive layers (130-1, 130-2 are conductive copper layers, [0081]);
a first electrically conductive layer comprising a leadframe (112 in 110 shown in FIG. 24) defining electrical contact areas (lead frame 112 surrounds the die and provides electrical interconnections through the dielectric layer(s) of the core structure 110, [0094]),
the leadframe embedded within the laminated body (FIG. 24 shows the leadframe 112 embedded within the laminated body 110, 120-1, 120-2, 120-4);
the die being mounted on the leadframe (leadframe comprises parts 114 and 116, wherein the middle part 116 has a cavity which supports the die, [0095]);
electrical connections between contact pads of the die (contact area on back-side of die, [0036]), the electrical contact areas of the leadframe (In FIG. 24, left and right parts of lead frame 110 connecting to 130-2, 130-3) and at least one other electrically conductive layer (130-3 and/or 180-4 in FIG. 7, [0094]), the electrical connections comprising electrically conductive vias (vias 140, 150, 160 in FIG. 7; these vias would establish electrical connections between back side of the die, the left, right parts of the lead frame 110, and the layer 130-3; FIG. 24 shows unlabeled vias establishing electrical connections between back side of the die, the left, right parts of the lead frame 110, and the layer 130-3 and extending through the dielectric layers) extending through the dielectric layers.
Mcknight-Macneil does not explicitly disclose wherein edges of the leadframe comprise a structured edge profile comprising lateral scallops defined by curved areas and a vertical undercut disposed beneath the lateral scallops, the structured edge profile defining lateral and vertical geometric variations that provide interlocking engagement between the leadframe and surrounding dielectric layers of the laminated body.
However, Mcknight-Macneil discloses The core structure 110 comprises dielectric layer(s), [0094].
In the same field of endeavor, Park discloses a leadless leadframe 100 with an improved die pad for mold locking, [0022] and the leadframe 100 includes die pad 110, [0022].
FIGs. 4-5, 8 shows edges of 110 including indentations 114 that form lateral scallops being defined laterally by curved areas.
Park further discloses the indentations 114 are semi-vias be located in the sidewalls 113 and on the periphery of the upper surface 111, which are in semi-circular shape through the upper surface of the die pad 110, [0022].
FIGs. 10, 12 show a vertical undercut 315 disposed beneath indentations 314.
Park further discloses the indentations 314 are V-shaped, U-shaped or semicircle shaped grooves, [0024].
Park further discloses A main purpose of the present invention is to provide a leadless leadframe with an improved die pad for mold locking. The leadless leadframe has a plurality of indentations formed in the sidewalls of the die pad for being encapsulated by the package body to enhance the mold locking capability of the die pad in the horizontal direction, [0004].
Accordingly, Park discloses:
wherein edges of a leadframe comprise a structured edge profile comprising lateral scallops defined by curved areas (indentations of 114, 314 are semicircular or U-shaped) and a vertical undercut disposed beneath the lateral scallops (vertical undercut 315 in FIG. 12), the structured edge profile defining lateral geometric variations (lateral geometric variations in the edge profile of the die pad 110, 310 is shown in FIGs. 4-5, 8, 10, 12) that provide interlocking engagement between the leadframe and surrounding dielectric layer (230 includes electrically insulated resin, [0024]; When the semiconductor package mentioned above passes through a thermal test, the indentations 114 can disperse the horizontal thermal stress and firmly hold the sidewall 113 of the die pad 110 with the package body 230 in the horizontal direction. Therefore, the sidewall 113 of the die pad 110 will not easily delaminate from the package body 230, [0024]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the edges of the leadframe in Mcknight-Macneil to include a structured edge profile with lateral scallops and a vertical undercut as taught by Park in order to improve mold locking as further taught by Park.
In the same field of endeavor, Sasaoka discloses in FIG. 8:
a leadframe (LF includes leads 20, [0083]) including a structured edge profile comprising a vertical undercut (recess portion 221, [0063]), the structured edge profile defining vertical geometric variations that provide interlocking engagement between the leadframe and surrounding dielectric layer (The rear surfaces 22 and 32 of the first lead 20 and the second lead 30 are exposed from the rear surface 14 of the molded resin 11 and are formed into concave portions on the sides of the front surfaces of the leads from the edges of the rear-surface exposed portion. The concave portions (i.e., the rear surface concave portions) 221 and 321 are covered by the molded resin 11 (see, FIG. 10), [0063]; FIG. 8 shows the vertical geometric variations of the vertical undercut 221 in direct contact with and interlocking engagement with molded resin 11b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vertical undercut of the lead frame 112 to be in direct contact with the dielectric layer(s) of the core structure 110 as taught by Sasaoka in order to improve interlocking between the lead frame 112 and the surrounding dielectric layers of the core structure 110.
RE: Claim 4, the combination of Mcknight-Macneil, Park, Sasaoka discloses The embedded die package of claim 1, wherein the dielectric layers comprise a glass fiber filled epoxy composite resin (Mcknight-Macneil discloses the at least one dielectric layer of the core and said first, second and outer dielectric build-up layers comprise any one of: a glass-fiber reinforced resin composition, [0021] and GaN die is embedded in a dielectric package body, e.g.: a glass fiber epoxy composite, [0005]),
the lateral scallops receiving portions of the epoxy composite resin during lamination (Park discloses The package body 230 encapsulates the semiconductor chip 210 and the bonding wires 220, and fills the indentations 114 of the die pad 110, [0024]; package body 230 includes electrically insulated resin, [0024]; Accordingly, as modified, portions of the glass-fiber resin composition would fill indentations of the lateral scallops and therefore be received by the lateral scallops during lamination).
The combination of Mcknight-Macneil, Park, Sasaoka does not explicitly disclose the lateral scallops receiving portions of the epoxy composite resin during lamination to accommodate deformation of glass fibers within the resin.
However, "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process," see MPEP 2113. In the instant case, as the lateral scallops receive portions of the glass-fiber resin composition during lamination, they would have accommodated any deformation of glass fibers within the resin during lamination.
Further, the limitation “to accommodate deformation of glass fibers within the resin” is an intended use limitation. Apparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, see MPEP 2114. Accordingly, as the lateral scallops would receive portions of the glass-fiber composition, they would be capable of accommodating deformation of glass fibers within the resin during lamination. Therefore, the limitations of the claim are met.
RE: Claim 21, the combination of Mcknight-Macneil, Park, Sasaoka discloses The embedded die package of Claim 1, the at least one other electrically conductive layer comprising a conductive layer that defines a thermal pad (In Mcknight-Macneil FIG. 7, thermal pad 180-4 or metal source pad 132-3, [0081]).
RE: Claim 22, the combination of Mcknight-Macneil, Park, Sasaoka discloses The embedded die package of Claim 21, the thermal pad also serving as a source pad (In Mcknight-Macneil 132-3 is a source pad, [0081]) for the embedded die package.
RE: Claim 24, the combination of Mcknight-Macneil, Park, Sasaoka discloses The embedded die package of Claim 1, the vertical undercut being curved (Sasaoka FIG. 8 shows the vertical undercut 221 being curved; Accordingly, as modified the vertical undercut is curved).
RE: Claim 25, the combination of Mcknight-Macneil, Park, Sasaoka discloses The embedded die package of Claim 1, wherein the structured edge profile reduces stress concentrations within the dielectric layers adjacent the leadframe during lamination (Park discloses When the semiconductor package mentioned above passes through a thermal test, the indentations 114 can disperse the horizontal thermal stress and firmly hold the sidewall 113 of the die pad 110 with the package body 230 in the horizontal direction, [0024]; Accordingly, as modified, the package is passed through a thermal test, and stress in the dielectric layers of the core 110 is dispersed by the structured edge profile; Accordingly, the structured edge profile would reduce stress concentrations within the dielectric layers of the core 110 adjacent the lead frame; Further, the limitation “wherein the structured edge profile reduces stress concentrations within the dielectric layers adjacent the leadframe during lamination” is a product by process limitation. "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process," see MPEP 2113. As the structured edge profile would reduce stress concentrations within the dielectric layers of the core 110 during a thermal test, the product is the same as the product made by the process of lamination, during which the structured edge profile reduces stress concentrations within the dielectric layers).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mcknight-Macneil in view of Park, further in view of Sasaoka as applied to claim 1 above, and further in view of US7005326B1 (“Glenn”).
RE: Claim 3, the combination of Mcknight-Macneil, Park, Sasaoka does not explicitly disclose The embedded die package of claim 1, wherein the structured edge profile comprises chamfered upper and lower edge portions.
However, in the same field of endeavor, Glenn discloses in FIG. 3:
wherein a structured edge profile (structured edge profile of die pad 24 and/or 30 of lead frame 20) comprises chamfered upper and lower edge portions (FIG. 3 shows upper and lower edge portions of 24 and 30 are chamfered or slanted)
Glenn teaches The reentrant portions of side surfaces 27 of die pad 24 and side surfaces 33 of tabs 30 of FIG. 3 have the function, in a completed package, of enhancing the connection between the encapsulating material, on the one hand, and die pad 24 and the contacts of the package (i.e., severed tabs 30), on the other hand, Col. 4, lines 61-67, see also Col. 4, lines 54-61.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Mcknight-Macneil, Park, Sasaoka so that the structured edge profile comprises chamfered upper and lower edge portions as taught by Glenn in order to enhance the connection between the surrounding dielectric layers of 110 and the lead frame 112.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mcknight-Macneil in view of Park, further in view of Sasaoka as applied to claim 1 above, and further in view of Yu Chen et al., "Molding void issue and solution of a Package-in-Package," 2012 14th International Conference on Electronic Materials and Packaging (EMAP), Hong Kong, China, 2012, pp. 1-5 (“Chen”), further in view of B. Xie, et al., "Accelerated Moisture Sensitivity Test Methodology for Stacked-Die Molded Matrix Array Package," 2007 9th Electronics Packaging Technology Conference, Singapore, 2007, pp. 100-104 (“Xie”) further in view of W. J. Roesch, "Measuring and comparing humidity acceleration factors of compound semiconductors," 2009 Reliability of Compound Semiconductors Digest (ROCS), Greensboro, NC, USA, 2009, pp. 125-136, (“Roesch”).
RE: Claim 20, the combination of Mcknight-Macneil, Park, Sasaoka does not explicitly disclose The embedded die package of Claim 1, wherein lamination of the embedded die structure is structured to survive 3 reflow cycles between 0 degrees Celsius and 260 degrees Celsius in 100 percent ambient humidity without delamination.
However, in the same field of endeavor, Chen discloses MSL 3 testing is Moisture Sensitivity Level 3 testing (see abstract on pg. 1).
Chen further discloses Failure mechanism was setup and verified based on findings from failure analysis and mold flow simulation. Design optimization had been pursued and verified, samples built after modification all passed the MSL3 test with improved reliability performance (see abstract pg. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Mcknight-Macneil, Park, Sasaoka by performing MSL 3 testing and performing design optimization and failure analysis so that the embedded die package passes MSL 3 testing as taught by Chen in order to improve reliability performance.
In the same field of endeavor, Xie teaches To validate the modeling results, the moisture/reflow tests were performed on this kind of MMAP under conditions of standard 216hrs30° C/60%RH and accelerated 30hrs, 45hrs, 60hrs, 75hrs, 88hrs-60° C/60%RH and After the moisture soak, the packages were subjected to 3 cycles of the certain reflow condition with the peak reflow temperature of 260 degrees Celsius (see pg. 102, paragraph immediately under the section heading “Experimental Validation”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Mcknight-Macneil, Park, Sasaoka, Chen so that the MSL 3 testing includes subjecting the embedded die package to relative humidity of 60%, 260 degrees Celsius and 3 reflow cycles as taught by Xie in order to improve reliability performance.
In the same field of endeavor, Roesch teaches In addition to biased moisture testing, there are also unbiased aging methods. The primary technique applied is autoclave (A/C) aging, run at 121ºC, 100% Relative Humidity and 15PSI, (pg. 126, left column, paragraph under Table 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Mcknight-Macneil, Park, Sasaoka, Chen, Xie so that the MSL 3 testing includes subjecting the embedded die package to relative humidity of 100% as taught by Roesch in order to improve reliability performance. As a result, the embedded die package would pass MSL3 testing and therefore survive 3 reflow cycles between 0 degrees Celsius and 260 degrees Celsius in 100 percent ambient humidity without delamination.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mcknight-Macneil in view of Park, further in view of Sasaoka as applied to claim 1 above, and further in view of US 20100258922 A1 (“Nakamura”).
RE: Claim 23, the combination of Mcknight-Macneil, Park, Sasaoka does not explicitly disclose The embedded die package of Claim 1, the surface of the leadframe being surface roughened independently of the structured edge profile.
However, in the same field of endeavor, Nakamura discloses etching and surface roughening of the lead frame LFa can improve the adhesion with the insulating resin, [0045].
Nakamura further discloses when both the upper and lower surfaces of the lead frame LFa are etched to roughen them, the surface roughening extends even to the bottom surface f2a of the die pad Dpa, [0046].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Mcknight-Macneil, Park, Sasaoka by performing a surface roughening process on the leadframe using surface etching as taught by Nakamura in order to improve adhesion with surrounding dielectric layers of 110. As a result, leadframe would be surface roughened independently of the structured edge profile.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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