Prosecution Insights
Last updated: September 17, 2026
Application No. 18/086,693

METHOD FOR INTEGRATING SEMICONDUCTOR CHIPS ON A SUBSTRATE

Non-Final OA §103
Filed
Dec 22, 2022
Examiner
CULBERT, CHRISTOPHER A
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Pulseforge Inc.
OA Round
1 (Non-Final)
42%
Grant Probability
Moderate
1-2
OA Rounds
0m
Est. Remaining
50%
With Interview

Examiner Intelligence

Grants 42% of resolved cases
42%
Career Allowance Rate
146 granted / 346 resolved
-25.8% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
43 currently pending
Career history
420
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
59.4%
+19.4% vs TC avg
§102
16.0%
-24.0% vs TC avg
§112
22.9%
-17.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 346 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 7-17 in the reply filed on 11/07/2025 is acknowledged. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 7-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chadda et al. (US 2021/0359186 A1) in view of Marinov et al. (US 2019/0057891 A1). Regarding claim 7, Chadda discloses a method for transferring microchips from a wafer to a receiving substrate, said method comprising: adhering microchips (portion above 24 and below 80 in Fig. 1A) to a temporary handler (22) wherein said temporary handler is a transparent carrier (laser light seen going through 22 in Fig. 13B) coated with a light-absorbing layer (24 in Fig. 1A), aligning and pressing said microchips on said temporary handler against a plurality of electrical contact points (412 in Fig. 13A; see Figs. 13A through 13H) on a receiving substrate (401 in Fig. 13A); applying a plurality of light pulses (one of which is shown in Fig. 13B) through said transparent carrier to heat said light-absorbing layer (although the predominant amount of energy in this step is transferred deeper into the structure, Chadda discloses some portion of the light is absorbed by components within the 10B, i.e., the light absorption layer, ¶ 0110, and this absorption will generate some small amount of heat) located on said temporary handler in order to bond said microchips to said electrical contacts points on said receiving substrate (the laser beam may be transmitted through the first coupon 22B and irradiate the reflector material layer 70 of an irradiated first light emitting diode 10B, which absorbs the laser beam and heats the adjacent solder layers 431, 441”, ¶ 0111); and applying a light pulse (light pulse shown in Fig. 13C) through said transparent carrier in order to separate said temporary handler at the interface of said light-absorbing layer and the temporary handler (the interface being the remainder of the LED which is separated from the temporary carrier as seen in Fig. 13D). Chadda does not disclose the use of a dicing tape to dice a wafer into the plurality of microchips and applying the microchips to the temporary handler via an adhesive layer. Marinov, in the same field of endeavor, discloses adhering a wafer (400 in Fig. 8A) onto a dicing tape (506) and then dicing the wafer into a plurality of components (see Figs. 8A) before adhering the components to a temporary handler (600 in Fig. 9) via an adhesive layer (“adhesive layer (not shown)”, ¶ 0187). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have divided the microchips of Chadda by attaching a wafer to a dicing film and applying the microchips to the temporary handler via an adhesive layer as taught by Marinov and the results of the substitution would have been predictable at applying the microchips to the temporary handler. (see MPEP § 2143(I)(B)). To separate the component from the temporary handler and the adhesive layer, Marinov further discloses applying a light pulse through the temporary handler to separate the temporary handler from the adhesive layer at the interface of a light-absorbing layer and an adhesive layer (see Fig,. 15) which also removes the adhesive layer to reveal the underlying components (see Fig. 15) which, in the method of the combination, will reveal said microchips that have been bonded to the receiving substrate. Regarding claim 8, Chadda further discloses that the electrical contact points on the receiving substrate are coated with the materials of the microchips (see Fig. 13A) and that the microchips comprise indium (¶ 0034). As such, Chadda discloses that the electrical contact points on said receiving substrate are coated with indium. Regarding claim 9, Chadda further discloses wherein said electrical contact points on said receiving substrate are coated with solder (¶ 0094). Regarding claim 10, Chadda further discloses with said light-absorbing layer includes nitrogen (¶ 0033). Regarding claim 11, Chadda further discloses that the plurality of light pulses are applied as a “flash” (¶ 0115) and as a “lamp” is something that emits light heating laser 467 in Fig. 13B may be considered a “flashlamp”. Regarding claim 12, Chadda discloses a method for transferring microchips from a wafer to a target wafer, said method comprising: adhering microchips (portion above 24 and below 80 in Fig. 1A) to a temporary handler (22) wherein said temporary handler is a transparent carrier (laser light seen going through 22 in Fig. 13B) coated with a light-absorbing layer (24 in Fig. 1A), aligning and pressing said microchips on said temporary handler against a plurality of electrical contact points (412 in Fig. 13A; see Figs. 13A through 13H) on a target wafer (401 in Fig. 13A); applying a plurality of light pulses (one of which is shown in Fig. 13B) through said transparent carrier to heat said light-absorbing layer (although the predominant amount of energy in this step is transferred deeper into the structure, Chadda discloses some portion of the light is absorbed by components within the 10B, i.e., the light absorption layer, ¶ 0110, and this absorption will generate some small amount of heat) located on said temporary handler in order to bond said microchips to said electrical contacts points on said target wafer (the laser beam may be transmitted through the first coupon 22B and irradiate the reflector material layer 70 of an irradiated first light emitting diode 10B, which absorbs the laser beam and heats the adjacent solder layers 431, 441”, ¶ 0111); and applying a light pulse (light pulse shown in Fig. 13C) through said transparent carrier in order to separate said temporary handler at the interface of said light-absorbing layer and the temporary handler (the interface being the remainder of the LED which is separated from the temporary carrier as seen in Fig. 13D). Chadda does not disclose the use of a dicing tape to dice a wafer into the plurality of microchips and applying the microchips to the temporary handler via an adhesive layer and individually placing each of said microchips via pick-and-place process. Marinov, in the same field of endeavor, discloses adhering a wafer (400 in Fig. 8A) onto a dicing tape (506) and then dicing the wafer into a plurality of components (see Figs. 8A) before adhering the components to a temporary handler (600 in Fig. 9) via an adhesive layer (“adhesive layer (not shown)”, ¶ 0187) individually via a pick-and-place process (¶ 0161). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have divided the microchips of Chadda by attaching a wafer to a dicing film and applying the microchips to the temporary handler via an adhesive layer individually via a pick-and-place process as taught by Marinov and the results of the substitution would have been predictable at applying the microchips to the temporary handler. (see MPEP § 2143(I)(B)). To separate the component from the temporary handler and the adhesive layer, Marinov further discloses applying a light pulse through the temporary handler to separate the temporary handler from the adhesive layer at the interface of a light-absorbing layer and an adhesive layer (see Fig,. 15) which also removes the adhesive layer to reveal the underlying components (see Fig. 15) which, in the method of the combination, will reveal said microchips that have been bonded to the receiving substrate. Regarding claim 13, Chadda further discloses that the electrical contact points on the target wafer are coated with the materials of the microchips (see Fig. 13A) and that the microchips comprise indium (¶ 0034). As such, Chadda discloses that the electrical contact points on said target wafer are coated with indium. Regarding claim 14, Chadda further discloses wherein said electrical contact points on said target wafer are coated with solder (¶ 0094). Regarding claim 15, Chadda further discloses with said light-absorbing layer includes nitrogen (¶ 0033). Regarding claim 16, Chadda further discloses that the plurality of light pulses are applied as a “flash” (¶ 0115) and as a “lamp” is something that emits light heating laser 467 in Fig. 13B may be considered a “flashlamp”. Regarding claim 17, Marinov further discloses a step of cleaning the components (¶ 0317). There was a benefit to cleaning the components as it removes debris. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have the step of placing include cleaning and activating (activating here is interpreted as preparing for subsequent attachment) exposed surfaces of said placed microchips and the target wafer for this benefit. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A CULBERT/ Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Dec 22, 2022
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
42%
Grant Probability
50%
With Interview (+7.7%)
3y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 346 resolved cases by this examiner. Grant probability derived from career allowance rate.

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