Prosecution Insights
Last updated: September 17, 2026

Pulseforge Inc.

3 pending office actions • 3 art units • 3 examiners • 0 of 3 (0%) have an AI response strategy ready • 1 patents granted in the last 365 days

Portfolio Summary

3
Total Pending OAs
2
Non-Final OAs
1
Final Rejections
0
Advisory / Quayle

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

1
Hard (33%)
2
Medium (67%)
0
Easy (0%)
0
Unknown (0%)

Rejection Statute Mix

BucketCases
§103 only2 (67%)
Multi-statute (no §101)1 (33%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

1
Life Sciences
33% of docket
0
Information Tech
0% of docket
0
Communications
0% of docket
1
Semiconductors
33% of docket
0
Mechanical / Eng
0% of docket
1
Business / Other
33% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

30 h
Manual time on pending OAs
6 h
Time saved (low, 20%)
10 h
Time saved (mid, 35%)
0.3 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
BERRY, PAUL ANTHONY 1 89.8% -1.2%
CULBERT, CHRISTOPHER A 1 42.2% +7.7%
WRIGHT, ALEXANDER SCOTT 1 72.5% -0.7%

Hard Cases (1)

Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 1 ordered by deadline are shown.

App #TitleExaminerDue in
18605697 METHOD FOR ATTACHING AND DETACHING WAFERS DURING INTEGRATED CIRCUIT MANUFACTURING BERRY, PAUL ANTHONY —

Top Art Units

Art UnitApps
4100 1
2815 1
1745 1

Pending Office Actions

App #TitleExaminerArt UnitStatutesStatusDue inAIFiled
18605697 METHOD FOR ATTACHING AND DETACHING WAFERS DURING INTEGRATED CIRCUIT MANUFACTURING BERRY, PAUL ANTHONY 4100 §103§112 Non-Final OA — Pending Mar 14, 2024
18086693 METHOD FOR INTEGRATING SEMICONDUCTOR CHIPS ON A SUBSTRATE CULBERT, CHRISTOPHER A 2815 §103 Non-Final OA — Pending Dec 22, 2022
17741460 METHOD FOR ATTACHING AND DETACHING SUBSTRATES DURING INTEGRATED CIRCUIT MANUFACTURING WRIGHT, ALEXANDER SCOTT 1745 §103 Final Rejection — Pending May 11, 2022

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