DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous rejection: claims 1 through 10 and 17 through 20 rejected, claims 11 through 16 non-elected.
Current rejection: claims 1 through 6, 17 and 20 rejected, claims 7 through 10, 18 and 19 objected, claim 11 through 16 non-elected.
Claim Objections
Claims 6, and 18 are objected to because of the following informalities:
Claim 6 recites “a second DRAM of the plurality of DRAM arrays” in line 2. The phrase appears to be missing a word, the examiner suggests “a second DRAM array” or a second portion of a DRAM array.
Claim 18 recites “for to be coupled” in line 4 appears to be a typographical error. The examiner suggests amending the claim to read “to be coupled.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 3, 4, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saraswat (US 2012/0250443) in view of Luk (US 5790839) in view of Chen (US 2004/0157163)
Regarding claim 1.
Saraswat teaches an integrated circuit (IC) stack (200) (fig 2) (paragraph 14), comprising: a plurality of semiconductor IC dice (202-214) stacked together (fig 2) (paragraph 14) and having circuit interconnections (paragraph 21) therebetween (fig 2,4); and at least one (212,214) of the plurality of semiconductor IC dice (202-214) comprises a [ dynamic random access memory (DRAM) array] (paragraph 9), wherein [the of DRAM array] comprises a plurality of trench capacitors (232d-232f) (paragraph 17,18) and support circuits (Cn) therefor (fig 2) (paragraph 16), wherein [the plurality of trench capacitors] of the plurality of [DRAM die] are adapted for coupling to a power bus [ ] (224) (fig 2) (paragraph 14).
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Sarasawat does not teach a plurality of DRAM arrays.
Luk teaches at least one semiconductor IC dice comprises a plurality of dynamic random-access memory (DRAM) arrays (DRAM) (fig 5a), wherein each of the plurality of DRAM arrays comprises a plurality of trench capacitors and support circuits (control logic) therefor, wherein first trench capacitors of the plurality of trench capacitors of a first DRAM array of the plurality of DRAM arrays are adapted for coupling to a power bus rail (fig 4a,5a) (column 4 lines 6-20), and second [portion] of the first DRAM array adapted for memory use (column 4 lines 25-30).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide capacitors between the power and the memory in order to filter noise generated by the logic devices.
Sitaram does not teach the DRAM array comprises trench capacitors for memory use.
Chen teaches first trench capacitors (304) of a first DRAM array are adopted for coupling to power and second trench capacitors (302) of the trench array are adapted for memory use (fig 2H) (paragraph 27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the DRAM array comprises memory trench capacitors in order to hold charge that can be read as data.
Regarding claim 2.
Sarasawat in view of Luk teaches elements of the claim 1
Sarasawat teaches the power bus (224) is adapted for coupling to a power distribution network (PDN) (404) of at least one of the plurality of semiconductor IC dice (404) (fig 4) (paragraph 27,28).
Regarding claim 3.
Sarasawat in view of Luk teaches elements of the claim 1
Sarasawat teaches the first trench capacitors (232) (paragraph 17) are adapted for coupling directly to the power bus (224) (paragraph 18,29).
Luk teaches the first trench capacitors (decoupling capacitor array) are adapted for coupling directly to the power bus (fig 5a) (column 4 lines 4 lines 20-25).
Regarding claim 4.
Sarasawat in view of Luk teaches elements of the claim 1
Sarasawat teaches the trench capacitors (232) (paragraph 17) are adapted for coupling to the power bus through the support circuits.
Luk teaches the first trench capacitors (decoupling capacitor array) are adapted for coupling to the power bus (fig 5a) (column 4 lines 4 lines 20-25).
Regarding claim 6.
Sarasawat in view of Luk teaches elements of the claim 1
Luk teaches the the plurality of tranch capacitors of a second DRAM of the plurality of DRAM arrays are available for use as memory (fig 5a).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sarasawat (US 2012/0250443) in view of Luk (US 5790839) in view of Chen (US 2004/0157163) as applied to claim 1 and further in view of Devaux (US 2023/0260968)
Regarding claim 5
Sarasawat in view of Luk teaches elements of the claim 1 above.
Sarasawat teaches the DRAM comprises first trench capacitors (paragraph 17)
Luk teaches the first trench capacitors (decoupling capacitor array) are adapted for coupling to the power bus (fig 5a) (column 4 lines 4 lines 20-25).
Sarasawat in view of Luk does not teach a plurality of power buses.
Devaux teaches a plurality of power buses (v) (paragraph 78)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of power busses in order distribute the power and convey different voltages (Luk paragraph 78)
Claim(s) 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sarasawat (US 2012/0250443) in view of Malladi (2020/0356488) in view of Luk (US 5790839) in view of Chen (US 2004/0157163)
Regarding claim 17
Sarasawat teaches a system of integrated circuit (IC) dice arranged in a three-dimensional stacked configuration (fig 2), comprising: a logic circuit IC die (202); at least one memory IC die (212) comprising dynamic random-access memory (DRAM), each of the plurality of DRAM [die] comprising a plurality of trench capacitors (paragraph 17) and support circuits therefor; and at least one digital logic and processing IC die (202) (paragraph 15),some of the DRAM (212) have associated trench capacitors (paragraph 17) thereof coupled to a power bus (224), the power bus (224) is adapted for coupling to a power distribution network (PDN) (404) for supplying power to the IC dies (202-214) (fig 4) (paragraph 27,28).
Sarasawat does not teach an interposer.
Malladi teaches a system of integrated circuit (IC) dice (110,120,150) arranged in a three-dimensional stacked configuration (fig 1) (paragraph 40), comprising: an interposer base (150) adapted for connecting to external circuits (160) (paragraph 42); a logic circuit IC die (120) electrically coupled to the interposer base (150) (paragraph 42); at least one memory IC die (110) (paragraph 40) comprising a plurality of dynamic random-access memory (DRAM) arrays (paragraph 41).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the die stack on an interposer in order for the interposer to serve as an intermediate structure to connect die to a circuit board or an external processor.
Sarasawat does not teach a plurality of DRAM arrays
Luk teaches each of the plurality of DRAM arrays (DRAM) comprising a plurality of trench capacitors (decoupling cap array) (column 4 lines 25-30) and support circuits therefor (fig 5a); wherein first capacitors of the plurality of capacitors of the first DRAM array of the plurality of DRAM arrays are used for memory and second trench capacitors of the plurality of capacitors of the first DRAM array (column 4 lines 15-30) are coupled to a power bus, the power bus is adapted for coupling to a power distribution network (PDN) (power grid) for supplying power to the IC dies (fig 5b) (paragraph 30-35).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for each DRAM die to comprise a plurality of DRAM arrays, in order to provide more memory capacity, each having associated decoupling trench capacitors in order for the capacitors to provide a noise shield for the memory (Luk column 4 lines 20-25).
Sarasawat does not teach the trench capacitor structure the DRAM array.
Chen teaches wherein first trench capacitors (302) of the plurality of trench capacitors of a first DRAM array of the plurality of DRAM arrays are used for memory and second trench capacitors (306) of the plurality of trench capacitors of the first DRAM array are for power (fig 2l) (paragraph 27)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the plurality of capacitors that comprise the DRAM array comprise first trench decoupling capacitors and second memory trench capacitors in order that the array can be formed using conventional DRAM technology (Luk column 4 lines 25-30)
Regarding claim 20.
Sarasawat in view Malladi in view of Luk in view of Chen teaches the structure of claim 17.
Sarasawat teaches signals and power are coupled between the stacked ICs with through silicon vias (TSV) (paragraph 11).
Allowable Subject Matter
Claims 7 through 10, 18 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the prior art does not teach An integrated circuit (IC) stack, comprising: at least one of the plurality of semiconductor IC dice comprises a plurality of dynamic random-access memory arrays, wherein each of the plurality of DRAM arrays comprises a plurality of trench capacitors and support circuits therefor, wherein first trench capacitors of the plurality of trench capacitors of a first DRAM array of the plurality of DRAM arrays are adapted for coupling to a power bus rail, and second trench capacitors of the plurality of trench capacitors of the first DRAM array are adapted for memory use, wherein a configuration selection circuit selects the second trench capacitors to be used for memory and the first trench capacitors to be coupled to the power bus in combination with the other elements of the claim.
Regarding claim 18, the prior art does not teach system of integrated circuit (IC) dice arranged in a three-dimensional stacked configuration, comprising: a plurality of DRAM arrays comprising a plurality of trench capacitors and support circuits therefor; wherein first trench capacitors of the plurality of trench capacitors of a first DRAM array of the plurality of DRAM arrays are used for memory and second trench capacitors of the plurality of trench capacitors of the first DRAM array are coupled to a power bus,
wherein the first trench capacitors selections are dynamically allocated to be used of which ones of the plurality of DRAM arrays are used for memory and the second trench capacitors are dynamically allocated for to be which other ones of the plurality of DRAM arrays, not used for memory, have trench capacitors thereof coupled to the power bus in combination with other elements of the claim.
Regarding claim 19, the prior art does not teach a system of integrated circuit (IC) dice arranged in a three-dimensional stacked configuration, comprising: each of the plurality of DRAM arrays comprising a plurality of trench capacitors and support circuits therefor; wherein first trench capacitors of the plurality of trench capacitors of a first DRAM array are used for memory and second trench capacitors of the plurality of trench capacitors of the first DRAM array coupled to a power bus, wherein a configuration selection circuit is programmed to select which ones a first one or more of the plurality of DRAM arrays to be used for memory and which other ones a second one or more of the plurality of DRAM arrays, not used for memory, have trench capacitors thereof coupled to the power bus and are not used for memory in combination with other elements of the claim.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that the prior art does not teach that that the DRAM array comprises power coupling trench capacitors and memory trench capacitors.
The applicant will note that Luk (5790839) illustrates that the array comprises a dynamic random access memory portion for storing data and a decoupling capacitor portion for coupling to the power supply. When this is considered with Chen (2004/0157163), it would have been obvious to one of ordinary skill in the art that “forming trench capacitor cells in conventional DRAM technology” suggests that both portions comprise trench capacitors formed using the same processes.
Previous rejections of claims 6 through 10 and 18 under 35 USC 112(b), second paragraph have been overcome.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 February 4, 2026