DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 1 – 3, 8, 9, 11, 16 - 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (10573699).
7With regard to claim 1, Park et al. disclose a display device (for example, see fig. 7) comprising:
a substrate (for example, see abstract);
a sub-pixel (referred to as “P1” by examiner’s annotation shown in fig. 7 below) including:
a transistor including an active pattern (referred to as “EA1” by examiner’s annotation shown in fig. 7 below; wherein the active pattern EA1 is one of the active patterns EA) disposed on the substrate and a gate electrode (referred to as “EG1” by examiner’s annotation shown in fig. 7 below; wherein the gate electrode EG1 is one of the gate electrodes EG) disposed on the active pattern (EG1) and defining a channel area (a channel area forming in the active pattern EA1, forming under the gate electrode EG1) in an area overlapping the active pattern (EG1); and
a light emitting element (OLE as shown in fig. 7) disposed on (on a side or a top side) the transistor;
a sensing signal line (EL) disposed on the gate electrode (EG1) to overlap the channel area (the channel area forming in the active pattern EA1, forming under the gate electrode EG1) and that inherently transmits a sensing signal (a sensing signal from the sensing gate line EL) to the gate electrode (EG1);
a source line (ES) including at least a portion (referred to as “ES1” by examiner’s annotation shown in fig. 7 below; wherein the source line ES1 is a central portion of the source line ES) extending longitudinally in a first direction (for example, Y-direction in fig. 7), electrically connected to the active pattern (EA1) of the transistor, and that transmits an initialization voltage (initialization voltage from the conductive line REF (for example, column 6, lines 42, 43) to the active pattern (EA1) of the transistor; and
a symmetric sub-pixel (referred to as “P2” by examiner’s annotation shown in fig. 7 below) having a same structure as the sub-pixel (P1), adjacent to the sub-pixel (P1) in a second direction (for example, X-direction) intersecting the first direction (for example, Y-direction), and symmetrical to the sub-pixel (P1) with respect to an imaginary symmetric line (a conductive line REF functioning as an imaginary symmetric line) extending longitudinally in the first direction to pass through a center of at least the portion (referred to as “C1” by examiner’s annotation shown in fig. 7 below) of the source line (ES) that extends longitudinally in the first direction (for example, Y-direction).
PNG
media_image1.png
701
709
media_image1.png
Greyscale
With regard to claim 2, Park et al. disclose the sub-pixel (P1) and the symmetric sub-pixel (P2) share the source line (ES).
With regard to claim 3, Park et al. disclose an entirety of the gate electrode (EG1, as shown in fig. 7) overlaps the sensing signal line (EL).
With regard to claim 8, Park et al. disclose the source line (ES) and the sensing signal line (EL) are disposed on a same layer (any layer or a buffer layer or a substrate layer, forming below the sensing signal line and the source line, functioning as a same layer).
With regard to claim 9, Park et al. disclose the source line (ES) and the sensing signal line (EL) extend in a same direction (X-direction).
With regard to claim 11, Park et al. disclose the sub-pixel further includes a storage capacitor (Cst, fig. 7) including a first electrode and second electrode (a capacitor including a first electrode connected between the switching thin film transistor and the driving thin film transistor and a second electrode connected between the driving thin film transistor and a light emitting element; for example, see claim 18), the first electrode and the gate electrode are disposed on a same layer (any connecting layer, forming below the first electrode and the gate electrode, functioning as a same layer), and the second electrode (the second electrode connected between the driving thin film transistor and a light emitting element) and the sensing signal line (EL) are disposed on a same layer (any layer or a buffer layer or a substrate layer, forming below the second electrode and the sensing signal line, functioning as a same layer).
With regard to claim 16, Park et al. disclose the sub-pixel (P1) is a red sub-pixel and the symmetric sub-pixel (P2) is a blue or green sub-pixel.
PNG
media_image1.png
701
709
media_image1.png
Greyscale
With regard to claim 17, Park et al. disclose an electronic device (for example, a panel display, as shown in abstract, functioning as an electronic device) comprising display device (for example, see fig. 7) comprising:
a substrate (for example, see abstract);
a sub-pixel (referred to as “P1” by examiner’s annotation shown in fig. 7 below) including:
a transistor (a transistor including an active pattern (referred to as “EA1” by examiner’s annotation shown in fig. 7 below; wherein the active pattern EA1 is one of the active patterns EA) disposed on the substrate; and
a light emitting element (OLE as shown in fig. 7) disposed on (on a side or a top side) the transistor;
a source line (ES) including at least a portion (referred to as “ES1” by examiner’s annotation shown in fig. 7 below; wherein the source line ES1 is a central portion of the source line ES) extending longitudinally in a first direction (for example, Y-direction in fig. 7), electrically connected to the active pattern (EA1) of the transistor, and that transmits an initialization voltage (initialization voltage from the conductive line REF (for example, column 6, lines 42, 43) to the active pattern (EA1) of the transistor; and
a symmetric sub-pixel (referred to as “P2” by examiner’s annotation shown in fig. 7 below) having a same structure as the sub-pixel (P1), adjacent to the sub-pixel (P1) in a second direction (for example, X-direction) intersecting the first direction (for example, Y-direction), and symmetrical to the sub-pixel (P1) with respect to an imaginary symmetric line (a conductive line REF functioning as an imaginary symmetric line) extending longitudinally in the first direction to pass through a center of at least the portion (referred to as “C1” by examiner’s annotation shown in fig. 7 below) of the source line (ES) that extends longitudinally in the first direction (for example, Y-direction).
PNG
media_image2.png
701
709
media_image2.png
Greyscale
With regard to claim 18, Park et al. disclose the sub-pixel (P1) and the symmetric sub-pixel share (P2) the source line (ES).
With regard to claim 19, Park et al. disclose the transistor includes: an active pattern (referred to as “EA1” by examiner’s annotation shown in fig. 7 below; wherein the active pattern EA1 is one of the active patterns EA) disposed on the substrate; and a gate electrode (referred to as “EG1” by examiner’s annotation shown in fig. 7 below; wherein the gate electrode EG1 is one of the gate electrodes EG) defining a channel area (a channel area forming in the active pattern EA1, forming under the gate electrode EG1) in an area overlapping the active pattern (EG1).
With regard to claim 20, Park et al. disclose the sub-pixel further includes a storage capacitor (Cst, fig. 7) including a first electrode and second electrode (a capacitor including a first electrode connected between the switching thin film transistor and the driving thin film transistor and a second electrode connected between the driving thin film transistor and a light emitting element; for example, see claim 18), the first electrode and the gate electrode are disposed on a same layer (any connecting layer, forming below the first electrode and the gate electrode, functioning as a same layer), and the second electrode (the second electrode connected between the driving thin film transistor and a light emitting element) and the source line (ES1) are disposed on a same layer (any layer or a buffer layer or a substrate layer, forming below the second electrode and the source line, functioning as a same layer).
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 4, 5, 12 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (10573699) in view of Lee et al. (US RE47839 E).
With regard to claims 4, 5, 12, Park et al. do not clearly disclose each of the gate electrode and the sensing signal line extends in the first direction wherein each of the gate electrode and the sensing signal line extends in the first direction, and the active pattern extends in the second direction, wherein a length of the sensing signal line in the first direction is greater than a length of the gate electrode in the first direction.
However, Lee et al. disclose each of the gate electrode (110) and the sensing signal line (160) extends in the first direction (for example, Y-direction), and the active pattern (130) extends in the second direction (some portions of the active layer 130 extending in the X-direction) wherein a length of the sensing signal line (160) in the first direction (for example, Y-direction) is greater than a length of the gate electrode (130) in the first direction (for example, Y-direction). (for example, see fig. 4).
PNG
media_image3.png
714
550
media_image3.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Park et al.’s device to have each of the gate electrode and the sensing signal line extends in the first direction wherein each of the gate electrode and the sensing signal line extends in the first direction, and the active pattern extends in the second direction, wherein a length of the sensing signal line in the first direction is greater than a length of the gate electrode in the first direction as taught by Lee et al. in order to secure a sensing result of the sensing line into sensing data to provide to an image processing circuit enhancing the reliability of the electrical connection between the vias and the semiconductor patterns for a stability operation of the semiconductor device as is known to one of ordinary skill in the art.
5. Claims 6, 7, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (10573699) in view of Kim et al. (8760419).
With regard to claims 6, 7, 10, Park et al. do not clearly disclose an insulating layer disposed between the gate electrode and the sensing signal line, wherein the sensing signal line is electrically connected to the gate electrode through a contact hole formed by removing a portion of the insulating layer wherein the contact hole is spaced apart from the active pattern in a plan view.
However, Kim et al. discloses an insulating layer (280) disposed between the gate electrode (SWG1) and the sensing signal line (a conductive line TG1, connecting to the sensing line SGL1, fig. 3, functioning as sensing signal line), wherein the sensing signal line (the conductive line (TG1) is electrically connected to the gate electrode (SWG1) through a contact hole (CNT1) formed by inherently removing a portion of the insulating layer (280) wherein the contact hole (CNT1) is spaced apart from the active pattern (222) in a plan view (a cross-sectional view including a plan view). (for example, see figs. 3, 4).
PNG
media_image4.png
434
652
media_image4.png
Greyscale
PNG
media_image5.png
639
562
media_image5.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Park et al.’s device to have an insulating layer disposed between the gate electrode and the sensing signal line, wherein the sensing signal line is electrically connected to the gate electrode through a contact hole formed by removing a portion of the insulating layer wherein the contact hole is spaced apart from the active pattern in a plan view as taught by Kim et al. in order to prevent damage to the semiconductor patterns and enhancing the reliability of the electrical connection between the vias and the semiconductor patterns for a stability operation of the semiconductor device as is known to one of ordinary skill in the art.
6. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (10573699) in view of Xu et al. (11967620).
With regard to claim 13, Park et al. do not clearly disclose the gate electrode and the sensing signal line include a same conductive material.
However, Xu et al. disclose the gate electrode and the sensing signal line include a same conductive material (the sensing signal line are located in a same layer and made of a same material as the gate electrode; for example, see claim 5 of Xu et al.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Park et al.’s device to have the gate electrode and the sensing signal line include a same conductive material as taught by Xu et al. in order to secure a sensing result of the sensing line into sensing data to provide to an image processing circuit enhancing the reliability of the electrical connection between the vias and the semiconductor patterns for a stability operation of the semiconductor device as is known to one of ordinary skill in the art.
7. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (10573699) in view of Oh et al. (10084030).
With regard to claim 15, Park et al. do not clearly disclose a data line disposed between the substrate and the active pattern, wherein the data line extends in the second direction, and the gate electrode extends in the first direction.
However, Xu et al. disclose a data line (a conductive line 180, directly connected to the active layer 163, functioning as a data line. Although the applicant uses terms different to those of Xu et al. to label the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. It would have been obvious to one of ordinary skill in the art at the time the invention was made to use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.) disposed between the substrate (100) and the active pattern (163), wherein the data line (a conductive line 180, directly connected to the active layer 163, functioning as a data line) extends in the second direction (for example, X-direction), and the gate electrode (110) extends in the first direction (for example, Z or Y-direction).
PNG
media_image6.png
477
694
media_image6.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Park et al.’s device to have a data line disposed between the substrate and the active pattern, wherein the data line extends in the second direction, and the gate electrode extends in the first direction as taught by Oh et al. in order to enhance a high data storage capacitance for a stability operation of the semiconductor device as is known to one of ordinary skill in the art.
Allowable Subject Matter
8. Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 14 is allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the active pattern includes: a second portion having a planer shape symmetrical to the first portion with respect to the imaginary symmetric line, and the transistor includes the second portion of the active pattern as recited in claim 14.
Response to Amendment
9. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
10. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights