DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 10, 2026 has been entered.
Response to Arguments
Applicant’s arguments, see Remarks, filed on April 10, 2026, with respect to claim 7 have been fully considered and are persuasive. The 35 USC § 112 (b) rejection of claim 7 has been withdrawn.
Applicant’s arguments, see Remarks, filed on April 10, 2026, with respect to the rejections of claims 1, 17, and 22 under 35 USC § 102 / 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Ning and England.
In summary, this application is not placed in a condition for an allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 8-10, 13-14, 17, and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Loh (US 2023/0197619 A1) in view of Ning (US 2021/0366532 A1) and England (US 2022/0051963 A1).
Regarding claim 1, Loh teaches an integrated circuit package (Figs. 3-4, ¶ [0027]: 102 ), comprising:
a die substrate (110; see ¶ [0027]; plain meaning of substrate: an element that spreads out underneath; IC die 110 is a die substrate since devices 112, 118-1, and 118-2 are mounted on it ) having a first die surface (top surface of 110) and a second die surface (bottom surface of 110) on an opposite side of the die substrate as the first die surface (bottom surface is on the opposite side of the top surface);
a die high voltage (¶ [0020]: VR 118 receives 20 V ) input power connection ( ¶ [0025]: 312&222-1) in the die substrate (Figs. 3-4 show 312&222-1 in 110) and arranged to receive a high voltage input power (¶ [0025], [0028]: VS1 or VS3) and transmit the high voltage input power to a high voltage power trace (¶ [0025]: 304 or ¶ [0028]: 404 ; or alternatively, 302, see ¶ [0025] or 402, see ¶ [0028]) located on the first die surface (304 and/or 404 includes 312&222&302/402, see [0025] and [0028]; hence, 304/404 routes to the top surface of 110);
a power converter module (¶ [0025], [0028]: 314 or 406) located on the first die surface (314 and/or 406 is on top surface of 110) and electrically connected to the high voltage power trace (Fig. 3-4 show 314/406 connected to 304/404), wherein the power converter module converts the high voltage input power to a low voltage output power ([0025]: VR1 or [0028]: VR3; also see ¶ [0020]: VR 118 downconverts to 1.1 V); and
a low voltage (¶ [0020]: VR 118 downconverts to 1.1 V ) power trace (¶ [0025]: 326&316 or ¶ [0028]: 418&408) located on the first die surface (BRI: portions of 326&316 or 418&408 are on the top surface of 110) and electrically connected to the power converter module to carry the low voltage output power to a circuit die (¶ [0016]: 112) located on the first die surface.
Loh further teaches the low voltage power trace (326&316 or 418&408) to be within the die substrate (110; see Fig. 3) . However, Loh does not teach a portion of the low voltage trace located laterally on the first die surface of the die substrate.
Ning, in the same field of invention, teaches a portion of the output voltage trace (see metal wiring of VR in Fig. 4; ¶ [0052]: “The voltage regulation unit 204 converts the external input first voltage Vext into the second voltage. The second voltage is then provided to the word line driver circuit 206 associated with the memory chip 201 through connection lines (e.g., a metal wiring layer) on the line substrate 301” ) to be located laterally (Fig. 4 shows metal wiring layer extending laterally on the top surface of 301) on the first surface (top surface) of the substrate (301).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Ning into the device of Loh to dispose a portion of the low voltage trace laterally on the first die surface of the die substrate. The ordinary artisan would have been motivated to modify Loh in the manner set forth above for at least the purpose of using substituting one wiring configuration of the output voltage trace (Ning Fig. 3 and ¶ [0050] explains the second voltage, i.e., output voltage of the voltage regulator, is directly connected to word line driver circuits of chips 201) with another wiring configuration (Fig. 4 and ¶ [0052] explains the second voltage is connected to the word line driver circuits through the metal wiring layer of substrate 301), for the same purpose of providing electrical connection of the low voltage output power to the circuit die (¶ [0052] ).
Ning further teach the input voltage trace (302,303, Vext, see Fig. 3 and ¶ [0052] ) located within the die substrate (301; note: Loh in view of Ning teaches 301 to be a die substrate). However, Loh in view of Ning does not teach a portion of the high voltage power trace located laterally on the first die surface of the die substrate.
England, in the same field of invention, teaches an input trace (99a; Fig. 1) located laterally on the first die surface (top surface of 44) of a substrate (44; ¶ [0048]: “input signal is routed from ball 46a, through copper vias 98 and traces 99a” ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of England into the device of Loh in view of Ning to dispose the high voltage power trace laterally on the first die surface of the die substrate. The ordinary artisan would have been motivated to modify Loh in view of Ning in the manner set forth above for at least the purpose of increasing routing options to increase routing density ( England ¶ [0048] ), reduce EM interference (¶ [0048] ), and fit the device according to package design specifications and restrictions (¶ [0048]: footprint of IC 22 with respect to interposer 33 ).
Regarding claim 2, the package of claim 1, wherein the die high voltage input power connection includes microbumps (Loh ¶ [0017]: die 110 has interconnects comprising of microbumps to facilitate electric connection to 106) located on the second die surface (Loh Figs. 3-4 shows interconnect 312 on the bottom surface of 110) and through substrate vias (222-1) electrically connected to the microbumps (see ¶ [0025]).
Regarding claim 3, the package of claim 1, wherein the high voltage input power is in a range of about 7 to about 22 Volts (Loh ¶ [0020]: VR 118 receives 20 V).
Regarding claim 4, the package of claim 1, wherein the low voltage output power is in a range of about 0.3 to about 1.5 Volts (Loh ¶ [0020]: VR 118 downconverts to 1.1 V).
Regarding claim 8, the package of claim 1, wherein the power converter module includes a capacitor submodule, inductor submodule, and transistor submodule (Loh ¶ [0020]) arranged as a vertical stack (¶ [0020] teaches each inductor, capacitor and transistor as discrete circuit components mounted at the top surface 212 of die 110).
Regarding claim 9, package of claim 1, wherein the power converter module is located on the first die surface between the high voltage power trace and the low voltage power trace (Loh Fig. 3 shows 314 on the top surface of 110 and between 304 and 326&316 along the horizontal axis; Loh Fig. 4 shows 406 between 404 and 418&408 along the horizontal axis).
Regarding claim 10, the package of claim 1, wherein the power convertor module is one of a plurality of power converter modules (Loh Fig. 3 shows two VR dies 118-1 and 118-2) and the power convertor modules are on the first die surface (both 118-1 and 118-2 are on the top surface of 110) and each connected to one of a plurality of the die high voltage input power connections (304 and 334) located adjacent to a perimeter of the die substrate (304 and 334 are at the left and right ends of 110).
Regarding claim 13, the package of claim 1, wherein the circuit die is a graphics processing unit circuit die (Loh ¶ [0016]).
Regarding claim 14, the package of claim 1, further including a package substrate (Loh Figs. 3-4 , [0015]: 106), wherein the die high voltage input power connection is connected to a high voltage power trace (Loh ¶ [0025]: 310 or ¶ [0028]: 404) on a first package surface (BRI: both 310 and/or 404 extend from the top surface of 106 to the bottom surface of 106) of the package substrate to carry the high voltage input power from a package input power connector (116-1) to the die high voltage input power connection (310 and/or 404 are part of trace 304/404 that carries input power to 118-1).
Regarding claim 17, Loh teaches a method of manufacturing an integrated circuit package (Figs. 3-4, ¶ [0027]: 102 ), comprising:
providing a die substrate (¶ [0027]; plain meaning of substrate: an element that spreads out underneath; IC die 110 is a die substrate since devices 112, 118-1, and 118-2 are mounted on it) having a first die surface (top surface of 110) and a second die surface (bottom surface of 110) on an opposite side of the die substrate as the first die surface (bottom surface is on the opposite side of the top surface);
forming a die high voltage (¶ [0020]: VR 118 receives 20 V ) input power connection ( ¶ [0025]: 312) in the die substrate (Figs. 3-4 show 312 in 110), including:
forming a high-power through-substrate via (¶ [0025]: 222-1) through the die substrate,
forming a high voltage power trace (¶ [0025]: 304 or ¶ [0028]: 404 ; or alternatively, 302, see ¶ [0025] or 402, see ¶ [0028]) on the first die surface (302 and/or 304 and/or 402, which are on the top surface of 110, are part of 302/402, see [0025], [0028]), and
forming a microbump (¶ [0017]: die 110 has interconnects comprising of microbumps to facilitate electric connection to 106) on the second die surface (Figs. 3-4 shows interconnect 312 on the bottom surface of 110), the microbump electrically connected to the through substrate via (see ¶ [0025]);
forming a low-voltage (¶ [0020]: VR 118 downconverts to 1.1 V ) power trace (¶ [0025]: 326&316 or ¶ [0028]: 418&408) on the first surface of the die substrate (BRI: portions of 326 or 418 are on the top surface of 110; also 316/408 are on the top surface of 110);
mounting a power converter module (¶ [0025], [0028]: 314 or 406) to the first die surface (314 and/or 406 is on top surface of 110), wherein:
the power convertor module is electrically connected to the high voltage power trace on the first die surface (Fig. 3-4 show 314/406 connected to 326/418 at the top surface of 110),
the power convertor module (¶ [0025], [0028]: 314 or 406) is electrically connected to the low voltage power trace on the first die surface (Fig. 3-4 show 314/406 connected to 326/418), and
the power converter module converts a high voltage input power (¶ [0020]: VR 118 receives 20 V; Fig. 3: VS1; Fig. 4: VS3 ) to a low voltage output power (¶ [0020]: VR 118 downconverts to 1.1 V; Fig. 3: VR1; Fig. 4: VR3 ) carried to the low voltage power trace (Figs. 3 shows VR1 applied to 326; Fig. 4 shows VR3 applied to 418); and
mounting a circuit die (¶ [0016]: 112) to the first die surface, wherein the circuit die is connected to the low voltage power trace on the first die surface (Figs. 3-4 shows 112 on the top surface of 110 and connected to 326/418).
Loh further teaches the low voltage power trace to be within the die substrate (see Fig. 3) . However, Loh does not teach a portion of the low voltage trace located laterally on the first die surface of the die substrate.
Ning, in the same field of invention, teaches forming a portion of the output voltage trace (see metal wiring of VR in Fig. 4; ¶ [0052]: “The voltage regulation unit 204 converts the external input first voltage Vext into the second voltage. The second voltage is then provided to the word line driver circuit 206 associated with the memory chip 201 through connection lines (e.g., a metal wiring layer) on the line substrate 301” ) to be located laterally (Fig. 4 shows metal wiring layer extending laterally on the top surface of 301) on the first surface (top surface) of the substrate (301).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Ning into the method of Loh to dispose a portion of the low voltage trace laterally on the first die surface of the die substrate. The ordinary artisan would have been motivated to modify Loh in the manner set forth above for at least the purpose of using substituting one wiring configuration of the output voltage trace (Ning Fig. 3 and ¶ [0050] explains the second voltage, i.e., output voltage of the voltage regulator, is directly connected to word line driver circuits of chips 201) with another configuration (Fig. 4 and ¶ [0052] explains the second voltage is connected to the word line driver circuits through the metal wiring layer of substrate 301), for the same purpose of providing electrical connection of the low voltage output power to the circuit die (¶ [0052] ).
Ning further teach the input voltage trace (302,303, Vext, see Fig. 3 and ¶ [0052] ) located within the die substrate (301; note: Loh in view of Ning teaches 301 to be a die substrate). However, Loh in view of Ning does not teach a portion of the high voltage power trace located laterally on the first die surface of the die substrate.
England, in the same field of invention, teaches forming an input trace (99a; Fig. 1) located laterally on the first die surface (top surface of 44) of a substrate (44; ¶ [0048]: “input signal is routed from ball 46a, through copper vias 98 and traces 99a” ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of England into the method of Loh in view of Ning to dispose the high voltage power trace laterally on the first die surface of the die substrate. The ordinary artisan would have been motivated to modify Loh in view of Ning in the manner set forth above for at least the purpose of increasing routing options to increase routing density ( England ¶ [0048] ), reduce EM interference (¶ [0048] ), and fit the device according to package design specifications and restrictions (¶ [0048]: footprint of IC 22 with respect to interposer 33 ).
Regarding claim 20, the method of claim 17, further including mounting the die substrate to a package substrate (Loh Figs. 3-4 , [0015]: 106), wherein the die high voltage input power connection is electrically connected to a high voltage power trace (¶ [0025]: 310 or ¶ [0028]: 404) on a first package surface (BRI: both 310 and/or 404 extend from the top surface of 106 to the bottom surface of 106) of the package substrate.
Regarding claim 21, the method of claim 17, further including: providing a package substrate (Loh Figs. 3-4 , [0015]: 106) having a first package surface and a second package surface; forming a high voltage power trace (Loh ¶ [0025]: 310 or ¶ [0028]: 404) on the first package surface of the package substrate (BRI: both 310 and/or 404 extend from the top surface of 106 to the bottom surface of 106); and connecting a package input power connector (116-1) to the high voltage power trace.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Loh (US 2023/0197619 A1), Ning (US 2021/0366532 A1), and England (US 2022/0051963 A1) as applied to claim 1 above, and in further view of Lin (US 2010/0246152 A1).
Regarding claim 5, Loh et al. teach the package of claim 1 but do not teach: wherein the low voltage power trace has a path length from the power converter module to the circuit die that is equal to about 10 mm or shorter.
Lin, in the same field of invention, teaches a device having metal traces ([0432]) with a length equal to about 10 mm or shorter ([0432]: 1 and 200 um, which converts to 0.001 to 0.2 mm)
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lin into the device of Loh et al. to have a path length from a power converter module to a circuit die that is equal to about 10 mm or shorter in an integrated circuit package at least comprising of a die substrate, a die high voltage input power connection in the die substrate, the power converter module on a first die surface, and a low power trace on the first die surface used to carry the low power to the circuit die. The ordinary artisan would have been motivated to modify Loh et al. in the manner set forth above for at least the purpose of routinely optimizing the length of the path length between the power converter module and the circuit die as this results in reducing the resistance of the path (Lin [0432]: resistance per unit length). Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP § 2144.05 (II) (A).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Loh (US 2023/0197619 A1), Ning (US 2021/0366532 A1), and England (US 2022/0051963 A1) as applied to claim 1 above, and in further view of Momose (US 2017/0317008 A1).
Regarding claim 6, Loh et al. teach the package of claim 1 but do not teach: wherein the die high voltage input power connection is within a distance of about 5 to 10 mm of a perimeter of the die substrate.
Momose, in the same field of invention, teaches a device with a connection (Fig. 6C: 12) within a distance (D1) of about 5 to 10 mm (Table 2 and [0062]: at least 0.5 mm) of a perimeter of the die substrate (10).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Momose into the device of Loh et al. to set a distance of about 5 to 10 mm between a die high voltage input connection and a perimeter of a die substrate in an integrated circuit package at least comprising of the die substrate, the die high voltage input power connection in the die substrate, a power converter module on a first die surface, and a low power trace on the first die surface used to carry the low power to the circuit die. The ordinary artisan would have been motivated to modify Loh et al. in the manner set forth above for at least the purpose of routinely optimizing the distance between the die high voltage input connection and a perimeter of a die substrate in order to prevent an insulation breakdown of the substrate (Momose [0062]). Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP § 2144.05 (II) (A).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Loh (US 2023/0197619 A1), Ning (US 2021/0366532 A1), and England (US 2022/0051963 A1) and as applied to claim 2, in further view of Zhuang (US 2017/0256508 A1).
Regarding claim 7, Loh et al. teach the package of claim 2, but does not teach wherein the microbumps of the die high voltage input power connection are arranged as a two-by-one dimensional array adjacent to a perimeter of the die substrate.
Zhuang, in the same field of invention, teaches bumps (40; see Fig. 4) that are arranged as a two-by-one dimensional array (see Fig. 4 and ¶ [0036] ) adjacent to a perimeter (outer edges of 4) of the die substrate (4; ¶ [0035]: 4 may be a substrate ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Zhuang into the device of Loh et al. to arrange the microbumps as two-by-one dimensional array adjacent to a perimeter of the die substrate. The ordinary artisan would have been motivated to modify Loh et al. in the manner set forth above for at least the purpose of using different array configurations (Zhuang teaches a different configuration in Fig. 15 and ¶ [0060]-[0061] ) for bumps to suit the dimensional needs of the mother board that the substrate is connected to (see ¶ [0037] ). See also MPEP § 2144.04 (IV) (B).
Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Loh (US 2023/0197619 A1), Ning (US 2021/0366532 A1), and England (US 2022/0051963 A1) and as applied to claim 1 and/or claim 17 above, in further view of Choi (US 2018/0190635 A1).
Regarding claim 11, Loh et al. teach the package of claim 1, but do not teach: further including a power controller module located on the first die surface and connected to adjust the power converter module to output the low voltage output power from the high voltage input power.
Choi, in the same field of invention, teaches an integrated circuit package further including a power controller module (Fig. 1, [0040]: PMIC 124 controls power to device 120) located on the first die surface (¶ [0042]: top surface of 110) and connected (Loh in view of Choi teaches this, see motivation below) to adjust the power converter module ([0040]: 124 controls and stabilizes the power; further, Fig. 17 and [0142] teaches PMIC providing various voltage levels to a plurality of devices; note: 719 is analogous to power converter module since it has passive devices) to output the low voltage output power (Vout1 to Vout6) from the high voltage input power (Vin).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Choi into the device of Loh et al. to include a power controller module on a first die surface, with the power controller module connected to adjust a power converter module to output the low voltage output power from the high voltage input power in an integrated circuit package at least comprising of a die substrate, a die high voltage input power connection in the die substrate, the power converter module on a first die surface, and a low power trace on the first die surface used to carry the low power to the circuit die. The ordinary artisan would have been motivated to modify Loh et al. in the manner set forth above for at least the purpose of connecting the power controller module to Loh’s power converter module, which is made of passive devices (Loh ¶ [0020]) and is analogous to the passive device 719 in Choi Fig. 17, in order to adjust the output of the power converter module by fanning out the output of the power converter module to a plurality of different devices on the package (Loh Fig. 17: AP, I/O interface, RAM, etc.), with these devices requiring different voltage levels (Choi [0142]). The ordinary artisan is further motivated to use the power controller module as current meters to measure the load current information of these devices (Choi [0143]).
Regarding claim 18, Loh et al. teach the method of claim 17, but does not teach: further including mounting a power controller module located on the first die surface and connected to adjust the power converter module to output the low voltage output power from the high voltage input power.
Choi, in the same field of invention, teaches a method of manufacturing an integrated circuit package further mounting a power controller module (Fig. 1, [0040]: PMIC 124 controls power to device 120) located on the first die surface (¶ [0042]: top surface of 110) and connected (Loh in view of Choi teaches this, see motivation below) to adjust the power converter module ([0040]: 124 controls and stabilizes the power; further, Fig. 17 and [0142] teaches PMIC providing various voltage levels to a plurality of devices; note: 719 is analogous to power converter module since it has passive devices) to output the low voltage output power (Vout1 to Vout6) from the high voltage input power (Vin).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Choi into the method of Loh et al. to mount a power controller module on a first die surface, with the power controller module connected to adjust a power converter module to output the low voltage output power from the high voltage input power in a method of manufacturing an integrated circuit package at least comprising of providing a die substrate, forming a die high voltage input power connection in the die substrate, mounting the power converter module on a first die surface, and forming a low power trace on the first die surface used to carry the low power to the circuit die. The ordinary artisan would have been motivated to modify Loh et al. in the manner set forth above for at least the purpose of connecting the power controller module to Loh’s power converter module, which is made of passive devices (Loh ¶ [0020]) and is analogous to the passive device 719 in Choi Fig. 17, in order to adjust the output of the power converter module by fanning out the output of the power converter module to a plurality of different devices on the package (Loh Fig. 17: AP, I/O interface, RAM, etc.), with these devices requiring different voltage levels (Choi [0142]). The ordinary artisan is further motivated to use the power controller module as current meters to measure the load current information of these devices (Choi [0143]).
Claims 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Loh (US 2023/0197619 A1), Ning (US 2021/0366532 A1), and England (US 2022/0051963 A1), as applied to claims 1 and 17 above, and further in view of Raj (US 2013/0003310 A1).
Regarding claim 12, Loh teaches the package of claim 1 but does not further teach a thermal cooling module located on the first die surface, wherein the thermal cooling module contacts the circuit die and the power converter module.
Raj, in the same field of invention, teaches a package comprising: a thermal cooling module (Fig. 5, [0044]: 510) located on the first surface (BRI: 510 is on top of the top surface of 312) of the die substrate (¶ [0032]: 312 is an interposer die), wherein the thermal cooling module contacts the circuit die and the power converter module (Fig. 5 shows 510 contacting processor 310 and VRM 314-1; Loh in view of Raj teaches processor to be specifically a GPU processor and VRM to be specifically a voltage converter).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Raj into the device of Loh to mount a thermal cooling module located on a first surface of a die substrate, wherein the thermal cooling module contacts a circuit die and a power converter module in an integrated circuit package at least comprising of the die substrate, a die high voltage input power connection in the die substrate, the power converter module on a first die surface, and a low power trace on the first die surface used to carry the low power to the circuit die. The ordinary artisan would have been motivated to modify Loh in the manner set forth above for at least the purpose of using thermal cooling module to dissipate the heat generated by the graphics processing unit circuit die and the power converter module (Raj [0044]).
Regarding claim 19, Loh teaches the method of claim 17 but does not further teach mounting a thermal cooling module on the first die surface, wherein the thermal cooling module contacts the circuit die and the power converter module.
Raj, in the same field of invention, teaches a method of manufacturing a package comprising: mounting a thermal cooling module (Fig. 5, [0044]: 510) on the first surface (BRI: 510 is on top of the top surface of 312) of the die substrate (¶ [0032]: 312 is an interposer die), wherein the thermal cooling module contacts the circuit die and the power converter module (Fig. 5 shows 510 contacting processor 310 and VRM 314-1; Loh in view of Raj teaches processor to be specifically a GPU processor and VRM to be specifically a voltage converter).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Raj into the method of Loh to mount a thermal cooling module on a first surface of a die substrate, wherein the thermal cooling module contacts a circuit die and a power converter module in a method of manufacturing an integrated circuit package at least comprising of providing the die substrate, forming a die high voltage input power connection in the die substrate, mounting the power converter module to a first die surface, and forming a low power trace on the first die surface used to carry the low power to the circuit die. The ordinary artisan would have been motivated to modify Loh in the manner set forth above for at least the purpose of using thermal cooling module to dissipate the heat generated by the graphics processing unit circuit die and the power converter module (Raj [0044]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Loh (US 2023/0197619 A1), Ning (US 2021/0366532 A1) and England (US 2022/0051963 A1), as applied to claim 14 above, and in further view of Kageyama (US 2016/0021748 A1).
Regarding claim 15, Loh et al. teach the package of claim 14 but do not teach: wherein the DC resistance loss across the low voltage power trace located on the first die surface of the die substrate is less than about 0.1 Ohm.
Kageyama, in the same field of invention, teaches a device wherein the DC resistance loss across a trace is less than about 0.1 ohm. ([0006]: several micro ohms to several milli ohms).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kageyama into the device of Loh et al. to set a DC resistance across the low voltage power trace located on the first die surface of the die substrate to be less than about 0.1 ohm in an integrated circuit package at least comprising of a die substrate, a die high voltage input power connection in the die substrate, a power converter module on a first die surface, the low power trace on the first die surface used to carry the low power to a circuit die, and a package substrate. The ordinary artisan would have been motivated to modify Loh et al. in the manner set forth above for at least the purpose of routinely optimizing (Kageyama [0058]-[0068]: r=ρ x L/S ) the resistance of the lower power trace that is used to carry the low power to a circuit die, by reducing the resistance to a level so that the circuit die can still function properly (Kageyama [0006]). Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP § 2144.05 (II) (A).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Loh (US 20230197619 A1), Ning (US 2021/0366532 A1) and England (US 2022/0051963 A1) as applied to claim 14 above, and in further view of Aygun (US 2020/0066641 A1).
Regarding claim 16, Loh et al. teach the package of claim 14 but do not teach: wherein a path length of the high voltage power trace on the package substrate equals a value in a range from about 30 to 50 mm
Aygun, in the same field of invention, teaches an integrated circuit package (Fig. 47: 5000) wherein a path length (length of L502) on a package substrate (5010) equals a value in a range from 30 to 50 mm (Fig. 47, [1564]: L502 between 50 mm to 70 mm).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Aygun into the device of Loh et al. to set a path length of a high voltage power trace on the package substrate equal to a value in a range from about 30 to 50 mm in an integrated circuit package at least comprising of a die substrate, a die high voltage input power connection in the die substrate, a power converter module on a first die surface, the low power trace on the first die surface used to carry the low power to a circuit die, and the package substrate with the high voltage power trace. The ordinary artisan would have been motivated to modify Loh et al. in the manner set forth above for at least the purpose of routinely optimizing the path length (as evidenced by Kageyama (US 20160021748 A1) [0058]: r=ρ x L/S ) of the of the high voltage power trace in order to reduce its resistance (Aygun [0101], [0978]). Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP § 2144.05 (II) (A).
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Loh (US 20230197619 A1) in view of Raj (US 2013/0003310 A1), Ning (US 2021/0366532 A1), and England (US 2022/0051963 A1)
Regarding claim 22, Loh teaches the integrated circuit package (Figs. 3-4, ¶ [0027]: 102 ), comprising:
a die substrate (¶ [0027]; plain meaning of substrate: an element that spreads out underneath; IC die 110 is a substrate since devices 112, 118-1, and 118-2 are mounted on it) having a first die surface (top surface of 110) and a second die surface (bottom surface of 110) on an opposite side of the die substrate as the first die surface (bottom surface is on the opposite side of the top surface);
a die high voltage (¶ [0020]: VR 118 receives 20 V ) input power connection ( ¶ [0025]: 312) in the die substrate (Figs. 3-4 show 312 in 110) and arranged to receive a high voltage input power (¶ [0025], [0028]: VS1 or VS3) and transmit the high voltage input power to a high voltage power trace (¶ [0025]: 304 or ¶ [0028]: 404 ; or alternatively, 302, see ¶ [0025] or 402, see ¶ [0028]) located on the first die surface (304 and/or 404 routes to the top surface of 110; alternatively, 302 / 402 is on the top surface of 110);
a power converter module (¶ [0025], [0028]: 314 or 406) located on the first die surface (314 and/or 406 is on top surface of 110) and electrically connected to the high voltage power trace (Fig. 3-4 show 314/406 connected to 304/404), wherein the power converter module converts the high voltage input power to a low voltage output power ([0025]: VR1 or [0028]: VR3; also see ¶ [0020]: VR 118 downconverts to 1.1 V);
a low voltage (¶ [0020]: VR 118 downconverts to 1.1 V ) power trace (¶ [0025]: 326 or ¶ [0028]: 418) located on the first die surface (BRI: portions of 326 or 418 are on the top surface of 110) and electrically connected to the power converter module to carry the low voltage output power to a graphics processing unit circuit die (¶ [0016]: 112 is a GPU) located on the first die surface;
a printed circuit board ([0015]: 106 is a PCB), wherein the die high voltage input power connection is connected by a high voltage through-substrate via (¶ [0025]: 310 or ¶ [0028]: 404) to a high voltage power (VS1 or VS3) on a first printed circuit board surface to carry the high voltage input power to the die high voltage input power connection (310/404 connects VS1/VS3 to 312).
However, Loh does not teach a package further comprising: a thermal cooling module located on the first surface of the die substrate, wherein the thermal cooling module contacts the graphics processing unit circuit die and the power converter module.
Raj, in the same field of invention, teaches a package comprising: a thermal cooling module (Fig. 5, [0044]: 510) located on the first surface (BRI: 510 is on top of the top surface of 312) of the die substrate (¶ [0032]: 312 is an interposer die), wherein the thermal cooling module contacts the graphics processing unit circuit die and the power converter module (Fig. 5 shows 510 contacting processor 310 and VRM 314-1; Loh in view of Raj teaches processor to be specifically a GPU processor and VRM to be specifically a voltage converter).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Raj into the device of Loh to mount a thermal cooling module located on a first surface of a die substrate, wherein the thermal cooling module contacts a graphics processing unit circuit die and a power converter module in an integrated circuit package at least comprising of the die substrate, a die high voltage input power connection in the die substrate, the power converter module on a first die surface, a low power trace on the first die surface used to carry the low power to the graphics processing unit circuit die, and a printed circuit board. The ordinary artisan would have been motivated to modify Loh in the manner set forth above for at least the purpose of using thermal cooling module to dissipate the heat generated by the graphics processing unit circuit die and the power converter module (Raj [0044]).
Loh further teaches the low voltage power trace to be within the die substrate (see Fig. 3) . However, Loh does not teach a portion of the low voltage trace located laterally on the first die surface of the die substrate.
Ning, in the same field of invention, teaches a portion of the output voltage trace (see metal wiring of VR in Fig. 4; ¶ [0052]: “The voltage regulation unit 204 converts the external input first voltage Vext into the second voltage. The second voltage is then provided to the word line driver circuit 206 associated with the memory chip 201 through connection lines (e.g., a metal wiring layer) on the line substrate 301” ) to be located laterally (Fig. 4 shows metal wiring layer extending laterally on the top surface of 301) on the first surface (top surface) of the substrate (301).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Ning into the device of Loh to dispose a portion of the low voltage trace laterally on the first die surface of the die substrate. The ordinary artisan would have been motivated to modify Loh in the manner set forth above for at least the purpose of using substituting one wiring configuration of the output voltage trace (Ning Fig. 3 and ¶ [0050] explains the second voltage, i.e., output voltage of the voltage regulator, is directly connected to word line driver circuits of chips 201) with another configuration (Fig. 4 and ¶ [0052] explains the second voltage is connected to the word line driver circuits through the metal wiring layer of substrate 301), for the same purpose of providing electrical connection of the low voltage output power to the circuit die (¶ [0052] ).
Ning further teach the input voltage trace (302,303, Vext, see Fig. 3 and ¶ [0052] ) located within the die substrate (301; note: Loh in view of Ning teaches 301 to be a die substrate). However, Loh in view of Ning does not teach a portion of the high voltage power trace located laterally on the first die surface of the die substrate.
England, in the same field of invention, teaches an input trace (99a) located laterally on the first die surface (top surface of 44) of a substrate (44; ¶ [0048]: “input signal is routed from ball 46a, through copper vias 98 and traces 99a” ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of England into the device of Loh in view of Ning to dispose the high voltage power trace laterally on the first die surface of the die substrate. The ordinary artisan would have been motivated to modify Loh in view of Ning in the manner set forth above for at least the purpose of increasing routing options to increase routing density ( England ¶ [0048] ), reduce EM interference (¶ [0048] ), and fit the device according to package design specifications and restrictions (¶ [0048]: footprint of IC 22 with respect to interposer 33 ).
Regarding claim 23, a computer (Loh [0036]-[0038]: computer system) having one or more circuits that include the integrated circuit package of claim 22 (see claim 22 rejection above).
Conclusion
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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