DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/30/26 has been entered.
Claim Status
Previous action: claims 1 through 8 and 10 rejected, 12 through 18 withdrawn
Present action: claims 1 through 8, 10, and 19 rejected, 12 through 18 withdrawn
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 through 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a second conductive layer formed on the first conductive contact” in line 11.
However, the claim also recites that the first conductive contact is part of the first bonding layer (line 4) and that the second conductive layer is part of the second bonding layer (line 9). Further, the specification as filed recites that the second conductive layer is formed on the second conductive contact. The examiner will interpret the claims as “a second conductive layer formed on the second conductive contact”
Claims 2 through 8 depend from and incorporate claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3, 4, and 8 is/are rejected under 35 U.S.C. 102a1 as being antici3pated by Lii (US 2022/0238353)
Regarding claim 1.
Lii teaches:
A semiconductor device (fig 7; [para 0040]), comprising: a first semiconductor substrate (fig 6:2; [para 0015]) comprising: a first base (fig 6:20; [para 0015]);
a first bonding layer (fig 6,16a:42; [para 0022]) having a first through via (fig 4:44,52; [para 0026]);
and a first conductive contact (fig 4,6:54’; [para 0027]) formed within the first through via (fig 4:44,52; [para 0026]);
a first conductive layer (fig 16a:58a; [para 0033]) formed on the first conductive contact (fig 6,16a:54’; [para 0027]);
a second semiconductor substrate (fig 6:100; [para 0036]) comprising: a second base (fig 6:114; [para 0036]);
a second bonding layer (fig 6:142; [para 0037]) having a second through via (fig 6:152; [para 0037]);
and a second conductive contact (fig 6,17:154’; [para 0038]) formed within the second through via (fig 6:152; [para 0037]); a second conductive layer (fig 6,17:158a; [para 0045]) formed on the (fig 17:154’; [para 0042]);
and a solder (SnAg) (fig 17:58b,158b; [para 0042]) formed between the first conductive layer (fig 16a:58a; [para 0033]) and the second conductive layer (fig 6,17:158a; [para 0045]);
wherein the first conductive contact (fig 7,18a:54’; [para 0043]) is electrically connected to the second conductive contact (fig 7,18a:154’; [para 0038]), and the first bonding layer (fig 7,18a:42; [para 0040]) and the second bonding layer (fig 7,18a:142; [para 0040]) are in direct contact with each other (fig 7,18a; [para 0040]).
Regarding claim 2.
Lii teaches the semiconductor device as claimed in claim 1, wherein
Lii teaches:
there is no adhesive layer between the first bonding layer (fig 7,18a:42; [para 0040]) and the second bonding layer (fig 7,18a:142; [para 0040]).
Regarding claim 3.
Lii teaches the semiconductor device as claimed in claim 1, wherein
Lii teaches:
the first bonding layer (fig 7,18a:42; [para 0040])and the second bonding layer (fig 7,18a:142; [para 0040]) are formed of the same material ([para 0037]).
Regarding claim 4.
Lii teaches the semiconductor device as claimed in claim 1, wherein
Lii teaches:
the first base (fig 6:20; [para 0015]) is silicon based ([para 0015]), and the first semiconductor substrate (fig 6:2; [para 0015]) further comprises a first patterned-conductive layer (fig 1:30; [para 0019]) formed over the first base (fig 6:20; [para 0015]) and exposed from the first through via (fig 2:44; [para 0023]).
Regarding claim 8.
Lii teaches the semiconductor device as claimed in claim 1, wherein
Lii teaches:
the first semiconductor substrate (fig 6:2; [para 0015]) comprises a first barrier layer (fig 16a:48; [para 0024]) formed on a first lateral surface of the first through via (fig 4:44,52; [para 0026]).
Claim(s) 10 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lii (US 2022/0238353)
Regarding claim 10.
Lii teaches:
A semiconductor substrate (fig 6:2; [para 0015]), comprising: a base (fig 6:20; [para 0015]);
a bonding layer (fig 6,16a:42; [para 0022]) having a bonding surface (fig 6,16a:42t; [para 0030]) and a through via (fig 4:44,52; [para 0026]) extending from the bonding surface (fig 6,16a:42t; [para 0030]);
a conductive contact (fig 4,6:54’; [para 0027]) formed within the through via (fig 4:44,52; [para 0026]) and recessed (fig 6,16a:55; [para 0027]) with respect to the bonding surface (fig 6,16a:42t; [para 0030]);
a barrier layer (fig 16a:48; [para 0024])formed on a lateral surface of the through via (fig 4:44,52; [para 0026]) and having a first sidewall and a second sidewall opposite to the first sidewall;
a conductive layer (fig 16a:58a; [para 0033]) formed on the conductive contact (fig 4,6:54’; [para 0027]) and extending from the first sidewall to the second sidewall;
and a solder (SnAg) (fig 17:58b,158b; [para 0042]) formed on the conductive layer (fig 4,6:54’; [para 0027]);
wherein the bonding surface (fig 6,16a:42t; [para 0030]) is a planarized surface ([para 0026]).
Claim(s) 19 is/are rejected under 35 U.S.C. 102a1 as being antici3pated by Lii (US 2022/0238353)
Regarding claim 19.
Lii teaches:
A semiconductor device, comprising: a first semiconductor substrate (fig 6:2; [para 0015]) comprising: a first base (fig 6:20; [para 0015]);
a first bonding layer (fig 6,16a:42; [para 0022]) having a first through via (fig 4:44,52; [para 0026]);
and a first conductive contact (fig 4,6:54’; [para 0027]) formed within the first through via (fig 4:44,52; [para 0026]);
a first conductive layer (fig 16a:58a; [para 0033]) formed on the first conductive contact (fig 4,6:54’; [para 0027]);
and a first barrier layer (fig 16a:48; [para 0024]) formed on a first lateral surface of the first through via (fig 4:44,52; [para 0026]) and having a first sidewall and a second sidewall opposite to the first sidewall;
a second semiconductor substrate (fig 6:100; [para 0036]) comprising: a second base (fig 6:114; [para 0036]);
a second bonding layer (fig 6:142; [para 0037]) having a second through via (fig 6:152; [para 0037]);and a second conductive contact (fig 6,17:154’; [para 0038]) formed within the second through via (fig 6:152; [para 0037]);
a solder (SnAg) (fig 17:58b,158b; [para 0042]) formed between the first conductive layer (fig 16a:58a; [para 0033]) and the second conductive contact (fig 6,17:154’; [para 0038]) and extending from the first sidewall to the second sidewall;
wherein the first conductive contact (fig 4,6:54’; [para 0027]) is electrically connected to the second conductive contact (fig 7,18a:154’; [para 0038]), and the first bonding layer (fig 7,18a:42; [para 0040]) and the second bonding layer (fig 7,18a:142; [para 0040]) are in direct contact with each other (fig 7,18a; [para 0040]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lii (US 2022/0238353) as applied to claim 1 and further in view of Edelstein (US 2014/0353828)
Regarding claim 5.
Lii teaches the semiconductor device as claimed in claim 1, above
Li teaches:
the first semiconductor substrate (fig 6:2; [para 0015]) further comprises a first patterned-conductive layer (fig 1:30; [para 0019]), .
Lii does not teach a conductive via formed within the first base.
Edelstein teaches:
the first semiconductor substrate (fig 1d:10; [para 0049]) further comprises a first patterned-conductive layer (fig 1d:32; [para 0049]), and a first conductive via (fig 1d:12; [para 0049]) formed within the first base (fig 1d:10; [para 0049]) which is electrically connected to the first patterned-conductive layer (fig 1d:32; [para 0049]).
It would have been obvious to one of ordinary skill in the art befoe the effective filing date of the claimed invention to provide vias within the first substrate in order to enable stacking connectivity and three dimensional device integration (paragraph 2).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lii (US 2022/0238353) as applied to claim 1 and further in view of Gao (US 2020/0013754)
Regarding claim 6.
Lii teaches the semiconductor device as claimed in claim 1, above
Lii does not teach another second bonding layer
Gao teaches:
the second semiconductor substrate (fig 1:102; [para 0033]) further comprises: two second patterned-conductive layers (fig 1:112; [para 0039]) formed over two sides of the second base (fig 1:104; [para 0034]);
another second bonding layer (fig 1:106; [para 0034]) wherein the second bonding layer (fig 1:106; [para 0034]) and the another second bonding layer (fig 1:106; [para 0034]) are formed over the two second patterned-conductive layers (fig 1:112; [para 0039]);
another second through via (fig 1:110; [para 0039]) wherein the second through via (fig 1:110; [para 0039]) and the another second through via (fig 1:110; [para 0039]) are formed within the second bonding layer (fig 1:106; [para 0034]) and the another second bonding layer (fig 1:106; [para 0034]), respectively;
another second conductive contact formed within the another second through via (fig 1:110; [para 0039]);
and a conductive via (fig 1:114; [para 0039]) electrically connecting the two second patterned-conductive layers (fig 1:112; [para 0039]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide another second bonding layer and another second through via with associated patterned conductive layers in order to enable a stack of die and thereby increasing the total functionality of the package
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lii (US 2022/0238353) as applied to claim 1 and further in view of Gao (US 2020/0013754)
Regarding claim 7.
Lii teaches the semiconductor device as claimed in claim 1, above
Lii does not teach a third bonding layer.
Gao teaches:
a third semiconductor substrate (fig 1:102; [para 0033]), comprising: a third base (fig 1:104; [para 0034]);
a third bonding layer (fig 1:106; [para 0034]) having a third through via (fig 1:110; [para 0036]);
and a third conductive contact formed within the third through via (fig 1:110; [para 0036]);
wherein the third semiconductor substrate (fig 1:102; [para 0033]) further comprises another second bonding layer (fig 1:106; [para 0034]), and the second bonding layer (fig 1:106; [para 0034]) and the another second bonding layer (fig 1:106; [para 0034]) are formed over two second patterned-conductive layers (fig 1:112; [para 0039]), respectively;
and the third bonding layer (fig 1:106; [para 0034]) and the another second bonding layer (fig 1:106; [para 0034]) are in direct contact with each other.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide another a third semiconductor structure in order to enable a stack of die and thereby increasing the total functionality of the package
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The claims are anticipated by newly applied reference Lii (US 2022/0238353)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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