Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response to response to RCE filed on 04/03/26.
Summary of claims
Claims 16-19 and 21-36 are pending.
Claims 16-19 and 21-36 are rejected.
Oath/Declaration
The oath/declaration filed on December 23th, 2020 is acceptable.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 16-19 and 21-36 provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of US Patent 11568123. Although the conflicting claims are not identical, they are not patentably distinct from each other.
This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented.
As claims 16-19 and 21-36 the scope of the claimed limitation of the instant application is essentially the same as claimed limitations of claims 1-20 of US Patent 11568123.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16, 19, 21-26, 29-33 and 35-36 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bruguler et al. (US Pub. 8887105).
As to claims 16 and 22 the prior art teach a method comprising:
predicting an etch depth profile of a layer of a modeled wafer based on a the calibrated etch model (see fig 1), the etch model configured to predict the etch depth profile based (i) on loading information that indicates dependence of an etch rate for a resist profile on a quantity, or a pattern, or both a quantity and a pattern, of material being etched, or (ii) on flux information that indicates dependence of an etch rate for a resist profile on an intensity, or a spread angle, or both an intensity and a spread angle, of radiation incident on the resist profile, or (iii) and/or on re-deposition information that indicates dependence of an etch rate for a resist profile on an amount of material removed from the resist profile that is re-deposited back on the resist profile, or (iv) any combination selected from (i) to (iii) (see fig 1-4 col. 8 lines 20 to col. 9 lines 40);
and using the predicted etch depth profile (v) to generate or enhance a metrology target design, (vi) to correct a photomask, (vii) to verify a post-etch process window, (viii) to co-optimize a lithography illumination and photomask, or (ix) as input for defect prediction of an inspection system, or (x) as input to a pattern fidelity control system to improve across wafer patterning performance or (xi) any combination selected from (v) to (x) (see fig 4-6 col. 9 lines 9-51 and col. 12 lines 33-65)
As to claims 19 and 36 the prior art teaches comprising using the predicted etch depth profile to generate or enhancing the metrology target design comprises adjusting one or more dimensions and/or a pattern of the metrology target design (see fig 1-4 col. 7 lines 50 to col. 8 lines 40).
As to claims 21, the prior art teach wherein the using the predicted etch depth profile further comprises using the predicted etch depth profile in rigorous coupled-wave analysis (RCWA) to generate or enhance a metrology target design (see fig 1-4 col. 8 lines 10 to col. 9 lines 20).
As to claims 23 and 29 the prior art teaches a method comprising:
calibrating an etch model using two or more selected from: cross-section profile of a layer of a wafer, scanning electron microscope measurement s from a layer of a wafer generated based on a corresponding etch process, or scatterometry measurements from a layer of a wafer generated based ona corresponding etch process (see fig 1-4 col. 8 lines 20 to col. 9 lines 40);
predicting an etch parameter of a layer of a modeled wafer based on the calibrated etch model (see fig 3-7 col. 6 lines 37 to col. 7 lines 30);
and using the predicted etch parameter to (i) correct a photomask, or (ii) verify a post- etch process window, or (iii) co-optimize a lithography illumination and photomask, or (iv) and/or generate or enhance a metrology target design, or (v) any combination selected from (i) to (iv) (see fig 4-6 col. 9 lines 9-51 and col. 12 lines 33-65).
As to claim 24 and 31 the prior art teaches wherein the combination of cross-section profile, scanning electron microscope, and scatterometry measurements include overlay data and alignment data (see fig 2-4 col 8 lines 10-65).
As to claim 25 and 32 the prior art teaches wherein the etch parameter comprises an etch bias of a plurality of patterns of the layer (see fig 3-5 col 8 lines 40 to col. 9 lines 20).
As to claims 26 and 33 the prior art teach wherein the etch parameter comprises an etch depth profile of the layer (see fig 3-5 col 9 lines 10 to col. 10 lines 50).
As to claims 30 and 35, the prior art teach a method comprising:
calibrating an etch model for predicting a cross-wafer etch fingerprint as input for wafer inspection or patterning control operations and having parameters that describe cross wafer variations of a corresponding etch process, using two or more selected from: a cross-wafer cross-section profile of a layer of wafer, scanning electron microscope measurements from a layer of a wafer generated based on the etch process, or scatterometry measurements from a layer of a wafer generated based on the etch process (see fig 1-4 col. 8 lines 20 to col. 9 lines 40);
predicting an etch parameter of a layer of a modeled wafer based on the calibrated etch model (see fig 3-7 col. 6 lines 37 to col. 7 lines 30);
and using the predicted etch parameter as input for defect prediction of an inspection system, or to a pattern fidelity control system to improve across wafer patterning performance (see fig 4-6 col. 9 lines 9-51 and col. 12 lines 33-65).
Allowable Subject Matter
Claims 17-18, 27-28 and 34 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH C TAT/Primary Examiner, Art Unit 2851
Prosecution Insights