DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claim 9 has been cancelled; claims 1, 7, 10 and 15 have been amended; claims 16-20 have been withdrawn from consideration; and claims 1-8 and 10-20 are currently pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 15 recite the limitation "nanosheet spacers of neighboring nanosheet devices " in lines 18-19 and 23-24, respectively. There is insufficient antecedent basis for this limitation in the claim. It is unclear whether “nanosheet spacers” refers to the previously recited “first spacer” and “second spacer,” which the claim recites “each comprise a nanosheet spacer.” It is also unclear whether “neighboring nanosheet devices” refers to the previously recites “first transistor” and “second transistor,” which the claim recites “each comprise a nanosheet device.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-6, 11, 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2021/0028112 A1, hereinafter “Kim”).
In regards to claim 1, Kim discloses (See, for example, Fig. 2) a semiconductor device array comprising:
a backside power distribution network (BSPDN) (Second wiring portion ML2 including metal wirings M2 and M3; See also Pars [0049]-[0051]);
a buried power rail (BPR) (120 in trench ST, See in Fig. 1) in contact (See, for example, Pars [0034] and [0036]) with the BSPDN;
a device layer comprising:
a first transistor (FINFET formed on active fin 105 on a first side of trench ST; including source/drain region 110 and gate structure GS, See also, Pars [0027] and [0028]);
a second transistor (FINFET formed on active fin 105 on a second, opposite side of trench ST, See also, Par [0027]);
a first spacer (164 on a first side of buried conductive wiring 120 within trench ST, See also Par [0035]); and
a second spacer (164 on a second side of buried conductive wiring 120 within trench ST, See also Par [0035]),
wherein: the first transistor is in contact with the first spacer (active fin 105 on the first side of trench ST is in contact with 164 through the active region 102 and device isolation layer 162; See also Fig. 3);
the second transistor is in contact with the second spacer (active fin 105 on the second side of trench ST is in contact with 164 through the active region 102 and device isolation layer 162; See also Fig. 3); and
the first transistor neighbors the second transistor (Active fins 105 on opposite sides of trench ST are neighboring transistors arranged on the active region 102, See also, Par [0033]);
the first transistor and the second transistor each comprise a nanosheet device (FINFETs formed on active fins 105 on opposite sides of trench ST, including source/drain regions 110 and gate structures GS, See Pars [0027] and [0028]. As set forth in the claim construction section above, applicant’s specification defines a “nanosheet device” to encompass a FinFET, “The nanosheet devices 114 can be field effect transistors (FETs), such as nanosheet FETs, vertical FETs (VTFETs), or FinFETs.”, See current application PG PUB Par [0022]);
the first spacer and the second spacer each comprise a nanosheet spacer (filling insulation portion 164 on a first side and on a second side of buried conductive wiring 120 within trench ST, See Pars [0035] and [0036]. Each filling insulation portion 164 is a dielectric sidewall structure disposed at a sidewall of the respective active region that isolates that active region from the conductive through structure 250, See Pars [0037]-[0038], which teach that forming 164 prevents undesired shorts between 250 and adjacent active regions.); and
a backside-connecting via (conductive thru structure 250, See Par [0036]) that is in contact with the first transistor (through buried conductive wiring 120 and contact structure 180 which contacts source/drain, See Pars [0044] and [0048]), the BPR (See, 250 directly contacts 120, See also Par [0036]-[0037]), the first spacer , and the second spacer (a portion of the conductive through structure 250 contacts 164 on both sides of 120…indicated by contact area CT1 in Fig. 3, See also Par [0037]);
wherein the backside-connecting via is in electrical contact with the first transistor (Conductive through structure 250 is electrically connected to the source/drain region 110 of the first transistor, See also Pars [0036], [0044] and [0048]),
and wherein the backside-connecting via is located between nanosheet spacers of neighboring nanosheet devices (conductive through structure 250 is disposed within trench ST between the filling insulation portions 164 located on opposite sides of buried conductive wiring 120; a portion of 250 contacts 164 on both sides of 120, indicated by contact area CT1 in Fig. 3, See Par [0037]. The active fins 105 on the opposite sides of trench ST are neighboring transistors arranged on the active 102, See Par [0033]. See also Fig. 3).
In regards to claim 15, Kim discloses (See, for example, Fig. 2) a semiconductor device array comprising:
a backside power distribution network (BSPDN) (Second wiring portion ML2 including metal wirings M2 and M3; See also Pars [0049]-[0051]);
a buried power rail (BPR) (120 in trench ST, See in Fig. 1) in contact (See, for example, Pars [0034] and [0036]) with the BSPDN;
a device layer comprising:
a first transistor (FINFET formed on active fin 105 on a first side of trench ST; including source/drain region 110 and gate structure GS, See also, Pars [0027] and [0028]);
a second transistor (FINFET formed on active fin 105 on a second, opposite side of trench ST, See also, Par [0027]);
a first spacer (164 on a first side of buried conductive wiring 120 within trench ST, See also Par [0035]); and
a second spacer (164 on a second side of buried conductive wiring 120 within trench ST, See also Par [0035]),
wherein: the first transistor is in contact with the first spacer (active fin 105 on the first side of trench ST is in contact with 164 through the active region 102 and device isolation layer 162; See also Fig. 3);
the second transistor is in contact with the second spacer (active fin 105 on the second side of trench ST is in contact with 164 through the active region 102 and device isolation layer 162; See also Fig. 3);
the first spacer neighbors the second spacer (164 on opposite sides of 120 are adjacent to each other within trench ST, See also Fig. 3 and Par [0035]);
the first transistor and the second transistor each comprise a nanosheet device (FINFETs formed on active fins 105 on opposite sides of trench ST, including source/drain regions 110 and gate structures GS, See Pars [0027] and [0028]. As set forth in the claim construction section above, applicant’s specification defines a “nanosheet device” to encompass a FinFET, “The nanosheet devices 114 can be field effect transistors (FETs), such as nanosheet FETs, vertical FETs (VTFETs), or FinFETs.”, See current application PG PUB Par [0022]);
the first spacer and the second spacer each comprise a nanosheet spacer (filling insulation portion 164 on a first side and on a second side of buried conductive wiring 120 within trench ST, See Pars [0035] and [0036]. Each filling insulation portion 164 is a dielectric sidewall structure disposed at a sidewall of the respective active region that isolates that active region from the conductive through structure 250, See Pars [0037]-[0038], which teach that forming 164 prevents undesired shorts between 250 and adjacent active regions.); and
the first transistor neighbors the second transistor (Active fins 105 on opposite sides of trench ST are neighboring transistors arranged on the active region 102, See also, Par [0033]); and
a backside-connecting via (conductive thru structure 250, See Par [0036]) that is in contact with the first transistor (through buried conductive wiring 120 and contact structure 180 which contacts source/drain, See Pars [0044] and [0048]), the BPR (See, 250 directly contacts 120, See also Par [0036]-[0037]), the first spacer , and the second spacer (a portion of the conductive through structure 250 contacts 164 on both sides of 120…indicated by contact area CT1 in Fig. 3, See also Par [0037]).
wherein: the second spacer prevents a short resulting from electrical contact between the second transistor and the backside-connecting via (Pars [0037]-[0038] teaches that forming 164 prevents undesired shorts between 250 and adjacent active regions);
the backside-connecting via is in electrical contact with a top surface of the first transistor (250 is electrically connected to the source/drain region 110 of the first transistor. The contact structure 180 includes a first contact area 180A that contacts a top surface of the source/drain region 110, See also Par [0044]);
and the backside-connecting via is located between nanosheet spacers of neighboring nanosheet devices (conductive through structure 250 is disposed within trench ST between the filling insulation portions 164 located on opposite sides of buried conductive wiring 120; a portion of 250 contacts 164 on both sides of 120, indicated by contact area CT1 in Fig. 3, See Par [0037]. The active fins 105 on the opposite sides of trench ST are neighboring transistors arranged on the active 102, See Par [0033]. See also Fig. 3).
the first spacer (164) and a first additional spacer (162/162b) surround the first transistor (surround the first active fin 105; See also Pars [0030] and [0035]); and
the second spacer (164) and a second additional spacer (162/162b) surround the second transistor (surround the first active fin 105; See also Pars [0030] and [0035]).
In regards to claim 2, Kim discloses (See, for example, Fig. 2) the second spacer prevents a short resulting from electrical contact between the second transistor and the backside-connecting via (Pars [0037]-[0038] teaches that forming 164 prevents undesired shorts between 250 and adjacent active regions).
In regards to claim 5, Kim discloses (See, for example, Fig. 5) a lower width of the backside-connecting via (250 is wider at the bottom, See Fig. 2)) beneath the first spacer and the second spacer (below 164 ) is wider than (250 gets narrow towards to the spacers) a middling width (width below the top surface of the 250T) of the backside-connecting via (250) between the first spacer and the second spacer.
In regards to claim 6, Kim discloses (See, for example, Fig. 2) the first spacer and the second spacer comprise an isolating dielectric metal (“filling insulation portion 164”, See, for example, Par [0066]).
In regards to claim 11, Kim discloses (See, for example, Figs. 2 and 3) the first spacer (164) and a first additional spacer (162b) surround the first transistor (surround the first active fin 105; See also Pars [0030] and [0035]); and the second spacer (164) and a second additional spacer (162b) surround the second transistor (surround the first active fin 105; See also Pars [0030] and [0035]).
In regards to claim 13, Kim discloses (See, for example, Figs. 2-3, Kim) that a third transistor is surrounded by a third spacer and a third additional spacer; and the third transistor is not in contact with the backside-connecting via (a plurality of active fins 105 arranged on the active region 102, See Figs. 1 and 2 and Par [0027]. The active fins 105 that are not adjacent to the trench ST containing the buried conductive wiring 120 and the conductive through structure 250 are not in contact with the backside-connecting via. These non-adjacent transistors are surrounded by respective portions of the device isolation layer 162 on their respective sides, including 162b, See also Par [0030]).
In regards to claim 14, Kim discloses (See, for example, Figs. 2-3) the first transistor and the second transistor are selected from a group consisting of a fin field effect transistor (FinFET), a vertical transport FET (VTFET), a semiconductor memory structure, and combinations thereof (See Pars [0027] and [0028] where the transistors are FINFET devices formed on active fins 105 with source/drain regions 110 and gate structures GS).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4, 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
In regards to claim 3, Kim discloses all limitations of claim 1 above except that the backside-connecting via is without metal voids.
However, forming a conductive via without metal voids is a well known in the art of semiconductor metallization because having voids would increase electrical resistance and degrade device reliability.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to form the backside-connecting via without voids because it is well-known in the art of semiconductor metallization to have a connecting metal via without voids because having voids would increase electrical resistance and degrade device reliability.
In regards to claim 4, Kim discloses (See, for example, Figs. 2 and 3) the backside-connecting via (250) comprises a bottom in contact with the BPR (120). Kim further teaches (See Par [0039]) that an upper end or end portion 250T of the conductive through structure 250 may be located lower than a level L1 of an upper surface 102T of the active region 102. In this manner, mutual electrical interference may be suppressed by ensuring a sufficient distance from the active fin 105 without forming the conductive through structure 250 to the upper surface 102T of the active region 102. For example, the conductive through structure 250 may have a size (e.g., a diameter or a width) of 20 nm to 500 nm, and a distance (e.g., a depth) of 200 nm to 3000 nm.
However, Kim fails to explicitly teach the backside-connecting via comprises a bottom in contact with the BPR, wherein a width of the bottom is at least one half of a top width of the backside-connecting via.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to arrive at a bottom width that is at least one half of the top width since it has been held that such design choice would ensure reliable electrical connection, and where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art and . In re Aller, 105 USPQ 233.
In regards to claim 10, Kim as modified above discloses (See, for example, Fig. 2, Kim) the metal is selected from a group consisting of Cobalt (Co) and Tungsten (W) (See Pars [0056]).
In regards to claim 12, Kim discloses (See, for example, Figs. 2-3) all limitations of claim 1 except that the first spacer and the second spacer have a thickness between five and twenty nanometers (nm).
Notwithstanding, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Furthermore, the specification contains no disclosure of either the critical nature of the claimed thickness range or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. See In re Woodruff, 919, f.2d 1575, 1578, 16 USPQ2d, 1936 (Fed. Cir. 1990).
Claims 1-8 and 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Huang et al. (US 2022/0375860 A1, hereinafter “Huang”).
In regards to claim 1, Kim discloses (See, for example, Fig. 2) a semiconductor device array comprising:
a backside power distribution network (BSPDN) (Second wiring portion ML2 including metal wirings M2 and M3; See also Pars [0049]-[0051]);
a buried power rail (BPR) (120 in trench ST, See in Fig. 1) in contact (See, for example, Pars [0034] and [0036]) with the BSPDN;
a device layer comprising:
a first transistor (FINFET formed on active fin 105 on a first side of trench ST; including source/drain region 110 and gate structure GS, See also, Pars [0027] and [0028]);
a second transistor (FINFET formed on active fin 105 on a second, opposite side of trench ST, See also, Par [0027]);
a first spacer (164 on a first side of buried conductive wiring 120 within trench ST, See also Par [0035]); and
a second spacer (164 on a second side of buried conductive wiring 120 within trench ST, See also Par [0035]),
wherein: the first transistor is in contact with the first spacer (active fin 105 on the first side of trench ST is in contact with 164 through the active region 102 and device isolation layer 162; See also Fig. 3);
the second transistor is in contact with the second spacer (active fin 105 on the second side of trench ST is in contact with 164 through the active region 102 and device isolation layer 162; See also Fig. 3); and
the first transistor neighbors the second transistor (Active fins 105 on opposite sides of trench ST are neighboring transistors arranged on the active region 102, See also, Par [0033]);
a backside-connecting via (conductive thru structure 250, See Par [0036]) that is in contact with the first transistor (through buried conductive wiring 120 and contact structure 180 which contacts source/drain, See Pars [0044] and [0048]), the BPR (See, 250 directly contacts 120, See also Par [0036]-[0037]), the first spacer , and the second spacer (a portion of the conductive through structure 250 contacts 164 on both sides of 120…indicated by contact area CT1 in Fig. 3, See also Par [0037]);
wherein the backside-connecting via is in electrical contact with the first transistor (Conductive through structure 250 is electrically connected to the source/drain region 110 of the first transistor, See also Pars [0036], [0044] and [0048]),
KIM is silent about the first transistor and the second transistor each comprise a nanosheet device; the first spacer and the second spacer each comprise a nanosheet spacer; and wherein the backside-connecting via is located between nanosheet spacers of neighboring nanosheet devices
Huang teaches (See, for example, Fig. 19)
the first transistor and the second transistor each comprise a nanosheet device (FINFETs, See Par [0042]; “The nanosheet devices 114 can be field effect transistors (FETs), such as nanosheet FETs, vertical FETs (VTFETs), or FinFETs.”, See current application PG PUB Par [0022]); the first spacer and the second spacer each comprise a nanosheet spacer (113, See Par [0036]; See, for example, Fig. 19); and wherein the backside-connecting via (150) is located between nanosheet spacers (113) of neighboring nanosheet devices (FINFETs, Par [0036]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Kim by Huang because vertically stacked multi-channel devices offer superior electrostatic control and reduced short-channel leakage.
In regards to claim 15, Kim discloses (See, for example, Fig. 2) a semiconductor device array comprising:
a backside power distribution network (BSPDN) (Second wiring portion ML2 including metal wirings M2 and M3; See also Pars [0049]-[0051]);
a buried power rail (BPR) (120 in trench ST, See in Fig. 1) in contact (See, for example, Pars [0034] and [0036]) with the BSPDN;
a device layer comprising:
a first transistor (FINFET formed on active fin 105 on a first side of trench ST; including source/drain region 110 and gate structure GS, See also, Pars [0027] and [0028]);
a second transistor (FINFET formed on active fin 105 on a second, opposite side of trench ST, See also, Par [0027]);
a first spacer (164 on a first side of buried conductive wiring 120 within trench ST, See also Par [0035]); and
a second spacer (164 on a second side of buried conductive wiring 120 within trench ST, See also Par [0035]),
wherein: the first transistor is in contact with the first spacer (active fin 105 on the first side of trench ST is in contact with 164 through the active region 102 and device isolation layer 162; See also Fig. 3);
the second transistor is in contact with the second spacer (active fin 105 on the second side of trench ST is in contact with 164 through the active region 102 and device isolation layer 162; See also Fig. 3);
the first spacer neighbors the second spacer (164 on opposite sides of 120 are adjacent to each other within trench ST, See also Fig. 3 and Par [0035]);
the first transistor neighbors the second transistor (Active fins 105 on opposite sides of trench ST are neighboring transistors arranged on the active region 102, See also, Par [0033]); and
a backside-connecting via (conductive thru structure 250, See Par [0036]) that is in contact with the first transistor (through buried conductive wiring 120 and contact structure 180 which contacts source/drain, See Pars [0044] and [0048]), the BPR (See, 250 directly contacts 120, See also Par [0036]-[0037]), the first spacer , and the second spacer (a portion of
the conductive through structure 250 contacts 164 on both sides of 120…indicated by contact area CT1 in Fig. 3, See also Par [0037]).
wherein: the second spacer prevents a short resulting from electrical contact between the second transistor and the backside-connecting via (Pars [0037]-[0038] teaches that forming 164 prevents undesired shorts between 250 and adjacent active regions);
the backside-connecting via is in electrical contact with a top surface of the first transistor (250 is electrically connected to the source/drain region 110 of the first transistor. The contact structure 180 includes a first contact area 180A that contacts a top surface of the source/drain region 110, See also Par [0044]);
the first spacer (164) and a first additional spacer (162/162b) surround the first transistor (surround the first active fin 105; See also Pars [0030] and [0035]); and
the second spacer (164) and a second additional spacer (162/162b) surround the second transistor (surround the first active fin 105; See also Pars [0030] and [0035]).
KIM is silent about the first transistor and the second transistor each comprise a nanosheet device; the first spacer and the second spacer each comprise a nanosheet spacer; and wherein the backside-connecting via is located between nanosheet spacers of neighboring nanosheet devices
Huang teaches (See, for example, Fig. 19)
the first transistor and the second transistor each comprise a nanosheet device (FINFETs, See Par [0042]; “The nanosheet devices 114 can be field effect transistors (FETs), such as nanosheet FETs, vertical FETs (VTFETs), or FinFETs.”, See current application PG PUB Par [0022]); the first spacer and the second spacer each comprise a nanosheet spacer (113, See Par [0036]; See, for example, Fig. 19); and wherein the backside-connecting via (150) is located between nanosheet spacers (113) of neighboring nanosheet devices (FINFETs, Par [0036]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Kim by Huang because vertically stacked multi-channel devices offer superior electrostatic control and reduced short-channel leakage.
In regards to claim 2, Kim discloses (See, for example, Fig. 2) the second spacer prevents a short resulting from electrical contact between the second transistor and the backside-connecting via (Pars [0037]-[0038] teaches that forming 164 prevents undesired shorts between 250 and adjacent active regions).
In regards to claim 3, Kim discloses all limitations of claim 1 above except that the backside-connecting via is without metal voids.
However, forming a conductive via without metal voids is a well known in the art of semiconductor metallization because having voids would increase electrical resistance and degrade device reliability.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to form the backside-connecting via without voids because it is well-known in the art of semiconductor metallization to have a connecting metal via without voids because having voids would increase electrical resistance and degrade device reliability.
In regards to claim 4, Kim discloses (See, for example, Figs. 2 and 3) the backside-connecting via (250) comprises a bottom in contact with the BPR (120). Kim further teaches (See Par [0039]) that an upper end or end portion 250T of the conductive through structure 250 may be located lower than a level L1 of an upper surface 102T of the active region 102. In this manner, mutual electrical interference may be suppressed by ensuring a sufficient distance from the active fin 105 without forming the conductive through structure 250 to the upper surface 102T of the active region 102. For example, the conductive through structure 250 may have a size (e.g., a diameter or a width) of 20 nm to 500 nm, and a distance (e.g., a depth) of 200 nm to 3000 nm.
However, Kim fails to explicitly teach the backside-connecting via comprises a bottom in contact with the BPR, wherein a width of the bottom is at least one half of a top width of the backside-connecting via.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to arrive at a bottom width that is at least one half of the top width since it has been held that such design choice would ensure reliable electrical connection, and where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art and . In re Aller, 105 USPQ 233.
In regards to claim 10, Kim as modified above discloses (See, for example, Fig. 2, Kim) the metal is selected from a group consisting of Cobalt (Co) and Tungsten (W) (See Pars [0056]).
In regards to claim 12, Kim discloses (See, for example, Figs. 2-3) all limitations of claim 1 except that the first spacer and the second spacer have a thickness between five and twenty nanometers (nm).
Notwithstanding, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Furthermore, the specification contains no disclosure of either the critical nature of the claimed thickness range or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. See In re Woodruff, 919, f.2d 1575, 1578, 16 USPQ2d, 1936 (Fed. Cir. 1990).
In regards to claim 5, Kim discloses (See, for example, Fig. 5) a lower width of the backside-connecting via (250 is wider at the bottom, See Fig. 2)) beneath the first spacer and the second spacer (below 164 ) is wider than (250 gets narrow towards to the spacers) a middling width (width below the top surface of the 250T) of the backside-connecting via (250) between the first spacer and the second spacer.
In regards to claim 6, Kim discloses (See, for example, Fig. 2) the first spacer and the second spacer comprise an isolating dielectric metal (“filling insulation portion 164”, See, for example, Par [0066]).
In regards to claims 7 and 8, Kim discloses all limitations of claim 6 above except that the isolating dielectric metal comprises a nitride based dielectric material; and the nitride based dielectric material is selected from a group consisting of silicon nitride (SiN.sub.x), silicon boron carbonitride (SiBCN), silicon boronitride (SiBN), silicon carbon nitride (SiCN), silicon oxynitride (SiON), and combinations thereof.
Huang while disclosing transistors having backside power rails teaches the isolating dielectric metal comprises a nitride based dielectric material (The gate spacers 113 may include any suitable dielectric material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, other suitable dielectric materials, and/or combinations thereof. The gate spacers 113 may have multiple films, such as dual films (e.g., a silicon oxide film and a silicon nitride film) or three films (a silicon oxide film; a silicon nitride film; and a silicon oxide film)., See Fig. 17, See Par [0036]); and
the nitride based dielectric material is selected from a group consisting of silicon nitride (SiN.sub.x), silicon boron carbonitride (SiBCN), silicon boronitride (SiBN), silicon carbon nitride (SiCN), silicon oxynitride (SiON), and combinations thereof (See, for example, Par [0036]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Kim by Huang because having the dielectric material of Huang would help provide etch selectivity during backside processing and enhanced dielectric isolation between the conductive through structure and adjacent active regions.
In regards to claim 11, Kim discloses (See, for example, Figs. 2 and 3) the first spacer (164) and a first additional spacer (162b) surround the first transistor (surround the first active fin 105; See also Pars [0030] and [0035]); and the second spacer (164) and a second additional spacer (162b) surround the second transistor (surround the first active fin 105; See also Pars [0030] and [0035]).
In regards to claim 13, Kim discloses (See, for example, Figs. 2-3, Kim) that a third transistor is surrounded by a third spacer and a third additional spacer; and the third transistor is not in contact with the backside-connecting via (a plurality of active fins 105 arranged on the active region 102, See Figs. 1 and 2 and Par [0027]. The active fins 105 that are not adjacent to the trench ST containing the buried conductive wiring 120 and the conductive through structure 250 are not in contact with the backside-connecting via. These non-adjacent transistors are surrounded by respective portions of the device isolation layer 162 on their respective sides, including 162b, See also Par [0030]).
In regards to claim 14, Kim discloses (See, for example, Figs. 2-3) the first transistor and the second transistor are selected from a group consisting of a fin field effect transistor (FinFET), a vertical transport FET (VTFET), a semiconductor memory structure, and combinations thereof (See Pars [0027] and [0028] where the transistors are FINFET devices formed on active fins 105 with source/drain regions 110 and gate structures GS).
Response to Arguments
Applicant’s arguments with respect to claims 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
