DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claim 7, 21, and 24-27 are amended. Claims 1-6, 15-20, and 23 are cancelled. Claim 33 is new, no new matter is present. Claims 7-14, 21-22, and 24-33 are present for examination.
Specification
The title objection of September 25, 2025 has been withdrawn.
Response to Arguments
Applicant’s arguments, see pages 1-4, filed January 15, 2026, with respect to the 35 U.S.C. 103 rejections have been fully considered and are persuasive. The 35 U.S.C. 103 rejections of September 25, 2025 has been withdrawn.
Applicant’s arguments, see pages 1-4, filed January 15, 2026, with respect to the rejection(s) of claim(s) 21-24 and 26 under 35 U.S.C. 102 and claim 25 under 35 U.S.C. 103 have been fully considered but they are not persuasive as no limitations have been added to claim 21 that were not previously rejected on September 25, 2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-22, 24, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng (US 2020/0328213 A1).
Claim 21, Cheng discloses a method of forming a semiconductor device (Figs. 3A-3M), comprising:
forming fins (fin structures 106/108, further it is noted that fin structure 108 is sharing an element number with dummy gate dielectric layer 108, hereinafter fin structure 108 is 108F, [0017], Fig. 1) protruding from a substrate (fins 106/108F protrude from substrate 102, [0017], Fig. 1), wherein each of the fins has alternating stacked first nanostructures (semiconductor layers 110 are first nanostructures, [0020], Fig. 2) and second nanostructures (semiconductor layers 112 are second nanostructures, [0020], Fig. 2) arranged in a z-axis (110 and 112 are arranged alternating in the z-direction, [0020], Fig. 2);
removing the first nanostructures 110 to form gaps (spaces 126 and 136 as well as trenches 124/134 are gaps, hereinafter gaps 124/134/126/136, [0029], Fig. 3C) each between adjacent two of the second nanostructures 112 (110 is removed to form gaps 126/136 each between two vertically adjacent 112, [0037], Fig. 3D); and
forming a gate stack (gate all around (GAA) stack structures 160A/160B, [0057], Fig. 3M) wrapping around the second nanostructures 112 (160A/160B surround second nanostructures 112, [0057], Fig. 3M), wherein the gate stack comprises:
a gate dielectric layer (gate dielectric layer 128, [0040], Fig. 3E) wrapping around the second nanostructures 112 (128 wraps around 112, [0040], Fig. 3E); and
a p-type work function material on the gate dielectric layer 128 (p-type work function layer 156 and second portion of metal gate fill material 158-2, hereinafter p-type work function material 156/158-2 and are on the gate dielectric layer 128, [0052], Fig. 3K), wherein the p-type work function material 156/158-2 has a first thickness along the z-axis above a topmost one of the second nanostructures 112 (first thickness of p-type work function material 156/158-2 above a topmost one of the second nanostructures 112, is equivalent to the thickness of the p-type work function material layer 156/158-2, which is about 1.0 – 3.0 nm, wherein 10 Å = 1.0 nm and 30 Å = 3.0 nm, [0052], Fig. 3K) and a second thickness along the z-axis between neighboring two of the second nanostructures (thickness, d1, of first nanostructure 110, would be equivalent to a second thickness along the z-direction between neighboring two of the second nanostructures 112, which is about 8-10 nm, [0037], Figs. 3D and 3K), and the first thickness is less than the second thickness (first thickness: 1.0 – 3.0 nm < second thickness: 8 – 10 nm), the p-type work function material 156 between the neighboring two of the second nanostructures 112 comprises:
a first p-type work function layer (p-type work function layer 156, [0052], Fig. 3K); and
a second p-type work function layer (second portion of metal gate fill material 158-2 is a second p-type work function layer, [0054], Fig. 3K) on the first p-type work function layer 156 (158-2 is formed on 156, [0054], Fig. 3K).
Claim 22, Cheng discloses the method (Figs. 3A-3M) of claim 21, further comprising:
forming gate spacers (gate spacers 140, [0029], Fig. 3B) on opposite sides of the gate stack 160A/160B (140 are formed on opposite sides of 160A/160B, respectively, [0029], Figs. 3B and 3M), wherein the gate spacers 140 are separated in an x-axis perpendicular to the z-axis (140 are separated in an x-axis perpendicular to the z-axis, see Annotated Fig. 3M), the p-type work function material 156/158-2 has a portion between the gate spacers 140 with a third thickness along the z-axis, and the third thickness is less than the second thickness (third thickness: 1.5 nm, wherein 15 Å = 1.5 nm < second thickness: 8 – 10 nm, [0052], Annotated Fig. 3M).
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Annotated Fig. 3M (Cheng) - Illustrates gate spacers 140 on opposite sides of the gate stack 160A/160B, wherein the gate spacers 140 are separated in an x-axis perpendicular to the z-axis
Claim 24, Cheng discloses the method (Figs. 3A-3M) of claim 21, wherein the p-type work function material 156/158-2 above the topmost one of the second nanostructures 112 is free of the first p-type work function layer 156 (above the topmost one of 112 within pMOS region 100B is free of 156, Fig. 3K).
Claim 26, Cheng discloses the method (Figs. 3A-3M) of claim 21, wherein the second p-type work function layer 158-2 has a material different from a material of the first p-type work function layer 156 (158-2 and 156 are materially different, [0052]-[0053]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claim 21 above, and further in view of Lee (US 2021/0359096 A1).
Claim 25, Cheng discloses the method (Figs. 3A-3M) of claim 21.
Cheng does not explicitly disclose wherein in a y-axis perpendicular to the x-axis, the second nanostructures each have a width greater than a width of the first p-type work function layer.
However, Lee discloses wherein in a y-axis perpendicular to the x-axis, the second nanostructures (Lee, nanostructures 52 are second nanostructures and have a width in the y-direction of D1, that is greater than a width of the first p-type work function layer 105 denoted by T1, [0064], Fig. 18A; Cheng, Fig. 3M) each have a width greater than a width of the first p-type work function layer (Lee, D1, > T1, [0064], Fig. 18A; Cheng, Fig. 3M). The combination of manipulating the relative widths of the channel nanostructure as well as the first p-type work function layer avoids undesired merging of the p-type work function material as well as the channel nanostructure, as well as further reduction of threshold voltage variation in the resultant semiconductor device (Lee, [0064]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to manipulating the relative widths of the channel nanostructure as well as the first p-type work function layer to avoid undesired merging of the p-type work function material as well as the channel nanostructure, as well as further reduction of threshold voltage variation in the resultant semiconductor device.
Allowable Subject Matter
Claims 7-14 and 27-33 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art of record, Cheng (US 2020/0328213 A1), Wu (US 2020/0135588 A1), Savant (US 2021/0407861 A1), fails to disclose the following limitations in combination with the rest of the claim.
Regarding claim 7 (from which claims 8-14 and 33 depend), after etching the first p-type work function layer to break the first p-type work function layer into the first p-type work function sublayers.
Cheng discloses a method of forming a semiconductor device (Figs. 3A-3M), comprising:
forming fins (fin structures 106/108, further it is noted that fin structure 108 is sharing an element number with dummy gate dielectric layer 108, hereinafter fin structure 108 is 108F, [0017], Fig. 1) protruding from a substrate (fins 106/108F protrude from substrate 102, [0017], Fig. 1), wherein each of the fins has alternating stacked first nanostructures (semiconductor layers 110 are first nanostructures, [0020], Fig. 2) and second nanostructures (semiconductor layers 112 are second nanostructures, [0020], Fig. 2);
forming a dielectric fin (isolation structure 104 is a dielectric fin and is composed of a dielectric material, [0022], Fig. 2) on a first side of one of the fins 106 (dielectric fin 104 is on a first side of one of the fins 106, wherein the first side is the right-hand side of the fin, [0022], Fig. 3C);
forming an insulation material (interlayer dielectric (ILD) layer 144 is an insulation material, [0035], Fig. 3C) on a second side of the one of the fins 106 opposite to the first side (insulation material 144 is on a second side of one of the fins 106 opposite to the first side of the fin, wherein the second side is the left-hand side of the fin, [0022], Fig. 3C);
removing the first nanostructures 110 to form gaps (spaces 126 and 136 as well as trenches 124/134 are gaps, hereinafter gaps 124/134/126/136, [0029], Fig. 3C) each between adjacent two of the second nanostructures 112 (110 is removed to form gaps 126/136 each between two vertically adjacent 112, [0037], Fig. 3D);
forming a first p-type work function layer (p-type work function layer 156, [0052], Fig. 3K) continuously extending across the gaps 124/134/126/136 (156 extends continuously across 124/134/126/136, Fig. 3K);
etching the first p-type work function layer 156 to break the first p-type work function layer 156 into separate first p-type work function sublayers (156 is etched into separate sublayers of 156 within nMOS region 100A and pMOS region 100B, respectively, Figs. 3L and 3M) respectively confined within the gaps 124/134/126/136.
Cheng does not explicitly disclose forming a second p-type work function layer across the first p-type work function sublayers.
However, Cheng discloses forming a second work function layer that may also function as a second p-type work function layer depending on the thermal anneal and material utilized, further, the second work function layer further includes a first portion of a metal gate fill 158-1 wherein the metal gate fill is formed in-situ following deposition of the first p-type work function layer 156 and may also be formed of the same material as that of the first p-type work function layer 156. Further, the second portion of a metal gate fill 158-2 is formed in-situ following deposition of the first portion of a metal gate fill 158-1 and may also be formed of the same material as that of the first p-type work function layer 156. The combination to form a second p-type work function layer across the separate first p-type work function sublayers would allow for a separate first and second gate structure between the separate adjacent devices, as well as to enhance the conductivity of the resulting device and reduce voids (Cheng, [0056]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to form a second p-type work function layer spanning a first p-type work function layer deposited within the first and second gate structures between separate devices to prevent oxidation of the nanosheets and induce threshold voltage mismatch between opposite impurity type work function layers (Cheng, [0013]).
Cheng/Wu/Savant does not explicitly disclose the following limitations; after etching the first p-type work function layer to break the first p-type work function layer into the first p-type work function sublayers.
Regarding claim 27 (from which claims 28-32 depend), the separate first p-type work function sublayers overlap in a direction perpendicular to the substrate.
Cheng discloses a method of forming a semiconductor device (Figs. 3A-3M), comprising:
forming fins (fin structures 106/108, further it is noted that fin structure 108 is sharing an element number with dummy gate dielectric layer 108, hereinafter fin structure 108 is 108F, [0017], Fig. 1) protruding from a substrate (fins 106/108F protrude from substrate 102, [0017], Fig. 1), wherein each of the fins has alternating stacked first nanostructures (semiconductor layers 110 are first nanostructures, [0020], Fig. 2) and second nanostructures (semiconductor layers 112 are second nanostructures, [0020], Fig. 2);
removing the first nanostructures 110 to form gaps (spaces 126 and 136 as well as trenches 124/134 are gaps, hereinafter gaps 124/134/126/136, [0029], Fig. 3C) each between adjacent two of the second nanostructures 112 (110 is removed to form gaps 126/136 each between two vertically adjacent 112, [0037], Fig. 3D); and
performing a deposition process to form a first p-type work function layer 156 within the gaps 124/134/126/136 (first p-type work function layer 156 is formed via a deposition process (e.g. atomic layer deposition (ALD)), [0052], Fig. 3K), the first p-type work function layer 156 having a thickness (thickness of the p-type work function layer 156 is about 1.0 – 3.0 nm, wherein 10 Å = 1.0 nm and 30 Å = 3.0 nm, [0052], Fig. 3K) less than a vertical distance between the adjacent two of the second nanostructures 112 (thickness, d1, of first nanostructure 110, would be equivalent to a second thickness along the z-direction between neighboring two of the second nanostructures 112, which is about 8-10 nm, wherein the thickness of the first p-type work function layer 156 is less than a vertical distance between the adjacent two 112, [0037], Figs. 3D and 3K);
etching the first p-type work function layer 156 to break the first p-type work function layer 156 into separate first p-type work function sublayers (156 is etched into separate sublayers of 156 within nMOS region 100A and pMOS region 100B, respectively, Figs. 3L and 3M) respectively confined within the gaps 124/134/126/136.
Cheng does not explicitly disclose forming a second p-type work function layer across the first p-type work function sublayers.
However, Cheng discloses forming a second work function layer that may also function as a second p-type work function layer depending on the thermal anneal and material utilized, further, the second work function layer further includes a first portion of a metal gate fill 158-1 wherein the metal gate fill is formed in-situ following deposition of the first p-type work function layer 156 and may also be formed of the same material as that of the first p-type work function layer 156. Further, the second portion of a metal gate fill 158-2 is formed in-situ following deposition of the first portion of a metal gate fill 158-1 and may also be formed of the same material as that of the first p-type work function layer 156. The combination to form a second p-type work function layer across the separate first p-type work function sublayers would allow for a separate first and second gate structure between the separate adjacent devices, as well as to enhance the conductivity of the resulting device and reduce voids (Cheng, [0056]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to form a second p-type work function layer spanning a first p-type work function layer deposited within the first and second gate structures between separate devices to prevent oxidation of the nanosheets and induce threshold voltage mismatch between opposite impurity type work function layers (Cheng, [0013]).
Cheng/Wu/Savant does not explicitly disclose the following limitations; the separate first p-type work function sublayers overlap in a direction perpendicular to the substrate.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812