Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 5/23/2025 is acknowledged.
Please disregard Requirement for Restriction/Election sent 7/25/2025.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, 10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Dennen (6555872)
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Regarding claim 1, Dennen teaches an semiconductor device comprising:
a substrate comprising a working surface (please see figure above); and
a transistor formed in the substrate (please see figure above), the transistor comprising:
a complex channel structure (please see figure above) which is vertically arranged with respect to the working surface, the complex channel structure comprising first and second source-drain (S-D) ends (please see figure above) provided in a plane extending along the working surface to define an opening to a bounded region of the complex channel structure,
a gate dielectric layer (126) formed on the complex channel structure within the bounded region, and
a gate metal layer (128; Dennen teaches gate material being tungsten) formed on the gate dielectric layer within the bounded region to form the transistor.
Regarding claim 2, Dennen teaches an semiconductor device of claim 1, wherein the complex channel structure comprises: a first channel portion including the first S-D end and extending along a vertical direction perpendicular to the working surface to a first distal end; and a second channel portion including the second S-D end and extending along the vertical direction to a second distal end (please see figure above).
Regarding claim 3, Dennen teaches an semiconductor device of claim 2, wherein the first and second distal ends are connected to complete the complex channel structure (please see figure above).
Regarding claim 4, Dennen teaches an semiconductor device of claim 3, further comprising a third channel portion that extends in a horizontal direction along the working surface and connects the first and second distal ends to complete the complex channel structure (please see figure above).
Regarding claim 5, Dennen teaches an semiconductor device of claim 4, wherein the gate dielectric layer comprises a conformal layer formed on the first, second and third channel portions to form a complex dielectric structure (please see figure above).
Regarding claim 6, Dennen teaches an semiconductor device of claim 5, wherein the gate metal fills abounded region of the complex dielectric structure (please see figure above).
Regarding claim 7, Dennen teaches an semiconductor device of claim 4, wherein the complex channel structure has a U-shape in a vertical plane that is perpendicular to the working surface (please see figure above).
Regarding claim 8, Dennen teaches an semiconductor device of claim 1, further comprising a first wiring layer formed over the semiconductor device, the first wiring layer comprising electrical connections that connect to the gate metal and the first and second S-D ends (please see connections to gate, source and drain above).
Regarding claim 10, Dennen teaches an semiconductor device of claim 1, further comprising a plurality of complex channel structure transistors formed in the substrate (please see fig. 13).
Further, please note that mere duplication of parts has no patentable significance unless a new and unexpected result is produced
Allowable Subject Matter
Claim 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: a semiconductor device of claim 6, wherein: the complex channel structure comprises a conductive oxide layer; and the gate dielectric comprises a high-k dielectric material.
Claim 11 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: a semiconductor device of claim 10, wherein: the substrate and the plurality complex channel transistors collectively define a first transistor sheet; and a second transistor sheet is located above the first transistor sheet, the second transistor sheet further comprising: a second substrate disposed on the first substrate and having a second working surface opposite the first working surface; and a second plurality of complex channel transistors located within the second substrate, each having first and second S-D ends.
Claims 12 and 13 are objected to based on their dependency on claim 11.
Conclusion
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/CALEB E HENRY/Primary Examiner, Art Unit 2818