DETAILED ACTION
This action is responsive to the amendment received October 13, 2025. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 8 and 9 have the wrong status identifiers. The claims are drawn to non-elected species and were previously withdrawn from consideration in the prior Non-Final action (see p. 2).
Election/Restrictions
Claims 8, 9, 35, and 35 are drawn to non-elected Species VI (Fig. 2F), and are withdrawn from consideration.
Drawings
The drawing objection is withdrawn in view of the amended claims.
Claim Rejections - 35 USC § 112
The prior §112 rejection is withdrawn in view of the amended claims.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 28, 29, 40, and 41 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (US 2021/0407854), of record, in view of Adan (US 6,982,477) and Lane et al. (US 2008/0277765).
(Re Claim 28) Jeong teaches a method for manufacturing integrated circuits from a semiconductor substrate wafer, comprising:
forming integrated circuits in said semiconductor substrate wafer, wherein each integrated circuit includes an electrically active area (Figs. 1-3, device regions including active areas 101, S100, semiconductor wafer 100, ¶¶62-67);
forming a thermally conductive protective structure around the electrically active area of the integrated circuits along scribe paths, wherein the thermally conductive protective structure is located between the electrically active areas of said integrated circuits and a laser ablation area of the scribe paths (Fig. 3: 32 in region 103, metal is thermally conductive ¶70, laser ablation area scribe path 115); and
then separating the integrated circuits by scribing the semiconductor substrate wafer along the scribe paths, wherein scribing includes performing a laser ablation, in the laser ablation area followed by performing one of an etching or a physical scribing (see Fig. 1: S300 is laser ablation process followed by S400 plasma etching, Figs. 7-8C show laser ablation).
Regarding forming a shoulder in semiconductor substrate wafer around the electrically active areas of the various integrated circuits, it is noted Jeong indicates several (unlabeled) trench isolation regions (trapezoids across upper surface of substrate 10 in Fig. 3), however does not provide further details. A PHOSITA desiring to make and use Jeong’s device would be motivated to look to related art to provide details of trench isolation structures used in semiconductor devices and dicing processes. Related art from Adan shows that when forming trench isolation regions, they are conventionally formed such that they surround integrated circuit active regions (Figs. 2-3: 2). Forming the trench isolation regions according to Adan advantageously provides isolation around the entire die, from all directions. Therefore, a PHOSITA would find it obvious to form the trench isolations according to Adan, and in doing so, When making the trench isolation regions around the active circuit areas according to Adan, the claimed shoulder is met as the shoulder is half of a trench. Alternatively, related art from Lane similarly also shows how trench isolation regions may be formed and filled around the device areas (Figs. 3A-4: 60A/60B, also noting a plurality of isolation trenches may be formed in Figs. 7A-7C) in order to provide a protective barrier around the dies to mitigate cracking (¶¶43-49, 77, 83, 93). In view of Lane, a PHOSITA would find it obvious to form one or more trenches surrounding each die in order to protect the dies by mitigating cracking, and in doing so the claimed shoulder is present. Regardless, in view of either Adan and/or Lane, a PHOSITA would recognize numerous advantages from forming trenches, thereby forming shoulder(s), surrounding the dies for both isolation and protection purposes.
(Re Claim 29) wherein forming the thermally conductive protective structure comprises forming a stack of metal elements around the electrically active areas of the integrated circuits (Fig. 3, ¶70).
(Re Claim 40) wherein the etching comprises a plasma etching (Fig. 1: S400).
(Re Claim 41) wherein forming the thermally conductive protective structure is carried out simultaneously with forming other components of the integrated circuit.
While Jeong is silent regarding simultaneously forming the protective structure and other components of the integrated circuits, this would be obvious to a PHOSITA as the layers of metal in the protective structure 32 and in the device region 30 are formed in the same ILD structure. Doing so would simplify fabrication saving time and reducing cost.
Claims 30, 31, and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al., Adan, and Lane et al. as applied above, and further in view of Chen et al. (US 2010/0123219, Chen’219), of record, and Chen et al. (US 2022/0051993, Chen’993), of record.
(Re Claim 30) wherein the stack of metal elements is continuous around the electrically active areas.
(Re Claim 31) wherein the stack of metal elements is discontinuous around the electrically active areas.
Jeong is silent regarding whether the stack of metal elements are continuous or discontinuous. A PHOSITA desiring to make and use Jeong’s invention would be motivated to look to related art to teach these additional details. Related art from Chen’219 discloses the metal may be formed either continuously or discontinuously around the device regions (see Figs. 1-3 and ¶¶30,34-35,37-38). Related art from Chen’993 also teaches the metal may be formed continuously or discontinuously around the device regions (see Figs. 1-11 and ¶¶16-35). In view of the prior art teaching various continuous and discontinuous metal stacks, a PHOSITA would find both obvious to try, each working configuration being an obvious alternative according to the prior art.
(Re Claim 39) wherein forming each integrated circuit comprises forming a chip edge ring surrounding said electrically active area, and wherein the thermally conductive protective structure is located between the laser ablation area and the chip edge ring.
Jeong lacks an additional chip edge ring. A PHOSITA would be motivated to look to related art to teach different die seal/edge ring structures to see if alternative configurations may offer advantages. Related art from Chen’219 teaches a plurality of rings/seals (14, 16, 22). Related art from Chen’993 also teaches a plurality of rings/seals (240, 242, 244, 246). In view of Chen’993 and Chen’219 a PHOSITA would find it obvious to include one or more additional or redundant ring/seal structures to further protect the device from cracks, moisture, delamination, etc. since a single structure may have defects and/or cracks and/or moisture may be able to penetrate a first outer ring/seal and be stopped at a second or third structure.
Allowable Subject Matter
Claims 1, 3-6, and 10-14 are allowed.
Claims 8 and 9 will be rejoined when the application is in condition for allowance.
Claim 32 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 33 depends from claim 32 and is allowable based on dependency.
Claim 34 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 37 and 38 depend from claim 34 and are allowable based on dependency. Claims 35 and 36 will be rejoined when the application is in condition for allowance.
Response to Arguments
Applicant asserts new claim 28 is allowable. The Examiner respectfully disagrees, see new grounds of rejection above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches various trench/shoulder related structures.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898