DETAILED ACTION
This Office action is in response to the amendment filed 15 May 2026. By this amendment, claims 1-5 and 15-16 are amended. Claims 1-29 are currently pending; claims 6-14 and 17-29 stand withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 15 May 2026 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant argues McKnight does not disclose a second thermal pad thermally coupled to the front side of the die, and argues that “the Office Action improperly relies on paragraph [0094] to assert that conductive layer 130-2 provides a thermal pad” since said paragraph refers to a different embodiment. (Remarks, pp. 11-12.) Examiner respectfully disagrees; McKnight discloses conductive layer 130-2 to be formed of copper (¶ 0084; ¶ 0094 discloses 130-2 as a conductive layer, generally), and since copper is a thermally conductive material and in cited Fig. 29 130-2 is on an external surface of the die package, 130-2 is considered to read on the recited “second thermal pad.” Furthermore, cited ¶ 0096 refers to a “top side thermal pad” of embedded package 1000 of Fig. 29. Examiner notes the claims do not currently contain structural limitations or features that constitute a “thermal pad” that would preclude the current interpretation of the prior art.
Applicant also argues McKnight does not disclose heat dissipation from both the front side and the back side of the die. (Remarks, pp. 12-13.) Examiner respectfully disagrees; that McKnight does not expressly state that heat dissipation occurs from the front side and the back side of the die does not mean that heat dissipation does not occur. The package as shown in Fig. 29 of McKnight shows thermally conductive structures connected to the front side (top) of the die, which would enable heat to dissipate from the front side of the die, and expressly discloses a thermal pad 118 for heat dissipation on the back side of the die (¶ 0096). Thus, the prior art reads on the claims as currently drafted.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0020669 A1 to McKnight-MacNeil et al. (hereinafter “McKnight-MacNeil”).
Regarding independent claim 1, McKnight-MacNeil (Fig. 29) discloses an embedded die package comprising a laminated body and a die (Die; ¶ 0097) comprising a power semiconductor device (¶ 0097), the die being embedded within the laminated body,
the die having a front side (top) including an active region (¶ 0037) and a back side (bottom) opposite the front side (Fig. 29),
the laminated body comprising a stack of a plurality of dielectric build-up layers 120-1/120-2/120-3/110 (¶ 0094) and a plurality of electrically conductive layers 130-1/130-2/130-3 (¶ 0094),
a first side (bottom) of the package corresponding to the back side (bottom) of the die and a second side (top) of the package opposite the first side corresponding to the front side (top) of the die,
a first thermal pad 118 (¶ 0096) being provided on the first side (bottom) of the package and a second thermal pad 130-2 (¶ 0084) being provided on the second side (top) of the package,
the first thermal pad 118 being thermally coupled to the back side (bottom) of the die to provide a thermal path for heat dissipation from the back side of the die (¶ 0096),
the second thermal pad 130-2 being thermally coupled (Fig. 29 - thermally coupled to 130-1 and conductive vias to top side of Die) to the front side (top) of the die to provide a thermal path for heat dissipation from the front side (top) of the die (¶ 0084),
the first and second thermal pads 118/130-2 providing for dual-side cooling (¶ 0096; ¶ 0084 - 130-2 comprises copper, suitable for heat dissipation and cooling).
Regarding claim 2, McKnight-MacNeil (Fig. 29) discloses the embedded die package of claim 1, wherein the laminated body is based on a bottom-side-cooled layup that provides the first thermal pad 118 and electrical connections 130-3 (¶ 0084) for the power semiconductor device on the first side (bottom) of the package and the second thermal pad 130-2 is provided on the second side (top) of the package corresponding to the front side (top) of the die.
Regarding claim 3, McKnight-MacNeil (Fig. 29) discloses the embedded die package of claim 1, wherein the laminated body is based on a top-side cooled layup that provides the first thermal pad 118 on the first side (bottom) of the package and provides electrical connections 130-2 (¶ 0084) for the power semiconductor device on the second side (top) of the package, and the second thermal pad 130-2 is provided on the second side (top) of the package (Fig. 29). The term “top-side” as recited in the limitation “top-side cooled layup” is a directional term subject to the orientation of the embedded die package and has no recited relationship with the recited first or second side or the package or front or back side of the die that would constrain interpretation. Thus, the embedded die package may be oriented in such a way as to meet the above recited “top-side cooled layup.”
Regarding claim 4, McKnight-MacNeil (Fig. 29) discloses the embedded die package of claim 2, wherein one of said plurality of electrically conductive layers comprises a leadframe 114/116 (¶ 0095), the leadframe supporting the die within the laminated body and providing the first thermal pad 118 (Fig. 29).
Regarding claim 5, McKnight-MacNeil (Fig. 29) discloses the embedded die package of claim 3, wherein one of said plurality of electrically conductive layers comprises a leadframe 114/116, the leadframe supporting the die within the laminated body and providing the first thermal pad 118 (Fig. 29).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over McKnight-MacNeil.
Regarding independent claim 15, McKnight-MacNeil (Fig. 29) discloses an embedded die package 1000 (¶ 0096) comprising a laminated body 120-1/120-2/120-3/130-1/130-2/130-3 (¶¶ 0095-96) and a die (Die; ¶ 0097) comprising a power semiconductor device (¶ 0097), the die being embedded within the laminated body,
the die (Die; see also Fig. 6B, ¶ 0080) having a front side (top) including a patterned layer of conductive metallization providing electrical contact areas of the power semiconductor device (Fig. 29; ¶ 0080), and a back side (bottom) opposite the front side including a thermal contact area (118 connected thereto; ¶0095; Fig. 29); and
a layer stack of the laminated body comprises:
a first conductive layer comprising a leadframe 114/116 (¶ 0095) supporting the die and providing electrical contact areas and a primary thermal pad 118 (¶ 0096), the thermal contact area of the die being in thermal contact with the primary thermal pad of the leadframe (Fig. 29);
a first dielectric build-up layer 110 (¶ 0095) embedding the die and the leadframe;
a second conductive layer 130-1 (Examiner notes the reference line does not reach layer in Fig. 29 - conductive layer disposed on top surface of 120-1, ¶ 0094) on the first dielectric build-up layer 110;
the second conductive layer 130-1 being patterned to define interconnect areas (Fig. 29);
the interconnect areas of the second conductive layer being connected by electrically conductive vias (Fig. 29 - vias in contact with top surface of Die) to respective electrical contact areas of the power semiconductor device (Die);
a second dielectric build-up layer 120-2 (¶ 0095) on the second conductive layer;
a third conductive layer 130-2 (¶ 0096) on the second dielectric build-up layer 120-2;
the third conductive layer 130-2 being patterned to define a secondary thermal pad (Fig. 29; ¶ 0084 - 130-2 comprises copper, suitable for heat dissipation and cooling), the secondary thermal pad being thermally coupled (thermally coupled to 130-1 and vias to top side of Die) to the front side (top) of the die to provide a thermal path for heat dissipation from the front side of the die (Fig. 29); and
a fourth conductive layer 130-3 (¶ 0096) underlying the first conductive layer 114/116 and separated therefrom by another dielectric build-up layer 120-3 (¶ 0096), the fourth conductive layer forming an external thermal pad 130-3 which is in thermal contact with the primary thermal pad 118 of the first conductive layer, and the fourth conductive layer providing external electrical contact areas which are interconnected to respective contact areas of the first conductive layer (Fig. 29), the primary and secondary thermal pads providing for dual-side cooling (Fig. 29).
The instant embodiment fails to expressly disclose: the second conductive layer being connected to electrical contact areas of the leadframe 114/116. In another figure, McKnight-MacNeil (Fig. 25) discloses a conductive layer 132/134 (¶ 0095) being connected by electrically conductive vias to respective electrical contact areas of the power semiconductor devices (Die) and electrical contact areas of the leadframe 114/116 (¶ 0095). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide electrically connections between the second conductive layer and the leadframe for the purpose of electrical contact versatility and accommodating different types of die in the embedded die package.
Regarding claim 16, McKnight-MacNeil (Fig. 29) discloses the embedded die package of claim 15, wherein thermally conductive vias provide said thermal contact between the primary thermal pad 118 and the external thermal pad 130-3 (¶ 0096).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
22 July 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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