DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claims 1, 6, 8, 11, 13, and 19-20 filed on 09/22/2025 have been fully considered for examination based on their merits. The previously presented claims 2-5, 7,9-10, 12, and 14-18 have been considered.
Response to Arguments
Applicant’s arguments, see Remarks, pages 7-9, filed 09/22/2025, with respect to the rejection(s) of claim(s) 1-20 under U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of ZHANG.
Regarding independent claim(s) 1, 13, and 19. The Applicant argues that the Office failed to show the cited references teach at least the amended limitations to claims 1, 13, and 19. The Examiner agrees, and thus the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of ZHANG.
Regarding Claims 2-12, 14-18, and 20: The claims 2-12, 14-18, and 20 depend on the independent claims, 1, 13, and 19 and are follow similar arguments as Claim 1, 13, and 19, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jingyun Zhang et al, (hereinafter ZHANG), US 20210210489 A1.
Regarding Claim 1, ZHANG teaches, a semiconductor device structure (Fig. 1, 10, a semiconductor device, [0008]), comprising:
a dielectric wall (Fig. 5, 120, insulator pillar) disposed over a substrate (Fig. 5, 103, substrate pillar);
a plurality of first semiconductor layers (Fig. 5, 105, SiGe30 layers) and extended outwardly (annotated Figure 5) from a first sidewall (annotated Figure 5, 320, spacers, [0037]) of the dielectric wall (Fig. 5, 120, insulator pillar), at least one of the plurality of first semiconductor layers (Fig. 5, 105, SiGe30 layers) comprising a sidewall contiguous (annotated Figure 5) with the first sidewall (annotated Figure 5, 320, spacers, [0037]);
a plurality of second semiconductor layers (Fig. 5, 106, Si layers) vertically stacked (annotated Figure 5) and extended outwardly from a second sidewall (annotated Figure 5, 320, spacers, [0037]) of the dielectric wall (annotated Figure 15E/4 below, 306), at least one of the plurality of second semiconductor layers (Fig. 5, 106, Si layers) vertically comprising a sidewall contiguous (annotated Figure 5) with the second sidewall annotated Figure 5, 320, spacers, [0037]);
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a first epitaxial source/drain (S/D) feature (annotated Figure 9, 710, sacrificial undoped S/D regions) disposed adjacent the first sidewall (annotated Figure 9, 320, spacers, [0037]) of the dielectric wall (Fig. 9, 120, insulator pillar);
a second epitaxial S/D feature (annotated Figure 9, 710, sacrificial undoped S/D regions) disposed adjacent the second sidewall (annotated Figure 9, 320, spacers, [0037]) of the dielectric wall (Fig. 9, 120, insulator pillar);
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a first bottom dielectric layer (annotated Figure 5, material of the spacer, 320, [0037]) extended outwardly (annotated Figure 5) from the first sidewall (annotated Figure 5, 320, spacers, [0037]) of the dielectric wall (Fig. 5, 120, insulator pillar); and
a second bottom dielectric layer (annotated Figure 5, material of the spacer, 320, [0037]) extended outwardly (annotated Figure 5) from the second sidewall (annotated Figure 5, 320, spacers, [0037]) of the dielectric wall (Fig. 5, 120, insulator pillar).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of Huan-Chieh Su et al, (hereinafter SU), US 20210407994 A1, and further in view of Jung-Hung Chang et al, (hereinafter CHANG), US 20210375864 A1.
Regarding Claim 1, ZHANG teaches, a semiconductor device structure (Fig. 1, 10, a semiconductor device, [0008]), comprising:
a dielectric wall (Fig. 5, 120, insulator pillar) disposed over a substrate (Fig. 5, 103, substrate pillar);
a plurality of first semiconductor layers (Fig. 5, 105, SiGe30 layers) and extended outwardly (annotated Figure 5) from a first sidewall (annotated Figure 5, 320, spacers, [0037]) of the dielectric wall (Fig. 5, 120, insulator pillar), at least one of the plurality of first semiconductor layers (Fig. 5, 105, SiGe30 layers) comprising a sidewall contiguous (annotated Figure 5) with the first sidewall (annotated Figure 5, 320, spacers, [0037]);
a plurality of second semiconductor layers (Fig. 5, 106, Si layers) vertically stacked (annotated Figure 5) and extended outwardly from a second sidewall (annotated Figure 5, 320, spacers, [0037]) of the dielectric wall (annotated Figure 15E/4 below, 306), at least one of the plurality of second semiconductor layers (Fig. 5, 106, Si layers) vertically comprising a sidewall contiguous (annotated Figure 5) with the second sidewall annotated Figure 5, 320, spacers, [0037]);
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a first epitaxial source/drain (S/D) feature (annotated Figure 9, 710, sacrificial undoped S/D regions) disposed adjacent the first sidewall (annotated Figure 9, 320, spacers, [0037]) of the dielectric wall (Fig. 9, 120, insulator pillar);
a second epitaxial S/D feature (annotated Figure 9, 710, sacrificial undoped S/D regions) disposed adjacent the second sidewall (annotated Figure 9, 320, spacers, [0037]) of the dielectric wall (Fig. 9, 120, insulator pillar);
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a first bottom dielectric layer (annotated Figure 5, material of the spacer, 320, [0037]) extended outwardly (annotated Figure 5) from the first sidewall (annotated Figure 5, 320, spacers, [0037]) of the dielectric wall (Fig. 5, 120, insulator pillar); and
a second bottom dielectric layer (annotated Figure 5, material of the spacer, 320, [0037]) extended outwardly (annotated Figure 5) from the second sidewall (annotated Figure 5, 320, spacers, [0037]) of the dielectric wall (Fig. 5, 120, insulator pillar).
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Alternatively, SU teaches, a semiconductor device structure (Figs. 10A-10B, 100), comprising:
a dielectric wall (Figs. 17A-17B, 306, dielectric feature) disposed over a substrate (Fig. 14, 101);
a plurality of first semiconductor layers (Fig. 7B, 106) vertically stacked (Fig. 7B, Z-direction) and extended outwardly (Fig. 15H, Y- direction) from a first sidewall (Figs. 17A-17B, 1514, dielectric material) of the dielectric wall (Figs. 17A-17B, 306, dielectric feature), at least one of the plurality of first semiconductor layers (Fig. 17A, 106) comprising a sidewall contiguous (annotated Figure 17A) with the first sidewall (Figs. 17A-17B, 1514, dielectric material);
a plurality of second semiconductor layers (Fig. 7B, 108; gate stack, 1206 is replaced for 108, [0044]) vertically stacked (Z-direction) and extended outwardly (Fig. 15H, Y- direction) from a second sidewall (Figs. 17A-17B, 1514, dielectric material) of the dielectric wall (Figs. 17A-17B, 306, dielectric feature), at least one of the plurality of second semiconductor layers (Fig. 7B, 108; gate stack, 1206 is replaced for 108, [0044]) comprising a sidewall contiguous (annotated Figure 17A) with the second sidewall (Figs. 17A-17B, 1514, dielectric material);
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a first epitaxial source/drain (S/D) feature (Figs. 17A-17B, 902, S/D epitaxial layer) disposed adjacent the first sidewall (Figs. 17A-17B, 1514, dielectric material) of the dielectric wall (Figs. 17A-17B, 306, dielectric feature);
a second epitaxial S/D feature (Figs. 17A-17B, 902, S/D epitaxial layer) disposed adjacent the second sidewall (Figs. 17A-17B, 1514, dielectric material) of the dielectric wall (Figs. 17A-17B, 306, dielectric feature);
The rationale behind using ZHANG and SU, both as primary reference is based on their combination of features presented that are complementary to support the rejection. The prior art of ZHANG, wherein etching of the unmasked sacrificial undoped epitaxy S/D regions, 710 results in the redefinition of the cavities, 510 (as shown in Figure 12), and the entire removal of the sacrificial undoped epitaxy, S/D regions, 710 at the unmasked side of insulator pillar, 120 (as shown in Figure 13), however the doped pFET epitaxy, S/D regions, 1310 is formed in the cavities of Figure 12 and at a first side of the insulator pillar, 120, and the nFET epitaxy, 1320 is formed at the second side of the insulator pillar, 120 as shown in Figure 15 (see paragraphs [0042-0044]), which are similar to the instant application. On the other hand, prior art of SU, though the second semiconductor layer, 108 shown in Figure 12A is subsequently removed, and gaps, 1203 are formed between the dielectric spacers, 804, as shown in Figure 12B. This allows the formation of gate stack structure 1204/1206 around the first semiconductor layer, 106 (see paragraphs, [0044-0045]), align with the dielectric wall, 306, and the spacers, 1514, of the structure as shown in Figures 17A-17B, and are similar to the instant application. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have combined ZHANG and SU, such that a semiconductor device structure comprising: a plurality of semiconductor layers vertically stacked and extended outwardly from a first sidewall of the dielectric wall, at least one of the plurality of semiconductor layers comprising a sidewall contiguous (ZHANG, Figures 17A-17B; SU, Figures 5/9).
ZHANG in combination with SU does not explicitly disclose, a semiconductor device structure comprising: a first bottom dielectric layer extended; and a second bottom dielectric layer.
CHANG teaches in Figure 28A, a semiconductor device structure (200, workpiece) comprising: a first bottom dielectric layer (Fig. 28A, 2030, bottom oxide feature or dielectric feature, [0012]); and a second bottom dielectric layer Fig. 28A, 2030, bottom oxide feature or dielectric feature, [0012]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention (AIA ) to have modified ZHANG in combination with SU to incorporate the teachings of CHANG, such that a semiconductor device structure comprising: a first bottom dielectric layer; and a second bottom dielectric layer. The advantage of having the bottom dielectric feature or bottom oxide feature, that enables to facilitate insulation of the channel region from the bulk substrate (CHANG, [0012]).
Regarding Claim 2, ZHANG in combination with SU as modified by CHANG teaches the semiconductor device structure of claim 1.
CHANG further teaches in Figures 29A, the semiconductor device structure (200, workpiece) of claim 1, wherein the first bottom dielectric layer (Fig. 29A, 2030) is disposed below the first epitaxial S/D feature (Figs. 29A/29B, 242/244), and the second bottom dielectric layer (Fig. 29A, 2030) is disposed below the second epitaxial S/D feature (Figs. 29A/29B, drain regions 20, 242/244).
Regarding Claim 3, ZHANG in combination with SU as modified by CHANG teaches the semiconductor device structure of claim 2.
SU further teaches in Figures 15H/16A, the semiconductor device structure (100), wherein the second bottom dielectric layer (Figs. 15H/16A, 1522) is separated from the second epitaxial S/D feature (Fig. 15H, 902, S/D epitaxial layer) by a first air gap (Fig. 16A, 1602, [0063]).
Regarding Claim 4, ZHANG in combination with SU as modified by CHANG teaches the semiconductor device structure of claim 3.
CHANG further teaches in Figure 29A, the semiconductor device structure (200, workpiece), wherein the first bottom dielectric layer (Fig. 29A, 2030) is in contact with the first epitaxial S/D feature (Figs. 29A/29B, drain regions 20, 242/244).
Regarding Claim 5, ZHANG in combination with SU as modified by CHANG teaches the semiconductor device structure of claim 3.
SU further teaches in Figures 15H/16A, the semiconductor device structure (100), wherein the first bottom dielectric layer (Figs. 15H/16A, 1522) is separated from the first epitaxial S/D feature (Fig. 15H, 902, S/D epitaxial layer) by a second air gap (Fig. 16A, 1602, [0063]).
Regarding Claim 6 ZHANG in combination with SU as modified by CHANG teaches the semiconductor device structure of claim 1.
SU further teaches in Figures 10A-10B, the semiconductor device structure (100), comprising:
a first gate electrode layer (Fig. 12C, 1206) surrounding at least three surfaces of each of the first semiconductor layers (106), the first gate electrode layer having a first conductivity type (conductivity type (e.g. p-type or n-type conductivity), [0022]; gate electrode materials, [0047]; Si used for 106, [0044]); and
a second gate electrode layer (Fig. 12C, 1206) surrounding at least three surfaces of each of the second semiconductor layers (108), the second gate electrode layer having a second conductivity type opposite the first conductivity type (conductivity type (e.g. p-type or n-type conductivity), [0022]; gate electrode materials, [0047]; SiGe used for 108, [0044]);
Regarding Claim 7, ZHANG in combination with SU as modified by CHANG teaches the semiconductor device structure of claim 6.
CHANG further teaches in Figures 16/29A, the semiconductor device structure (200, workpiece), wherein the first bottom dielectric layer (Figs. 16/29A, 234/2030) is disposed below the first gate electrode layer (Figs. 16/29A, 252/220, first gate structure/gate stack), and the second bottom dielectric layer (Figs. 16/29A, 234/2030) is disposed below the second gate electrode layer (Figs. 16/29A, 254/220, first gate structure/gate stack).
Regarding Claim 8, ZHANG in combination with SU as modified by CHANG teaches the semiconductor device structure of claim 6.
CHANG teaches in Figure 16, the semiconductor device structure (200, workpiece), comprising: an interfacial layer (IL) (252/254 includes an interfacial layer, 250, ILD layer, [0040]) surrounding at least three surfaces of each of the first (106) and second semiconductor layers (108); and a high-k dielectric layer disposed on the IL ([0040]).
Regarding Claim 9, ZHANG in combination with SU as modified by CHANG teaches the semiconductor device structure of claim 8.
CHANG teaches in Figures 16/17, the semiconductor device structure (200, workpiece), wherein the IL is in contact with the high-k dielectric layer ([0040]), the first bottom dielectric layer, and second bottom dielectric layer (Figs. 16/17, ILD layer, 250 covering the semiconductor device structure including bottom oxide feature, 234, [0040]).
Regarding Claim 10, ZHANG in combination with SU as modified by CHANG teaches the semiconductor device structure of claim 1.
SU further teaches in Figure 8B, the semiconductor device structure (100), wherein the first (802) and second (804) dielectric layers have a first thickness (5 nm to about 30 nm, [0040]), and each of the first (106) and second (108) semiconductor layers has a second thickness (6 nm to 12 nm for 106 and 2 nm to 6 nm for 108, [0025]) less than the first thickness ([0025], [0040]).
Regarding Claim 11, ZHANG in combination with SU as modified by CHANG teaches the semiconductor device structure of claim 1.
CHANG teaches in Figures 16/17, the semiconductor device structure (200, workpiece), comprising:
an interlayer dielectric (ILD) layer (250) disposed over the first and second epitaxial S/D features (244/246) ; and
a contact etch stop layer (CESL) (248) disposed between and in contact with the ILD and the first and second epitaxial S/D features.
Regarding Claim 12, ZHANG in combination with SU as modified by CHANG teaches the semiconductor device structure of claim 11.
CHANG teaches in Figures 16/17, the semiconductor device structure (200, workpiece), wherein the CESL (Figs. 16/17, 248) comprises a material chemically different than that of the first and second bottom dielectric layers (in some embodiments, the bottom dielectric features consists essentially of silicon germanium oxide, [0069]).
Claim(s) 13-14, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of SU, further in view of CHANG and further in view Yu-San Chien et al, (hereinafter CHIEN), US 20210391327 A1.
Regarding Claim 13, ZHANG teaches, a semiconductor device structure (Fig. 1, 10, a semiconductor device, [0008]), comprising:
a dielectric wall (Fig. 1, 13, insulator pillar) disposed between a first fin structure (Fig. 1, 11, nFET) and a second fin structure (Fig. 1, 12, pFET);
a first source/drain (S/D) feature (Fig. 15, 1320, nFET epitaxy) disposed adjacent a first sidewall (annotated Figure 15) of the dielectric wall (Fig. 15, 120, insulator pillar);
a second S/D feature (Fig. 15, 1310, pFET epitaxy) disposed adjacent a second sidewall (annotated Figure 15) of the dielectric wall (Fig. 15, 120, insulator pillar);
a plurality of first semiconductor layers (Fig. 5, 105, SiGe30 layers) vertically stacked (annotated Figure 5) and extended outwardly (annotated Figure 5) from the first sidewall (annotated Figure 5) of the dielectric wall (Fig. 5, 120, insulator pillar);
a plurality of second semiconductor layers (Fig. 5, 106, Si layers) vertically stacked (annotated Figure 5) and extended outwardly (annotated Figure 5) from a second sidewall (annotated Figure 5) of the dielectric wall (Fig. 5, 120, insulator pillar);
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a first gate electrode layer (Figs. 16/17, 1510, one or more gate structures) surrounding at least three surfaces (Figs. 16/17, the one or more gate structures, 1510, traverse the nFET section, 1321, the insulator pillar, 120 and the pFET section, 1311, [0046]) of at least one of the first semiconductor layers (Fig. 5, 105, SiGe30 layers / Figs. 16/17, 1503, nFET nanosheets), the first gate electrode layer (Figs. 16/17, 1510, gate structure) having a first conductivity type (Fig. 17, high-k metal gate elements of the nFET nanosheets, [0047]);
a second gate electrode layer (Figs. 16/17, 1510, one or more gate structure) surrounding at least three surfaces Figs. 16/17, the one or more gate structures, 1510, traverse the nFET section, 1321, the insulator pillar, 120 and the pFET section, 1311, [0046]) of at least one of the second semiconductor layers (Fig. 5, 106, Si layers / Figs. 16/17, 1504, pFET nanosheets), the second gate electrode layer having a second conductivity type opposite the first conductivity type (Fig. 17, high-k metal gate elements of the pFET nanosheets, [0047]);
Alternatively, SU teaches, a semiconductor device structure (Figs. 10A-10B, 100), comprising:
a dielectric wall (Figs. 17A-17B, 306, dielectric feature) disposed between a first fin structure and a second fin structure (Figs. 3D-3E/4, 202);
a first source/drain (S/D) feature (Fig. 10A, 902, S/D epitaxial layers) disposed adjacent a first sidewall (annotated Figure 10A) of the dielectric wall (Fig. 10A, 306, dielectric feature);
a second S/D feature (Fig. 10A, 902, S/D epitaxial layers) disposed adjacent a second sidewall (annotated Figure 10A) of the dielectric wall (Fig. 10A, 306, dielectric feature);
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a plurality of first semiconductor layers (Fig. 7B, 106) vertically stacked (Fig. 7B, Z-direction) and extended outwardly (Fig. 15H, Y-direction) from the first sidewall (Figs. 17A-17B, 1514, dielectric material) of the dielectric wall (Figs. 17A-17B, 306, dielectric feature);
a plurality of second semiconductor layers (Fig. 7B, 108; gate stack, 1206 is replaced for 108, [0044]) vertically stacked (Fig. 7B, Z-direction) and extended outwardly (Fig. 15H, Y-direction) from a second sidewall (Figs. 17A-17B, 1514, dielectric material) of the dielectric wall (Figs. 17A-17B, 306, dielectric feature);
a first gate electrode layer (Fig. 12C, 1206) surrounding at least three surfaces of at least one of the first semiconductor layers (Fig. 7B, 106), the first gate electrode layer having a first conductivity type (conductivity type (e.g. p-type or n-type conductivity), [0022]; gate electrode materials, [0047]; Si used for 106, [0044]);
a second gate electrode layer (Fig. 12C, 1206) surrounding at least three surfaces of at least one of the second semiconductor layers (Fig. 7B, 108; gate stack, 1206 is replaced for 108, [0044]), the second gate electrode layer having a second conductivity type opposite the first conductivity type (conductivity type (e.g. p-type or n-type conductivity), [0022]; gate electrode materials, [0047]; SiGe used for 108, [0044]);
The rationale behind using ZHANG and SU, both as primary reference is based on their combination of features presented that are complementary to support the rejection. The prior art of ZHANG, wherein etching of the unmasked sacrificial undoped epitaxy S/D regions, 710 results in the redefinition of the cavities, 510 (as shown in Figure 12), and the entire removal of the sacrificial undoped epitaxy, S/D regions, 710 at the unmasked side of insulator pillar, 120 (as shown in Figure 13), however the doped pFET epitaxy, S/D regions, 1310 is formed in the cavities of Figure 12 and at a first side of the insulator pillar, 120, and the nFET epitaxy, 1320 is formed at the second side of the insulator pillar, 120 as shown in Figure 15 (see paragraphs [0042-0044]), which are similar to the instant application. On the other hand, prior art of SU, though the second semiconductor layer, 108 shown in Figure 12A is subsequently removed, and gaps, 1203 are formed between the dielectric spacers, 804, as shown in Figure 12B. This allows the formation of gate stack structure 1204/1206 around the first semiconductor layer, 106 (see paragraphs, [0044-0045]), align with the dielectric wall, 306, and the spacers, 1514, of the structure as shown in Figures 17A-17B, and are similar to the instant application. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have combined ZHANG and SU, such that a semiconductor device structure comprising: a plurality of semiconductor layers vertically stacked and extended outwardly from a first sidewall of the dielectric wall, at least one of the plurality of semiconductor layers comprising a sidewall contiguous (ZHANG, Figures 17A-17B; SU, Figures 5/9).
ZHANG in combination with SU does not explicitly disclose, a semiconductor device structure comprising: a first bottom dielectric layer disposed between the first fin structure and the first S/D feature, the first bottom dielectric layer having a bottom surface contiguous with an upper surface of the first S/D feature; and a second bottom dielectric layer disposed between the second fin structure and the second S/D feature, the second bottom dielectric layer having a bottom surface contiguous with an upper surface of the second S/D feature.
CHANG teaches in Figure 29A/29B, a semiconductor device structure (200, workpiece) comprising: a first bottom dielectric layer (Fig. 29A, 2030, bottom oxide feature or dielectric feature, [0012]) disposed between the first fin structure (Fig. 29A, 204, stack, [0020]) and the first S/D feature (Figs. 29A/29B, 20, source/drain regions, 242/244, [0023]); and a second bottom dielectric layer (Figs. 29A, 2030, bottom oxide feature or dielectric feature, [0012]) disposed between the second fin structure (Fig. 29A, 204, stack, [0020]) and the second S/D feature (Figs. 29A/29B, 20, source/drain regions, 242/244, [0023]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention (AIA ) to have modified ZHANG in combination with SU to incorporate the teachings of CHANG, such that a semiconductor device structure comprising: a first bottom dielectric layer disposed between the first fin structure and the first S/D feature; and a second bottom dielectric layer disposed between the second fin structure and the second S/D feature. The advantage of having the bottom dielectric feature or bottom oxide feature, that enables to facilitate insulation of the channel region from the bulk substrate (CHANG, [0012]).
ZHANG in combination with SU as modified by CHANG does not explicitly disclose, a semiconductor device structure comprising: a first bottom dielectric layer disposed between the first fin structure and the first S/D feature, the first bottom dielectric layer having a bottom surface contiguous with an upper surface of the first S/D feature; and a second bottom dielectric layer disposed between the second fin structure and the second S/D feature, the second bottom dielectric layer having a bottom surface contiguous with an upper surface of the second S/D feature.
CHIEN teaches a semiconductor device structure (Fig. 1K, 100) comprising: a first bottom dielectric layer (Fig. 5C, 120, dielectric material) disposed between the first fin structure (Figs. 4/5C, 104, fins) and the first S/D feature (Figs. 4/5C, 128), the first bottom dielectric layer (Fig. 5C, 120, dielectric material) having a bottom surface contiguous with an upper surface (annotated Figure 5C) of the first S/D feature (Figs. 4/5C, 128); and a second bottom dielectric layer (Fig. 5C, 120, dielectric material) disposed between the second fin structure (Figs. 4/5C, 115/104, hybrid fins) and the second S/D feature (Figs. 4/5C, 128), the second bottom dielectric layer (Fig. 5C, 120, dielectric material) having a bottom surface contiguous with an upper surface (annotated Figure 5C) of the second S/D feature (Figs. 4/5C, 128).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention (AIA ) to have ZHANG in combination with SU as modified by CHANG to incorporate the teachings of CHIEN, such that a semiconductor device structure comprising: a first bottom dielectric layer disposed between the first fin structure and the first S/D feature, the first bottom dielectric layer having a bottom surface contiguous with an upper surface of the first S/D feature; and a second bottom dielectric layer disposed between the second fin structure and the second S/D feature, the second bottom dielectric layer having a bottom surface contiguous with an upper surface of the second S/D feature. The aforementioned arrangements of dielectric layer, fin structure and the position of S/D regions thus continues to improve the integration density of various electronic components (CHIEN, [0002]).
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Regarding Claim 14, ZHANG in combination with SU as modified by CHANG and CHIEN teaches the semiconductor device structure of claim 13.
CHANG further teaches in Figure 28A, the semiconductor device structure (200, workpiece), wherein the first bottom dielectric layer and the second bottom dielectric layer (Fig. 28A, 2030, bottom oxide feature or dielectric feature, [0012]) are separated by the first fin structure (Fig. 3, 210 or Fig. 28A above, 204, stack, [0020]).
Regarding Claim 16, ZHANG in combination with SU as modified by CHANG and CHIEN teaches the semiconductor device structure of claim 15.
CHANG further teaches in Figure 28A, the semiconductor device structure (200, workpiece), wherein the first bottom dielectric layer and the second bottom dielectric layers (Fig. 28A, 2030, bottom oxide feature or dielectric feature, [0012]) are in contact with the dielectric wall (Fig. 3, filling the trenches 211 with the dielectric material in between fin-shaped structures, 210, [0021]; Fig. 29A, epitaxial features, 244/242 (potentially replaced with dielectric material of Fig. 3) to serve as contact feature between first and second bottom dielectric layers, 2030; it should also be noted that substituting (dielectric materials) for (epitaxial materials) is a simple substitution of one known element for another to obtain predictable results [See MPEP2143]; According to CHANG, [0069] in some embodiments, the bottom dielectric feature consists essentially of silicon germanium oxide.).
Regarding Claim 17, ZHANG in combination with SU as modified by CHANG and CHIEN teaches the semiconductor device structure of claim 13.
SU further teaches in Figures 15H/16A, the semiconductor device structure (100) of claim 13, wherein first bottom dielectric layer (Figs. 15H/16A, 1522) is separated from the first S/D feature (Fig. 15H, 902, S/D epitaxial layer) by a first air gap (Fig. 16A, 1602, [0063]).
Regarding Claim 18, ZHANG in combination with SU as modified by CHANG and CHIEN teaches the semiconductor device structure of claim 17.
SU further teaches in Figures 15H/16A, the semiconductor device structure (100) of claim 17, wherein second bottom dielectric layer (Figs. 15H/16A, 1522) is separated from the second S/D feature (Fig. 15H, 902, S/D epitaxial layer) by a second air gap (Fig. 16A, 1602, [0063]).
Regarding Claim 19, ZHANG teaches a method for forming a semiconductor device structure (Fig. 18, method of fabricating a semiconductor device, [0048]), comprising:
Forming (Fig. 18, 1801) a first fin structure (Fig. 1, 11, nFET/ Fig. 15, 1321) and a second fin structure (Fig. 1, 12, pFET/ Fig. 15, 1311) from a substrate (Fig. 2, 102), wherein the first fin structure (Fig. 1, 11, nFET/ Fig. 15, 1321) includes a first plurality of semiconductor layers (Fig. 17, 1503, nFET nanosheets) over a first sacrificial layer (Fig. 5, 105, SiGe30 layers), and the second fin structure (Fig. 1, 12, pFET/ Fig. 15, 1311) includes a second plurality of semiconductor layers (Fig. 17, 1504, pFET nanosheets) over a second sacrificial layer (Fig. 5, 106, Si layers), and wherein at least one of the first plurality of semiconductor layers (Fig. 17, 1503, nFET nanosheets) and at least one of the second plurality of semiconductor layers (Fig. 17, 1504, pFET nanosheets) comprises first semiconductor layers (Fig. 5, 105, SiGe30 layers) and second semiconductor layers (Fig. 5, 106, Si layers);
forming (Fig. 18, 1801) a dielectric wall (Fig. 5, 120, insulator pillar) between the first fin structure (Fig. 1, 11, nFET/ Fig. 15, 1321) and the second fin structure (Fig. 1, 12, pFET/ Fig. 15, 1311);
forming (Fig. 18, 1806) an insulating material (Fig. 4, 320, spacers) between the second fin structure (Fig. 1, 12, pFET/ Fig. 15, 1311) and a third fin structure (Fig. 1, 11, nFET/ Fig. 15, 1321 or plurality of fin structures Figure 16) adjacent the second fin structure (Fig. 1, 12, pFET/ Fig. 15, 1311);
forming a sacrificial gate stack (Fig. 14, 310, dummy gates) over the first fin structure (Fig. 1, 11, nFET/ Fig. 15, 1321) and the second fin structure (Fig. 1, 12, pFET/ Fig. 15, 1311);
selectively removing (Fig. 18, 1804) the first and second sacrificial layers to form an opening (Fig. 12, 510, cavities);
filling the opening with a bottom dielectric material (Fig. 14, 1310, pFET epitaxy);
forming (Fig. 18, 1805) a source/drain feature (Fig. 15, 1310/1320, pFET epitaxy/nFET epitaxy) over the bottom dielectric material (Fig. 15, 320, spacers);
forming an interfacial layer (IL) (Fig. 18, 1806) to surround (Fig. 16, 1520, ILD) at least three surfaces (Fig. 17) of the first semiconductor layers (Fig. 17, 1503, nFET nanosheets) of the first (Fig. 15, 1321, nFET) and second fin structures (Fig. 15, 1311, pFET);
forming (Fig. 18, 1808) a gate electrode layer (Figs. 16/17, 1510, one or more gate structures) over the IL (Fig. 16, 1520, ILD).
Alternatively, SU teaches a method for forming a semiconductor device structure (Figs. 1-17B, 100, [0019]), comprising:
forming a first fin structure (Figs. 3D-3E/4, 202) and a second fin structure (Figs. 3D-3E/4, 202) from a substrate (Fig. 2, 101), wherein the first fin structure (Figs. 3D-3E/4, 202) includes a first plurality of semiconductor layers (Fig. 7B, 106) over a first sacrificial layer ([0028]), and the second fin structure (Figs. 3D-3E/4, 202) includes a second plurality of semiconductor layers (Fig. 7B, 108; gate stack, 1206 is replaced for 108, [0044]) over a second sacrificial layer ([0028]), and wherein at least one of the first plurality of semiconductor layers (Fig. 7B, 106) over and at least one of the second plurality of semiconductor layers (Fig. 7B, 108; gate stack, 1206 is replaced for 108, [0044]) comprises first semiconductor layers (Fig. 7B, 106) and second semiconductor layers (Fig. 7B, 108; gate stack, 1206 is replaced for 108, [0044]);
forming a dielectric wall (Figs. 17A-17B, 306, dielectric feature) between the first fin structure (Figs. 3D-3E/4, 202) and the second fin structure (Figs. 3D-3E/4, 202);
forming an insulating material (Figs. 3A-3E, 302) between the second fin structure (Figs. 3D-3E/4, 202) and a third fin structure (plurality of fin structures) adjacent the second fin structure (Figs. 3D-3E/4, 202);
forming a sacrificial gate stack (Fig. 5B, (502, 504, 506), [0035]) over the first fin structure (Figs. 3D-3E/4, 202) and the second fin structure (Figs. 3D-3E/4, 202);
selectively removing the first and second sacrificial layers to form an opening (removal of sacrificial layer, [0028], formation of opening, [0055]);
filling the opening with a bottom dielectric material ([0056]);
forming a source/drain feature over the bottom dielectric material ([0040]),
selectively removing the second semiconductor layers of the first and second plurality of semiconductor layers ([0039], [0044]);
forming an interfacial layer (IL) to surround at least three surfaces of the first semiconductor layers of the first and second fin structures and exposed surfaces of the bottom dielectric material (Fig. 12C, 1204 includes an IL formed between 106 and dielectric material (like dielectric feature [0032]), [0045]); and
forming a gate electrode layer (Fig. 12C, 1206) over the IL (Fig. 12C, 1204).
The rationale behind using ZHANG and SU, both as primary reference is based on their combination of features presented that are complementary to support the rejection. The prior art of ZHANG, wherein etching of the unmasked sacrificial undoped epitaxy S/D regions, 710 results in the redefinition of the cavities, 510 (as shown in Figure 12), and the entire removal of the sacrificial undoped epitaxy, S/D regions, 710 at the unmasked side of insulator pillar, 120 (as shown in Figure 13), however the doped pFET epitaxy, S/D regions, 1310 is formed in the cavities of Figure 12 and at a first side of the insulator pillar, 120, and the nFET epitaxy, 1320 is formed at the second side of the insulator pillar, 120 as shown in Figure 15 (see paragraphs [0042-0044]), which are similar to the instant application. On the other hand, prior art of SU, though the second semiconductor layer, 108 shown in Figure 12A is subsequently removed, and gaps, 1203 are formed between the dielectric spacers, 804, as shown in Figure 12B. This allows the formation of gate stack structure 1204/1206 around the first semiconductor layer, 106 (see paragraphs, [0044-0045]), align with the dielectric wall, 306, and the spacers, 1514, of the structure as shown in Figures 17A-17B, and are similar to the instant application. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have combined ZHANG and SU, such that a semiconductor device structure comprising: a plurality of semiconductor layers vertically stacked and extended outwardly from a first sidewall of the dielectric wall, at least one of the plurality of semiconductor layers comprising a sidewall contiguous (ZHANG, Figures 17A-17B; SU, Figures 5/9).
SU though teaches the bottom dielectric material, 1514 of Fig. 17A, but ZHANG in combination with SU does not explicitly disclose a method for forming a semiconductor device structure comprising: forming an interfacial layer (IL) to surround at least three surfaces of the first semiconductor layers of the first and second fin structures and exposed surfaces of the bottom dielectric material.
CHANG teaches in Figure 16, a method for forming a semiconductor device structure (200, workpiece) comprising: forming an interfacial layer (IL) (252/254 includes an interfacial layer, 250, ILD layer, [0040]) to surround at least three surfaces of the first semiconductor layers (208, channel members) of the first and second fin structures (260/262, type MBC transistors) and exposed surfaces of the bottom dielectric material (Figs. 16, 234, bottom dielectric feature, [0042]/Fig. 28A, 2030, bottom oxide feature or dielectric feature, [0012])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention (AIA ) to have modified ZHANG in combination with SU to incorporate the teachings of CHANG, such that a method for forming a semiconductor device structure comprising: forming an interfacial layer (IL) to surround at least three surfaces of the first semiconductor layers of the first and second fin structures and exposed surfaces of the bottom dielectric material, so that the interfacial layers facilitate as protecting layers with high-K gate dielectric layer features for efficient operation of the semiconductor device structure (CHANG, [0040], [0063]).
ZHANG in combination with SU as modified by CHANG does not explicitly disclose, a semiconductor device structure comprising: a first bottom dielectric layer disposed between the first fin structure and the first S/D feature, the first bottom dielectric layer having a bottom surface contiguous with an upper surface of the first S/D feature; and a second bottom dielectric layer disposed between the second fin structure and the second S/D feature, the second bottom dielectric layer having a bottom surface contiguous with an upper surface of the second S/D feature.
CHIEN teaches a semiconductor device structure (Fig. 1K, 100) comprising: a first bottom dielectric layer (Fig. 5C, 120, dielectric material) disposed between the first fin structure (Figs. 4/5C, 104, fins) and the first S/D feature (Figs. 4/5C, 128), the first bottom dielectric layer (Fig. 5C, 120, dielectric material) having a bottom surface contiguous with an upper surface (annotated Figure 5C) of the first S/D feature (Figs. 4/5C, 128); and a second bottom dielectric layer (Fig. 5C, 120, dielectric material) disposed between the second fin structure (Figs. 4/5C, 115/104, hybrid fins) and the second S/D feature (Figs. 4/5C, 128), the second bottom dielectric layer (Fig. 5C, 120, dielectric material) having a bottom surface contiguous with an upper surface (annotated Figure 5C) of the second S/D feature (Figs. 4/5C, 128).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention (AIA ) to have modified ZHANG in combination with SU as modified by CHANG to incorporate the teachings of CHIEN, such that a semiconductor device structure comprising: a first bottom dielectric layer disposed between the first fin structure and the first S/D feature, the first bottom dielectric layer having a bottom surface contiguous with an upper surface of the first S/D feature; and a second bottom dielectric layer disposed between the second fin structure and the second S/D feature, the second bottom dielectric layer having a bottom surface contiguous with an upper surface of the second S/D feature. The aforementioned arrangements of dielectric layer, fin structure and the position of S/D regions thus continues to improve the integration density of various electronic components (CHIEN, [0002]).
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Regarding Claim 20, ZHANG in combination with SU, as modified by CHANG and CHIEN teaches the method of claim 19.
SU further teaches, the method (Figs. 1-17B, 100, [0019]), comprising:
forming a second source/drain feature (Figs. 15H/17B, 902, S/D epitaxial layer) over the bottom dielectric material (Figs/ 17A/17B, 1514);
wherein the second source/drain (Fig. 15H, 902, S/D epitaxial layer) is deposited so that an air gap (Fig. 16A, 1602) is defined between a bottom surface of the second source/drain feature (Fig. 15H, 902, S/D epitaxial layer) and an upper surface of the bottom dielectric material (Figs. 15H/16A, 1522/802).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of SU, further in view of CHANG, and further in view of I-Sheng Chen et al, (hereinafter CHEN), US 9660033 B1.
Regarding Claim 15, ZHANG in combination with SU, as modified by CHANG and CHIEN teaches the semiconductor device structure of claim 13.
CHANG further teaches in Figure 28A, the semiconductor device structure (200, workpiece), wherein the first bottom dielectric layer and the second bottom dielectric layer (Fig. 28A, 2030, bottom oxide feature or dielectric feature, [0012]) are connected (Fig. 21A, 203, the bottom sacrificial feature is oxidized to transform into bottom oxide feature, 2030, [0055]).
Though CHANG teaches the semiconductor device structure where in the first bottom dielectric layer and the second bottom dielectric layer are connected via the bottom sacrificial feature, 203, ZHANG in combination with SU, as modified by CHANG and CHIEN does not explicitly disclose the semiconductor device structure, wherein the first bottom dielectric layer and the second bottom dielectric layer are connected.
CHEN teaches in Figure 2D, the semiconductor device structure (200, device), wherein the first bottom dielectric layer and the second bottom dielectric layer (annotated Figure 2D below, 204, strain relaxed buffer (SRB) layer, [Col. 3, Lines 50-55) are connected (annotated Figure 2D below).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention (AIA ) to have ZHANG in combination with SU, as modified by CHANG and CHIEN to incorporate the teachings of CHEN, such that the semiconductor device structure, wherein the first bottom dielectric layer and the second bottom dielectric layer are connected, so that the SRB layer, 204 interposes the isolation features, 210, similar to the bottom dielectric feature or bottom oxide feature, of CHANG, [0012] that enables to facilitate insulation of the channel region from the bulk substrate (CHEN, Fig. 2D, [Col. 5, Lines 45-50]).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 9660033 B1 – Figure 15
STATEMENT OF RELEVANCE – Perspective view of a portion of a semiconductor device with fin structures, wherein the semiconductor layers are extended outwards.
US 20210358911 A1 – Figures 20A-20B
STATEMENT OF RELEVANCE – Flow diagram illustrating a method of forming pFET, nFET sections and an insulator pillar.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812
/CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812