DETAILED ACTION
This Office action responds to the Amendment file on March 3, 2026, responding to the Office action mailed on December 28, 2025, has been entered. The present Office action is made with all the suggested amendments being fully considered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant’s arguments with respect to the claims filed on March 3, 2026 have been considered, but are moot in view of the new grounds of rejections.
Applicant argues the protection layer 212 of on top of the top electrode cannot be used to protect the top electrode during manufacturing process of the prior of record, Cheng et al. (US 10,636,842) as shown in the FIGs. 5-7 of the present application. Cheng et al. uses a patterned photoresist layer 211 during etching process, but removed and not became a part of the overall stacked structure. However, Chiu et al. (US 2020/0365655) has patterned hard mask layer 170 being used during etching process and becoming a part of the overall stacked structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 4-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (Cheng hereinafter) (US 10,636,842) and in view of Chiu et al. (Chiu hereinafter) (US 2020/0365655).
Regarding Claims 1, 2, and 4-20:
Cheng (see FIG. 1B-, 1E, 1F-2, 1G, 1I, and 2G) teaches
{1} A resistive memory device 20, comprising: a dielectric layer 101; a first via connection structure 102 disposed in the dielectric layer; a first stacked structure disposed on the first via connection structure and the dielectric layer; a first insulating structure 220 penetrating through a portion of the first stacked structure in a vertical direction and dividing the first stacked structure into a first memory cell unit 218 and a second memory cell unit 218, wherein the first memory cell unit and the second memory cell unit comprise a first shared bottom electrode 200, and the first insulating structure is disposed directly on the first shared bottom electrode; and a spacer structure 212 disposed on a sidewall of the first stacked structure, and wherein the first insulating structure is directly connected with the spacer structure, and the first stack structure comprises: an electrically conductive layer 210 disposed above the first shared bottom electrode in the vertical direction; a variable resistance material 202 disposed between the first shared bottom electrode and the electrically conductive layer in the vertical direction; and, wherein the spacer structure is silicon nitride or silicon carbonitride;
{2} the first memory cell unit and the second memory cell unit are respectively located at two opposite sides of the first insulating structure in a first horizontal direction, and the spacer structure is directly connected with two opposite sidewalls of the first insulating structure in a second horizontal direction perpendicular to the first horizontal direction;
{4} the spacer structure is devoid of being disposed on a top surface of the electrically conductive layer;
{5} the first insulating structure penetrates through the electrically conductive layer and the variable resistance material in the vertical direction;
{6} the first memory cell unit further comprises a first top electrode 210A and a first variable resistance layer 202'/202" disposed between the first shared bottom electrode and the first top electrode in the vertical direction, and the second memory cell unit further comprises a second top electrode 210A and a second variable resistance layer 202'/202" disposed between the first shared bottom electrode and the second top electrode in the vertical direction;
{7} the first variable resistance layer is a first portion of the variable resistance material, and the second variable resistance layer is a second portion of the variable resistance material separated from the first portion of the variable resistance material by the first insulating structure;
{8} the first top electrode is a first portion of the electrically conductive layer, and the second top electrode is a second portion of the electrically conductive layer separated from the first portion of the electrically conductive layer by the first insulating structure;
{9} the first insulating structure is directly connected with the first variable resistance layer, the second variable resistance layer, the first top electrode, and the second top electrode;
{10} a seam in the first insulating structure;
{11} the spacer structure surrounds the first stacked structure in a direction perpendicular to the vertical direction;
{12} the spacer structure comprises two portions separated from each other by the first insulating structure;
{14} a second via connection structure 102 disposed in the dielectric layer; a second stacked structure disposed on the second via connection structure and the dielectric layer, wherein the second stacked structure is separated from the first stacked structure; and a second insulating structure 220 penetrating through a portion of the second stacked structure in the vertical direction and dividing the second stacked structure into a third memory cell unit 218 and a fourth memory cell unit 218, wherein the third memory cell unit and the fourth memory cell unit comprise a second shared bottom electrode 200', and the second insulating structure is disposed directly on the second shared bottom electrode;
{15} the first insulating structure and the second insulating structure extend in a horizontal direction respectively, and the first insulating structure and the second insulating structure are disposed adjacent to each other in the horizontal direction;
{16} the first insulating structure and the second insulating structure are separated from each other;
{17} the first insulating structure and the second insulating structure are different portions of an insulating structure extending in the horizontal direction;
{18} the first shared bottom electrode and the second shared bottom electrode are separated from each other; and
{19} an air gap exists within the seam.
Cheng (see col.4/ll.41-66, col.5/ll.4-6, col.6/ll.15-63, col.8//ll.36-41) teaches “a protection layer 212 is formed conformally along sidewalls of the stack structures and the top surface of the stack structures, and the first isolation structure 214 are formed between each of the stack structures … the planarization process may be performed until the top surfaces of the stack structures are exposed (that is, the top surface of the patterned top electrode layer 210' … are level with the insulating material (not shown) … may include metal oxide, such as aluminum oxide (Al2O3) or silicon nitride (SiN4)”; “the first isolation structure 214 may be or include insulating material, such as oxide (such as silicon oxide), nitride, or a combination thereof”; “the second isolation structure 220 may include or be insulating materials, such as oxide (e.g., silicon oxide), nitride, or a combination of … … the second isolation structure 220 and the inter-metal dielectric layer 300 may be formed in the same deposition process … the recesses 216 may not be filled with the insulating material, or only partially filled with insulating material, to form the second isolation structure 220’ with air gap”; and “the protection layer 212 only formed along the sidewalls of …, not on the top surface of the second barrier structure 208" (not shown)”.
However, Cheng does not explicitly teach {1} a capping layer disposed on the electrically conductive layer, wherein the first insulating structure penetrates through a portion of the capping layer, and the capping layer is directly connected to the first insulating structure and the spacer structure and the capping layer is oxide insulation material; {13} a length of the first insulating structure in a horizontal direction is greater than a length of the first stacked structure in the horizontal direction; {17} the first insulating structure and the second insulating structure are directly connected with each other; and {20} the first insulating structure comprises two opposite sidewalls extending to protrude an edge of the spacer structure.
Chiu (see FIGs. 5-8 and 10B) teaches a memory device comprising a shared bottom electrode 134/132 and memory stack comprising a resistive switching elements 142, a capping layer 152, a top electrode 162, and a hard mask 172 and (see ¶ [0017], ¶ [0023], ¶ [0029], ¶ [0033]) teaches “The hard mask layer 170 is deposited on the top electrode layer … may include an oxygen containing hard mask layer, such as silicon-oxide (SiO2) or silicon-oxynitride (SiON) … substantially devoid of oxygen, such as silicon-nitride (SiN), silicon-carbide (SiC), or a composite dielectric … carbon-doped silicon nitride may be used”; “the spacer layer 180 may be made of silicon nitride, silicon carbide, or silicon carbon nitride”; “a film layer 190 is conformally formed over memory region MR and the peripheral region PR … covers the memory cells MC1 and MC2, the spacers 180', and the memory stop layer 120”; “the spacer 180' continuously surrounding the stacks S1 and S2 or the stacks S3 and S4”
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Cheng to further include the teaching of Chiu to keep the hard mask layer above the top electrode of the memory stack as a part of the memory stack, to select either the same or different material for the spacer and top capping layers, and to integrally interconnect all the isolation structures together beyond the boundaries of memory cell with sidewall spacers to meet the design and/or manufacturing requirements.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (Cheng hereinafter) (US 10,636,842) and in view of Chiu et al. (Chiu hereinafter) (US 2020/0365655) as applied to claim 1 above, and further in view of Tsai et al. (Tsai hereinafter) (US 2020/0136039).
Regarding Claim 3:
Cheng in the device of Chiu teaches all aspect of the instant invention, but does not explicitly teach a bottom surface of the first insulating structure is lower than a top surface of the first shared bottom electrode in the vertical direction and higher than a top surface of the first via connection structure in the vertical direction.
However, Tsai (see ¶ [0026] and Fig. 4) teaches a RRAM structure and “the last etching sub-operation can over etch the exposed conductive structure 220 to ensure that the conductive structure 220 is exposed and dielectric 230 has been removed from the bottom of opening 400.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Cheng in the device of Chiu to include the teaching of Tsai to allow the shared bottom electrode 310b slightly etched to ensure it is exposed before next manufacturing step.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Prosecution Insights