DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16, 18-20, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (“Xie”), US 2021/0296184, in view of Mertens et al. (“Mertens”), US 2023/0420544.
Regarding Claim 16, Xie discloses a semiconductor structure (abstract, claim 16, and left side of figure 5), comprising:
a first FET device (bottom stack layers 22 and 24; Fig. 5; ¶ 0045-49) comprising a first source/drain region (50; Fig. 6; ¶ 0052 “50 can be a first source/drain region”);
a second FET device (top stack of layers 22 and 24; Fig. 5; ¶ 0045-0049) disposed over the first FET device in a vertical direction (Fig. 5), wherein the second FET device comprises a second source/drain region (54; Fig. 6; ¶ 0052 “54 can be a second source/drain region”);
a middle dielectric layer disposed between the first FET device and the second FET device (spacer 34; Figs. 4-5; ¶ 0041 describes the dielectric spacer material as 32 between the two stacks, wherein 32 and 34 are the same spacer, this dielectric could also be an airgap see figure 2 and claim 16).
Xie does not disclose
a conductive contact disposed between the first and second source/drain regions;
a plurality of first inner spacers of the first FET device; and
a plurality of second inner spacers of the second FET device, wherein the first inner spacers and the second inner spacers are formed independently from each other,
and the first inner spacers and the second inner spacers comprise different materials.
Mertens discloses
a conductive contact (180; Figs. 12-13; ¶ 0101 “contacts 180”) disposed between (Figs. 12-13) the first (150; Fig. 7; ¶ 0089 “bottom source/drain bodies 150”) and second (160; Fig. 7; ¶ 0089 “top source/drain bodies 160”) source/drain regions;
a plurality of first inner spacers (144a; Fig. 2B; ¶ 0075) of the first FET device; and
a plurality of second inner spacers (144a; Fig. 2B; ¶ 0075) of the second FET device, wherein the first inner spacers and the second inner spacers are formed independently (in this instance the second inner spacers are spaced apart from the first inner spacers) from each other (“The patentability of a product does not depend on its method of production.”, In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)), and the first inner spacers and the second inner spacers comprise different materials (¶ 0075 “oxide, nitride or carbide” in this instance the first inner spacer is oxide and the second inner spacer is nitride).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Xie to have a conductive contact disposed between the first and second source/drain regions; a plurality of first inner spacers of the first FET device; and a plurality of second inner spacers of the second FET device, wherein the first inner spacers and the second inner spacers are formed independently from each other, as taught by Mertens, because they facilitate “an efficient process flow” during manufacturing (Mertens ¶ 0079), thereby reducing the overall manufacturing cost of the semiconductor structure. Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Xie to have the first inner spacers and the second inner spacers comprise different materials, as taught by Mertens, in order to customize the performance of the first and second FET devices, thereby optimizing the performance of the semiconductor structure.
Regarding Claim 18, Xie does not disclose wherein the first inner spacers have dimensions different from dimensions of the second inner spacers.
Mertens discloses the first inner spacers have dimensions different from dimensions of the second inner spacers (¶ 0078 a cover spacer 145 is “deposited after the first sub-step” and it will “cover the inner spacers 144b. The second sub-step of the recessing may then be performed” therefore the dimensions of the second inner spacers 144a formed (¶ 0075) after the second recessing sub-step are different; furthermore in this instance the thickness of the bottom sacrificial layer 112 is 10 nm (¶ 0066 “a thickness in a range from 3 nm to 10 nm”) and the thickness of the top sacrificial layer 132 is 3 nm (¶ 0066) therefore the dimensions (in this instance thickness) of the second inner spacer 144a is different than the top inner spacer 144b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Xie to have the first inner spacers having dimensions different from dimensions of the second inner spacers, as taught by Mertens, in order to customize the performance of the first and second FET devices, thereby optimizing the performance of the semiconductor structure.
Regarding Claim 19, Xie discloses wherein the first FET device has a conductive type different from a conductive type of the second FET device (¶ 0022).
Regarding Claim 20, Xie does not disclose wherein one of the second inner spacers includes a first outer surface, one of the first inner spacers includes a second outer surface, wherein the first and second outer surfaces are misaligned.
Mertens discloses one of the second inner spacers includes a first outer surface (Fig. 2B in this instance the outer surface of a second inner spacer 144b that is in direct contact with the sacrificial layer 132), one of the first inner spacers includes a second outer surface (Fig. 2B in this instance the outer surface of a first inner spacer 144a that is in direct contact with bottom source/drain bodies 150), wherein the first and second outer surfaces are misaligned (in this instance misaligned in the vertical and horizontal directions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Xie to have one of the second inner spacers include a first outer surface, one of the first inner spacers include a second outer surface, wherein the first and second outer surfaces are misaligned, as taught by Mertens, in order to customize the performance of the first and second FET devices, thereby optimizing the performance of the semiconductor structure.
Regarding Claim 24, Xie does not disclose wherein the conductive contact is disposed adjacent the middle dielectric layer.
Mertens discloses wherein the conductive contact is disposed adjacent the middle dielectric layer (Figs. 11-13 and ¶ 0099-0101 layer 154 is replaced with contact 180, Figs 2B, 4 and ¶ 0085 “The etch back process may more specifically be stopped at a level between the top and bottom sub-stacks, e.g., coinciding with a level of the middle insulating layer 120.”, therefore conductive contact 180 is disposed adjacent the middle dielectric layer 120).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Xie to have wherein the conductive contact is disposed adjacent the middle dielectric layer, as taught by Mertens, in order to prevent short circuits, thereby improving the performance and reliability of the semiconductor structure.
Allowable Subject Matter
Claims 1-2, 6, 8, and 21-23 are allowed.
Regarding Claim 1, the prior art does not disclose forming first conductive contacts electrically connected to corresponding first source/drain regions before forming the second source/drain regions, wherein the first conductive contacts are disposed between the first source/drain regions and the second source/drain regions and in the combination as claimed.
Claims 2, 6, 8, and 21-23 are allowable for depending on Claim 1.
Claims 9-11 and 15 are allowed.
Regarding Claim 9, the prior art does not disclose forming first source/drain regions electrically connected to the plurality of second semiconductor layers; forming first conductive layers over the first source/drain regions; forming second source/drain regions electrically connected to the plurality of fourth semiconductor layers after forming the first conductive layers; and forming second conductive layers over the second source/drain regions and in the combination as claimed.
Claims 10-11 and 15 are allowable for depending on Claim 9.
Claims 25-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 25, the prior art does not teach or render obvious wherein the first FET device further comprises a first gate electrode disposed below the middle dielectric layer in combination as claimed with claims 24 and 16. Therefore, the combination of the features of Claims 16, 24, and 25 is considered allowable.
Claims 26-28 incorporate all of the limitations of allowable Claim 25. Therefore, they are also allowable.
Response to Arguments
In their amendment and response filed 3/2/2026, the applicant states (page 7) that “Claim 1 is amended to incorporate allowable claim 4, claim 9 is amended to incorporate allowable claim 12”. “Thus…claims 1, 9…should be allowable for at least the same reasons as claims 4 and 12.”
As explained supra, Claims 1-2, 6, 8-11, 15, and 21-23 are allowed.
The applicant states (page 7) that amended Claim 16 “and claims dependent thereon should be allowable”. The amendments to Claim 16 has necessitated an updated rejection of Claim 16 over the Xie and Mertens references, as discussed supra. Claim 16 and its dependent claims 18-20 and 24 are now rejected over the combination of Xie and Mertens. In addition, Claims 25-28 are objected to as depending on rejected Claims 16 and 24.
Independent Claim 16 is rejected for at least the reasons stated supra. Dependent Claims 18-20 and 24 are rejected for at least the reasons stated supra.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818