Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant's election, without traverse, of Species I, claims 14-18, in the “Response to Restriction Requirement” filed on 11/06/2025 is acknowledged and entered by the Examiner. Applicant's cancellation of claims 19-33, and addition of claims 34-48 in “Claims” filed on 11/06/2025 with the same reply, have been entered.
This office action considers claims 14-18 and 34-48 pending for prosecution.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 14-16, 18, and 34-48 are rejected under 35 U.S.C.103 as being unpatentable over Kuo et al (US 20200105711 A1; hereinafter Kuo), in view of Isa et al. (US 20060113671 A1; hereinafter Isa).
Regarding claim 14, Kuo teaches a manufacturing method of a semiconductor package (see the entire document, specifically Fig. 1+; [0015+], and as cited below), comprising:
forming an insulation body (104; Fig. 1; [0015]) on a carrier (100; Fig. 1; [0015]), wherein the insulation body (104; Fig. 1; [0015]) has a first insulation surface facing the carrier (100; Fig. 1; [0015]);
forming a first RDL structure (110; Fig. 3; [0021]) formed on the insulation body (104; Fig. 1; [0015]);
disposing a semiconductor component (114; Fig. 4A; [0025]) on the first RDL structure (110; Fig. 3; [0021]);
forming a package body (130; Fig. 5; [0029]) to surround the semiconductor component (114; Fig. 4A; [0025]), wherein the package body (130; Fig. 5; [0029]) has a first package surface disposed on the first RDL structure (110; Fig. 3; [0021]); and
forming a plurality of recessed portions (Fig. 25; [0070]) and (see below for “a plurality of voids on”) the insulation body (104; Fig. 25; [0070]) to form an insulation layer (104; Fig. 25; [0070]), wherein the recessed portions (Fig. 25; [0070]) are recessed with respect to a first insulation surface of the insulation body (104; Fig. 1; [0015]) and form a pattern, and (see below for “the voids are embedded in”) the insulation body (104; Fig. 1; [0070]).
As noted above, Kuo does not expressly disclose “forming a plurality of recessed portions and a plurality of voids on the insulation body to form an insulation layer, wherein the recessed portions are recessed with respect to a first insulation surface of the insulation body and form a pattern, and the voids are embedded in the insulation body”.
However, in the analogous art, Isa teaches a semiconductor device having an integrated circuit and a method for manufacturing the same ([0002]), wherein (Fig. 1A+; [0002+]) a porous insulating film (342; Fig. 4; [0085-0086]) is an insulating film with connection holes and wiring trenches and minute cavities isolated from each other and distributed in the porous insulating film (342; Fig. 4; [0085-0086]).
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to modify Kuo’s dielectric layer (104) with Isa’s porous insulating layer (342; Fig. 4; [0085-0086]) with cavities, and thereby, modified Kuo’s (by Isa) method will have forming a plurality of recessed portions (Kuo Fig. 25; [0070] in view of Isa Fig. 4; [0085-0086]) and a plurality of voids (in view of Isa Fig. 4; [0085-0086]; cavities in the porous insulating layer) on the insulation body (Kuo 104; Fig. 25; [0070] in view of Isa 342; Fig. 4; [0085-0086]) to form an insulation layer (Kuo 104; Fig. 25; [0070] in view of Isa 342; Fig. 4; [0085-0086]), wherein the recessed portions (Kuo Fig. 25; [0070]) are recessed with respect to a first insulation surface of the insulation body (Kuo 104; Fig. 25; [0070] in view of Isa 342; Fig. 4; [0085-0086]) and form a pattern, and the voids (in view of Isa Fig. 4; [0085-0086]; cavities in the porous insulating layer) are embedded in the insulation body (Kuo 104; Fig. 25; [0070] in view of Isa 342; Fig. 4; [0085-0086]).
The ordinary artisan would have been motivated to modify Kuo in the manner set forth above, at least, because this inclusion provides a porous insulating layer with cavities isolated from each other (Isa [0042, 0085-0086, 0094]), where the porous insulating film is used for the interlayer insulating film, thereby achieving lower dielectric constant and improvement in adhesion with a wiring material and a high performance semiconductor device capable of high speed operation can be obtained.
Regarding claim 15, modified Kuo (by Isa) teaches all of the features of claim 14.
Modified Kuo (by Isa) further teaches wherein the package body (130; Fig. 5; [0029]) has a second package surface opposite to the first package surface, the manufacturing method further comprises: forming a second RDL structure (160; Fig. 22; [0065]) on the second package surface of the package body (130; Fig. 22; [0029]).
Regarding claim 16, modified Kuo (by Isa) teaches all of the features of claim 15.
Modified Kuo (by Isa) further comprises:
forming a plurality of conductive vias (112; Fig. 3; [0022]) on the first RDL structure(110; Fig. 3; [0021]);
wherein in forming the package body (130; Fig. 5; [0029]) to surround the semiconductor component (114; Fig. 4A; [0025]), the package body (130; Fig. 5; [0029]) surrounds the conductive vias (112; Fig. 3; [0022]); and
in forming the second RDL structure (160; Fig. 22; [0065]) on the second package surface of the package body (130; Fig. 5; [0029]), the conductive vias (112; Fig. 3; [0022]) are connected to the second RDL structure (160; Fig. 22; [0065]).
Regarding claim 18, modified Kuo (by Isa) teaches all of the features of claim 14.
Modified Kuo (by Isa) further teaches further comprising: forming a conductive bump (106; Fig. 1; [0017]) on the insulation layer (104; Fig. 1; [0017]); and in forming the first RDL structure (110; Fig. 3; [0021]) formed on the insulation layer (104), the conductive bump (106; Fig. 1; [0017]) is formed between the insulation layer (104) and the first RDL structure (110; Fig. 1; [0021-0022]).
Regarding claim 34, Kuo teaches a manufacturing method of a semiconductor package (see the entire document, specifically Fig. 1+; [0015+], and as cited below), comprising:
forming an insulation body (104; Fig. 1; [0015]) on a carrier (100; Fig. 1; [0015]) through a release layer (102; Fig. 1; [0015]), wherein the insulation body 104; Fig. 1; [0015]) has a first insulation surface facing the carrier (100; Fig. 1; [0015]);
forming a first RDL structure (110; Fig. 3; [0021]) on the insulation body (104; Fig. 1; [0015]);
disposing a semiconductor component (114; Fig. 4A; [0025]) on the first RDL structure (110; Fig. 3; [0021]);
forming a package body (130; Fig. 5; [0029]) to surround the semiconductor component (114; Fig. 4A; [0025]), wherein the package body (130; Fig. 5; [0029]) has a first package surface disposed on the first RDL structure (110; Fig. 3; [0021]); and
forming a plurality of recessed portions (Fig. 25; [0070]) and (see below for “a plurality of voids on”) the insulation body (104; Fig. 25; [0070]) to form an insulation layer (104; Fig. 25; [0070]), wherein the recessed portions (Fig. 25; [0070]) are recessed with respect to a first insulation surface of the insulation body (104; Fig. 1; [0015]) and form a pattern, and (see below for “the voids are embedded in”) the insulation body (104; Fig. 1; [0070]).
As noted above, Kuo does not expressly disclose “forming a plurality of recessed portions and a plurality of voids on the insulation body to form an insulation layer, wherein the recessed portions are recessed with respect to a first insulation surface of the insulation body and form a pattern, and the voids are embedded in the insulation body”.
However, in the analogous art, Isa teaches a semiconductor device having an integrated circuit and a method for manufacturing the same ([0002]), wherein (Fig. 1A+; [0002+]) a porous insulating film (342; Fig. 4; [0085-0086]) is an insulating film with connection holes and wiring trenches and minute cavities isolated from each other and distributed in the porous insulating film (342; Fig. 4; [0085-0086]).
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to modify Kuo’s dielectric layer (104) with Isa’s porous insulating layer (342; Fig. 4; [0085-0086]) with cavities, and thereby, modified Kuo’s (by Isa) method will have forming a plurality of recessed portions (Kuo Fig. 25; [0070] in view of Isa Fig. 4; [0085-0086]) and a plurality of voids (in view of Isa Fig. 4; [0085-0086]; cavities in the porous insulating layer) on the insulation body (Kuo 104; Fig. 25; [0070] in view of Isa 342; Fig. 4; [0085-0086]) to form an insulation layer (Kuo 104; Fig. 25; [0070] in view of Isa 342; Fig. 4; [0085-0086]), wherein the recessed portions (Kuo Fig. 25; [0070]) are recessed with respect to a first insulation surface of the insulation body (Kuo 104; Fig. 25; [0070] in view of Isa 342; Fig. 4; [0085-0086]) and form a pattern, and the voids (in view of Isa Fig. 4; [0085-0086]; cavities in the porous insulating layer) are embedded in the insulation body (Kuo 104; Fig. 25; [0070] in view of Isa 342; Fig. 4; [0085-0086]).
The ordinary artisan would have been motivated to modify Kuo in the manner set forth above, at least, because this inclusion provides a porous insulating layer with cavities isolated from each other (Isa [0042, 0085-0086, 0094]), where the porous insulating film is used for the interlayer insulating film, thereby achieving lower dielectric constant and improvement in adhesion with a wiring material and a high performance semiconductor device capable of high speed operation can be obtained.
Regarding claim 35, modified Kuo (by Isa) teaches all of the features of claim 34.
Modified Kuo (by Isa) further teaches wherein the package body (130; Fig. 5; [0029]) has a second package surface opposite to the first package surface, the manufacturing method further comprises: forming a second RDL structure (160; Fig. 23; [0065]) on the second package surface of the package body (130; Fig. 22; [0029]); and after forming the second RDL structure (160; Fig. 23; [0065]), removing the release layer (102; Fig. 24; [0069]) to expose the first insulation surface (104; Fig. 24; [0069]).
Regarding claim 36, modified Kuo (by Isa) teaches all of the features of claim 34.
Modified Kuo (by Isa) further comprises: forming an insulation through-hole (Figs. 25-27; [0070-0091]) in the insulation layer (104; Figs. 25-27; [0070-0091]); forming a first conductor contact (514; Figs. 25-27; [0076-0091]) in the insulation through-hole, wherein the first conductor contact (514; Figs. 25-27; [0076-0091]) is electrically connected to the first RDL structure (110; Fig. 27]).
Regarding claim 37, modified Kuo (by Isa) teaches all of the features of claim 36.
Modified Kuo (by Isa) further teaches wherein in forming the first RDL structure (110; Fig. 3; [0021]) on the insulation body (104; Fig. 3; [0021]), the first RDL structure (110; Fig. 3; [0021]) comprises a first conductive trace layer (106; Fig. 3; [0017]) and a first dielectric layer (108; Fig. 3; [0020]); in forming an insulation through-hole (Figs. 25-27; [0070-0091]) in the insulation layer (104; Figs. 25-27; [0070-0091]), the insulation through-hole (Figs. 25-27; [0070-0091]) passes the first dielectric layer (108) to expose the first conductive trace layer (106); in forming the first conductor contact (514; Figs. 25-27; [0076-0091]) in the insulation through-hole, the first conductor contact (514; Figs. 25-27; [0076-0091]) is electrically connected to the first conductor contact (106) of the first RDL structure (110).
Regarding claim 38, modified Kuo (by Isa) teaches all of the features of claim 36.
Modified Kuo (by Isa) further teaches wherein in forming the first conductor (514; Figs. 25-27; [0076-0091]) contact in the insulation through-hole, the first conductor contact (514; Figs. 25-27; [0076-0091]) does not protrude relative to the first insulation surface (104; Figs. 25-27; [0070-0091]).
Regarding claim 39, modified Kuo (by Isa) teaches all of the features of claim 34.
Modified Kuo (by Isa) further comprising: removing a portion of the package body (130; Fig. 5; [0029]) to expose a terminal surface of each conductive via (112; Fig. 5; [0029]) and a terminal surface (126; Fig. 5; [0025]) of the semiconductor component (114; Fig. 5; [0029]).
Regarding claim 40, modified Kuo (by Isa) teaches all of the features of claim 39.
Modified Kuo (by Isa) further comprising: forming a second RDL structure (160; Figs. 21-23; [0057-0061, 0065-0067]) on the terminal surface of each conductive via (112; Fig. 5; [0029]) and the terminal surface (126; Fig. 5; [0025]) of the semiconductor component (114; Fig. 5; [0029]), wherein the second RDL structure (160; Figs. 21-23; [0065]) is electrically connected with each conductive via (112; Fig. 5; [0029]) and the semiconductor component (114; Fig. 5; [0029]).
Regarding claim 41, Kuo teaches a manufacturing method of a semiconductor package (see the entire document, specifically Fig. 1+; [0015+], and as cited below), comprising:
forming an insulation body (104; Fig. 1; [0015]) on a carrier (100; Fig. 1; [0015]), wherein the insulation body 104; Fig. 1; [0015]) has a first insulation surface facing the carrier (100; Fig. 1; [0015]);
forming a first RDL structure (110; Fig. 3; [0021]) on the insulation body (104; Fig. 1; [0015]);
disposing a semiconductor component (114; Fig. 4A; [0025]) on the first RDL structure (110; Fig. 3; [0021]);
forming a package body (130; Fig. 5; [0029]) to surround the semiconductor component (114; Fig. 4A; [0025]), wherein the package body (130; Fig. 5; [0029]) has a first package surface disposed on the first RDL structure (110; Fig. 3; [0021]); and
forming a plurality of recessed portions (Fig. 25; [0070]) and (see below for “a plurality of voids on”) the insulation body (104; Fig. 25; [0070]) to form an insulation layer (104; Fig. 25; [0070]), wherein the recessed portions (Fig. 25; [0070]) are recessed with respect to a first insulation surface of the insulation body (104; Fig. 1; [0015]) and form a pattern, and (see below for “the voids are embedded in”) the insulation body (104; Fig. 1; [0070]).
As noted above, Kuo does not expressly disclose “forming a plurality of recessed portions and a plurality of voids on the insulation body to form an insulation layer, wherein the recessed portions are recessed with respect to a first insulation surface of the insulation body and form a pattern, and the voids are embedded in the insulation body”.
However, in the analogous art, Isa teaches a semiconductor device having an integrated circuit and a method for manufacturing the same ([0002]), wherein (Fig. 1A+; [0002+]) a porous insulating film (342; Fig. 4; [0085-0086]) is an insulating film with connection holes and wiring trenches and minute cavities isolated from each other and distributed in the porous insulating film (342; Fig. 4; [0085-0086]).
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to modify Kuo’s dielectric layer (104) with Isa’s porous insulating layer (342; Fig. 4; [0085-0086]) with cavities, and thereby, modified Kuo’s (by Isa) method will have forming a plurality of recessed portions (Kuo Fig. 25; [0070] in view of Isa Fig. 4; [0085-0086]) and a plurality of voids (in view of Isa Fig. 4; [0085-0086]; cavities in the porous insulating layer) on the insulation body (Kuo 104; Fig. 25; [0070] in view of Isa 342; Fig. 4; [0085-0086]) to form an insulation layer (Kuo 104; Fig. 25; [0070] in view of Isa 342; Fig. 4; [0085-0086]), wherein the recessed portions (Kuo Fig. 25; [0070]) are recessed with respect to a first insulation surface of the insulation body (Kuo 104; Fig. 25; [0070] in view of Isa 342; Fig. 4; [0085-0086]) and form a pattern, and the voids (in view of Isa Fig. 4; [0085-0086]; cavities in the porous insulating layer) are embedded in the insulation body (Kuo 104; Fig. 25; [0070] in view of Isa 342; Fig. 4; [0085-0086]).
The ordinary artisan would have been motivated to modify Kuo in the manner set forth above, at least, because this inclusion provides a porous insulating layer with cavities isolated from each other (Isa [0042, 0085-0086, 0094]), where the porous insulating film is used for the interlayer insulating film, thereby achieving lower dielectric constant and improvement in adhesion with a wiring material and a high performance semiconductor device capable of high speed operation can be obtained.
Modified Kuo (by Isa) further teaches
wherein in forming the first RDL structure (110; Fig. 3; [0021]) on the insulation body (104; Fig. 1; [0015]), the first RDL structure (110; Fig. 3; [0021]) comprises a first conductive via layer (106; Fig. 1; [0017]);
the manufacturing method further comprising: forming a plurality of conductive vias (112; Fig. 3; [0022]) on the first conductive via layer (106; Fig. 1; [0017]) of the first RDL structure (110; Fig. 3; [0021]).
Regarding claim 42, modified Kuo (by Isa) teaches all of the features of claim 41.
Modified Kuo (by Isa) further teaches wherein in forming the package body (130; Fig. 5; [0029]) to surround the semiconductor component (114), the package body (130; Fig. 5; [0029]) covers the conductive vias (112) and the semiconductor component (114).
Regarding claim 43, modified Kuo (by Isa) teaches all of the features of claim 41.
Modified Kuo (by Isa) further comprising: removing a portion of the package body (130; Fig. 5; [0029]) to expose a terminal surface of each conductive via (112) and a terminal surface (126) of the semiconductor component (114).
Regarding claim 44, modified Kuo (by Isa) teaches all of the features of claim 43.
Modified Kuo (by Isa) further comprising: forming a second RDL structure (160; Figs. 20-25; [0057-0061, 0065-0067]) on the terminal surface of each conductive via (112; Fig. 5; [0029]) and the terminal surface (126; Fig. 5; [0025]) of the semiconductor component (114; Fig. 5; [0029]), wherein the second RDL structure (160; Figs. 21-23; [0065]) is electrically connected with each conductive via (112; Fig. 5; [0029]) and the semiconductor component (114; Fig. 5; [0029]).
Regarding claim 45, modified Kuo (by Isa) teaches all of the features of claim 41.
Modified Kuo (by Isa) further comprising: forming a second RDL structure (160; Figs. 20-25; [0057-0061, 0065-0067]) on the package body (130), wherein the second RDL structure (160; Figs. 20-25; [0057-0061, 0065-0067]) comprises a second dielectric layer (156; Figs. 20-25; [0030]) and a second conductive bump (162; Figs. 20-25; [0067]) protruding relative to a surface of the second dielectric layer (156; Figs. 20-25; [0030]).
Regarding claim 46, modified Kuo (by Isa) teaches all of the features of claim 45.
Modified Kuo (by Isa) further comprising: forming a second conductor contact (166; Figs. 20-25; [0067]) on the second conductive bump ({162}; Figs. 20-25; [0067]) of the second RDL structure (160; Figs. 20-25; [0067]).
Regarding claim 47, modified Kuo (by Isa) teaches all of the features of claim 41.
Modified Kuo (by Isa) further comprising: forming a second RDL structure (160; Figs. 20-25; [0057-0061, 0065-0067]) on the package body (130); and after forming the second RDL structure (160; Figs. 20-25; [0057-0061, 0065-0067]) on the package body (130), the insulation layer (104; Fig. 25; [0069]) is inverted to make the insulation body face up.
Regarding claim 48, modified Kuo (by Isa) teaches all of the features of claim 47.
Modified Kuo (by Isa) further comprising: forming an insulation through-hole (Figs. 25-27; [0070-0091]) in the insulation layer (104; Figs. 25-27; [0070-0091]); forming a first conductor contact (514; Figs. 25-27; [0076-0091]) in the insulation through-hole, wherein the first conductor contact (514; Figs. 25-27; [0076-0091]) is electrically connected to the first RDL structure (110; Fig. 27]).
3. Claim 17 is rejected under 35 U.S.C.103 as being unpatentable over Kuo et al (US 20200105711 A1; hereinafter Kuo), in view of Isa et al. (US 20060113671 A1; hereinafter Isa), in further view of Nikitin et al. (US 20090191665 A1; hereinafter Nikitin).
Regarding claim 17, modified Kuo (by Isa) teaches all of the features of claim 14.
Modified Kuo (by Isa) further teaches wherein the insulation layer (Kuo 104; Fig. 25; see [0070] in view of Isa 342; Fig. 4; see [0085-0086, 0087]) further comprises (see below for “a dye doped in”) the insulation body (Kuo 104; Fig. 25; see [0070] in view of Isa 342; Fig. 4; see [0085-0086, 0087]); in forming the plurality of recessed portions (Kuo Fig. 25; [0070]) and the plurality of voids (in view of Isa Fig. 4; [0085-0086]; cavities in the porous insulating layer) on the insulation body layer (Kuo 104; Fig. 25; see [0070] in view of Isa 342; Fig. 4; see [0085-0086, 0087]), the plurality of the recessed portions (Kuo Fig. 25; [0070]) and the plurality of the voids (in view of Isa Fig. 4; [0085-0086]; cavities in the porous insulating layer) fare formed (see below for “by a laser marking process of the dye absorbing the laser energy and then vaporizing layer”).
As noted above, modified Kuo (by Isa) does not expressly disclose “wherein the insulation layer further comprises a dye doped in the insulation body; in forming the plurality of recessed portions and the plurality of voids on the insulation body, the plurality of the recessed portions and the plurality of the voids fare formed by a laser marking process of the dye absorbing the laser energy and then vaporizing”.
However, in the analogous art, Nikitin teaches a semiconductor device and methods of manufacturing semiconductor devices ([0001]), wherein (Fig. 1A+; [0005+]) where insulating layer (108; Fig. 3B-3C; [0038, 0041]) is made of a polymer that contains particles, where a laser beam has interacted with insulating layer ([0041]) and the polymer molecules of insulating layer evaporate ([0041]).
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Nikitin’s laser beam irradiation step of the insulating with a polymer that contains particles into modified Kuo’s (by Isa) method, and thereby, modified Kuo’s (by Isa and Nikitin) method will have
wherein the insulation layer (Kuo 104; Fig. 25; see [0070] in view of Isa 342; Fig. 4; see [0085-0086, 0087] in view of Nikitin 108; Fig. 3B-3C; [0038, 0041]) further comprises a dye doped in the insulation body (Kuo 104; Fig. 25; see [0070] in view of Isa 342; Fig. 4; see [0085-0086, 0087] in view of Nikitin 108; Fig. 3B-3C; [0038, 0041]); in forming the plurality of recessed portions (Kuo Fig. 25; [0070]) and the plurality of voids (in view of Isa Fig. 4; [0085-0086]; cavities in the porous insulating layer in view of Nikitin 108; Fig. 3B-3C; [0038, 0041]) on the insulation body layer (Kuo 104; Fig. 25; see [0070] in view of Isa 342; Fig. 4; see [0085-0086, 0087] in view of Nikitin 108; Fig. 3B-3C; [0038, 0041]), the plurality of the recessed portions (Kuo Fig. 25; [0070]) and the plurality of the voids (in view of Isa Fig. 4; [0085-0086]; cavities in the porous insulating layer in view of Nikitin 108; Fig. 3B-3C; [0038, 0041]) fare formed by a laser marking process of the dye absorbing the laser energy and then vaporizing layer (in view of Nikitin 108; Fig. 3B-3C; [0038, 0041]).
The ordinary artisan would have been motivated to modify Kuo in the manner set forth above, at least, because this inclusion provides insulating layer is made of a polymer that contains particles, where a laser beam has interacted with insulating layer ([0041]) and the polymer molecules of insulating layer evaporate (Nikitin [0038, 0041]), which can help grow conductive layers on the insulating layer and increase the functionality of the device.
Conclusion
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/OMAR F MOJADDEDI/Examiner, Art Unit 2898