Attorney Docket Number: 102351-2044-01727/US13041
Filing Date: 01/18/2023
Claimed Priority Date: none
Inventors: Hsu et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 04/23/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 04/23/2026 in reply to the previous Office action mailed on 12/23/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the features canceled from the claims. No new matter should be entered.
“wherein, in the top view, the first solder has first, second, and third sides protruding from a perimeter of the first pad and a fourth side recessed from the perimeter, and wherein the fourth side is longer than the first, second, and third sides” in the device of claims 1 and 2, as recited in claim 2
“wherein the component has a first terminal and a decoupling capacitor, wherein, along the first direction, a first height of the first terminal is greater than a second height of the decoupling capacitor”, in the device of claims 1 and 8, as recited in claim 8
“wherein a first distance between a first edge of the first solder and first interlayer elements in the first column is greater than a second distance between a second edge of the first solder and the first interlayer elements in the second column” in the device of claims 1 and 10, as recited in claim 10
“wherein the component has a first terminal and a decoupling capacitor, wherein, along the third direction, a first length of the first terminal is greater than a second length of the decoupling capacitor”, in the device of claims 1, 8, and 12, as recited in claim 12
“wherein, in the top view, the first solder has first, second, and third sides protruding from a perimeter of the pad and a fourth side recessed from the perimeter, and wherein the fourth side is longer than the first, second, and third sides” in the device of claims 17 and 18, as recited in claim 18
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference characters not mentioned in the description: 321e.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
The specification fails to provide antecedent basis for the claims 2, 10, and 12, reciting, as follows:
“wherein, in the top view, the first solder has first, second, and third sides protruding from a perimeter of the first pad and a fourth side recessed from the perimeter, and wherein the fourth side is longer than the first, second, and third sides” in the device of claims 1 and 2, as recited in claim 2
“wherein the component has a first terminal and a decoupling capacitor, wherein, along the first direction, a first height of the first terminal is greater than a second height of the decoupling capacitor”, in the device of claims 1 and 8, as recited in claim 8
“wherein a first distance between a first edge of the first solder and first interlayer elements in the first column is greater than a second distance between a second edge of the first solder and the first interlayer elements in the second column” in the device of claims 1 and 10, as recited in claim 10
“wherein the component has a first terminal and a decoupling capacitor, wherein, along the third direction, a first length of the first terminal is greater than a second length of the decoupling capacitor”, in the device of claims 1, 8, and 12, as recited in claim 12
“wherein, in the top view, the first solder has first, second, and third sides protruding from a perimeter of the pad and a fourth side recessed from the perimeter, and wherein the fourth side is longer than the first, second, and third sides” in the device of claims 17 and 18, as recited in claim 18
Appropriate correction is required. No new matter should be entered.
Claim Rejections - 35 USC § 112
The following are quotations of the first paragraph of 35 U.S.C. 112(a) and 35 U.S.C. 112(b):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2, 8, 10, 12, and 18 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 2 has been amended to recite at least the new limitation “wherein, in the top view, the first solder has first, second, and third sides protruding from a perimeter of the first pad and a fourth side recessed from the perimeter, and wherein the fourth side is longer than the first, second, and third sides”.
Applicant has not alleged where support for the newly added limitations may be found. However, a review of the written description fails to find any support for the claimed side length relationships, as the specification as originally filed provides no mention of any side length relationship between sides of a first solder. Moreover, the specification even directly states in pars.0006 and 0142/ll.8-11 of published application US 2024/0243086 that the elements and features shown in the drawings are not necessarily to scale, with certain dimensions of various structures being potentially arbitrarily increased or reduced. In accordance with these statements in the written description, a review of the Drawings fails to identify any substantiative support for the limitation “wherein, in the top view, the first solder has first, second, and third sides protruding from a perimeter of the first pad and a fourth side recessed from the perimeter, and wherein the fourth side is longer than the first, second, and third sides”. Accordingly, the newly amended limitations are directed to New Matter.
Claim 8 has been amended to recite at least the new limitation “wherein the component has a first terminal and a decoupling capacitor, wherein, along the first direction, a first height of the first terminal is greater than a second height of the decoupling capacitor”.
Applicant has not alleged where support for the newly added limitations may be found. However, a review of the written description fails to find any support for the claimed terminal and decoupling capacitor height relationships, as the specification as originally filed provides no mention of any first height for a terminal or height for a decoupling capacitor at all. Moreover, the specification even directly states in pars.0006 and 0142/ll.8-11 of published application US 2024/0243086 that the elements and features shown in the drawings are not necessarily to scale, with certain dimensions of various structures being potentially arbitrarily increased or reduced. Furthermore, the specification as filed additionally identifies the terminals as integrally part of the decoupling capacitor (see pars.0041/ll.7-8 and 0043/ll.5-6 of published application US 2024/0243086). Accordingly, the distinction that the component includes “a first terminal and a decoupling capacitor”, such that the along the first direction a first height of the first terminal is greater than a second height of the decoupling capacitor, is unsupported. In accordance with these statements in the written description, a review of the Drawings fails to identify any substantiative support for the limitation “wherein the component has a first terminal and a decoupling capacitor, wherein, along the first direction, a first height of the first terminal is greater than a second height of the decoupling capacitor” and the specific conception that the component includes “a first terminal and a decoupling capacitor”, such that the along the first direction a first height of the first terminal is greater than a second height of the decoupling capacitor. Accordingly, the newly amended limitations are directed to New Matter.
Claim 10 has been amended to recite at least the new limitation “wherein a first distance between a first edge of the first solder and first interlayer elements in the first column is greater than a second distance between a second edge of the first solder and the first interlayer elements in the second column”.
Applicant has not alleged where support for the newly added limitations may be found. However, a review of the written description fails to find any support for the claimed first distance and second distance relationships, as the specification as originally filed provides no mention of any first distance between a first edge of a first solder and first interlayer elements in a first column and second distance between a second edge of a first solder and first interlayer elements in a second column features at all. Moreover, the specification even directly states in pars.0006 and 0142/ll.8-11 of published application US 2024/0243086 that the elements and features shown in the drawings are not necessarily to scale, with certain dimensions of various structures being potentially arbitrarily increased or reduced. In accordance with these statements in the written description, a review of the Drawings fails to identify any substantiative support for the limitation “wherein a first distance between a first edge of the first solder and first interlayer elements in the first column is greater than a second distance between a second edge of the first solder and the first interlayer elements in the second column”. Accordingly, the newly amended limitations are directed to New Matter.
Claim 12 has been amended to recite at least the new limitation “wherein the component has a first terminal and a decoupling capacitor, wherein, along the third direction, a first length of the first terminal is greater than a second length of the decoupling capacitor”.
Applicant has not alleged where support for the newly added limitations may be found. However, a review of the written description fails to find any support for the claimed terminal and decoupling capacitor length relationships, as the specification as originally filed provides no mention of any first length for a terminal or length for a decoupling capacitor at all. Moreover, the specification even directly states in pars.0006 and 0142/ll.8-11 of published application US 2024/0243086 that the elements and features shown in the drawings are not necessarily to scale, with certain dimensions of various structures being potentially arbitrarily increased or reduced. Furthermore, the specification as filed additionally identifies the terminals as integrally part of the decoupling capacitor (see pars.0041/ll.7-8 and 0043/ll.5-6 of published application US 2024/0243086). Accordingly, the distinction that the component includes “a first terminal and a decoupling capacitor”, such that the along the third direction a first length of the first terminal is greater than a second length of the decoupling capacitor, is unsupported. In accordance with these statements in the written description, a review of the Drawings fails to identify any substantiative support for the limitation “wherein the component has a first terminal and a decoupling capacitor, wherein, along the third direction, a first length of the first terminal is greater than a second length of the decoupling capacitor” and the specific conception that the component includes “a first terminal and a decoupling capacitor”, such that the along the third direction a first length of the first terminal is greater than a second length of the decoupling capacitor. Accordingly, the newly amended limitations are directed to New Matter.
Claim 18 has been amended to recite at least the new limitation “wherein, in the top view, the first solder has first, second, and third sides protruding from a perimeter of the pad and a fourth side recessed from the perimeter, and wherein the fourth side is longer than the first, second, and third sides”.
Applicant has not alleged where support for the newly added limitations may be found. However, a review of the written description fails to find any support for the claimed side length relationships, as the specification as originally filed provides no mention of any side length relationship between sides of a first solder. Moreover, the specification even directly states in pars.0006 and 0142/ll.8-11 of published application US 2024/0243086 that the elements and features shown in the drawings are not necessarily to scale, with certain dimensions of various structures being potentially arbitrarily increased or reduced. In accordance with these statements in the written description, a review of the Drawings fails to identify any substantiative support for the limitation “wherein, in the top view, the first solder has first, second, and third sides protruding from a perimeter of the pad and a fourth side recessed from the perimeter, and wherein the fourth side is longer than the first, second, and third sides”. Accordingly, the newly amended limitations are directed to New Matter.
The applicant may cancel the claims, amend the claims, or demonstrate explicit support for the claimed subject matter in the original disclosure (e.g., by citing specific excerpts from Specification or features in Drawings related to the claimed embodiment, as originally filed). A broad statement alleging support for the claimed subject matter will be considered non-persuasive.
Claim 12 depends from claim 8 and thus inherits the deficiencies identified supra.
Claim 6 is rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1, from which claim 6 depends, initially recites the limitation “a chip having an upper surface”. Claim 6 further recites the limitation “wherein the plurality of first interlayer elements are configured to guide the connecting element to partially cover a first lateral surface of the terminal” before reciting the limitation “wherein each of the first interlayer elements comprises a barrier layer covering a second upper surface and a second lateral surface thereof”. The language in the claim does not clearly render to which feature the term “thereof” is intended to refer. For example, based on the language previously recited in claim 6 and in parental claim 1, “thereof” could refer to any of the chip, the terminal, or the first interlayer elements themselves. Accordingly, this limitation “wherein each of the first interlayer elements comprises a barrier layer covering a second upper surface and a second lateral surface thereof” in the claim is indefinite as it is unclear to which feature the term “thereof” distinctly refers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 7-9, 12-13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chikuma (US 2021/0127493) in view of Yang (US 2004/0099934).
Regarding claim 1, Chikuma (see, e.g., figs. 10, 11, and 15) shows most aspects of the instant invention, including an electronic device comprising:
an electronic element 1 having an upper surface 1s and a first pad 2 disposed over the upper surface;
a component 100 disposed over the electronic element and configured to filter noise from the electronic element (see, e.g., pars.0003/ll.1-3 and 0005);
a plurality of first interlayer elements 11b, 11a connecting the first pad, wherein at least one 11b of the plurality of interlayer elements is non-overlapping with the component in a first direction T substantially perpendicular to the upper surface (see, e.g., fig. 11 and par.0088/ll.9-10);
wherein:
the first interlayer elements 11b, 11a are arranged in a first array configuration and separated from each other, the first array configuration comprising a plurality of rows and a plurality of columns in a top view (see, e.g., fig. 15), and the rows extend in a second direction L and the columns extend in a third direction W perpendicular to the first direction T, wherein each of the first interlayer elements in a first column (column corresponding to 11b) are non-overlapping with the component 100 in the first direction (see, e.g., fig. 11 and par.0088/ll.9-10) and each of the first interlayer elements in a second column (column corresponding to 11a) are overlapping with the component in the first direction (see, e.g., fig. 11 and par.0088/ll.1-3)
Chikuma shows most aspects of the invention. Furthermore, Chikuma teaches that Chikuma’s electronic element may be a circuit board and that Chikuma’s component may be configured to filter noise from Chikuma’s circuit board (see, e.g. pars.0003/ll.1-3, 0005, and 0030/ll.5). Chikuma, however, fails to explicitly specify that Chikuma’s electronic element may be a chip and that Chikuma’s component is configured to filter noise from the chip.
Yang, in the same field of endeavor, teaches chips to be suitable substrates for mounting noise-filtering components, pads, and interlayer elements, wherein such a chip is shown to be mounted on a circuit board (see, e.g., Yang: fig. 6). Yang further teaches that having a noise-filtering component directly installed on a chip, which is itself installed on a circuit board, reduces the number of devices needed on the circuit board, saving board space and making it possible to shrink the size of the circuit board, which subsequently reduces costs (see, e.g., Yang: pars.0010 and 0044). Yang additionally teaches that having the noise-filtering component configured to filter noise from the chip can further enhance the performance of the electronic device by reducing simultaneous switching noise (see, e.g., Yang: pars.0006/ll.1-3, 0007, 0042-0043).
Yang is evidence showing that one of ordinary skill in the art would appreciate that an electronic device comprising a chip and a component configured to filter noise from the chip would be equivalent to an electronic device comprising a circuit board and a component configured to filter noise from the circuit board, and that such differences would result in no unexpected changes in the performance of the electronic device of Chikuma. That is, the electronic substrates of both Chikuma and Yang would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting external electronic and noise-filtering components.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chikuma’s electronic device comprise either a chip and a component configured to filter noise from the chip, as taught by Yang, or a circuit board and a component configured to filter noise from the circuit board, as taught by Chikuma, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting external electronic and noise-filtering components. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, Yang is evidence that at the time of filing the invention one of ordinary skill in the art would find particular incentive to have Chikuma’s electronic element comprise a chip installed on Chikuma’s circuit board, wherein Chikuma’s component is further configured to filter noise from the chip, as taught by Yang, so as to reduce the number of devices needed on Chikuma’s circuit board, saving space and making it possible to shrink the size of Chikuma’s circuit board, subsequently reducing costs in a manner further allowing enhancement of the performance of Chikuma’s electronic device through reduction of simultaneous switching noise.
Furthermore, and accordingly, the specific claim limitation that Chikuma’s component is configured to filter noise from the chip is a property of the component of Chikuma and Yang’s device.
Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
In the instant case, Chikuma teaches the same component with noise-filtering capabilities as recited in the claim, therefore, the component will have the chip noise-filtering configuration and capacity also recited in the claim.
Regarding claim 13, Chikuma (see, e.g., figs. 10, 11, and 15) shows most aspects of the instant invention, including an electronic device comprising:
an electronic element 1 having a pad 2;
a component 100 disposed over the electronic element and having a terminal 120;
a plurality of first interlayer elements 11b, 11a disposed over the pad and configured to guide a first connecting element 4 to partially cover a lateral surface (portions of 120 not parallel to L) of the terminal;
wherein:
the first interlayer elements 11b, 11a are arranged in an array configuration and separated from each other, the array configuration comprising a plurality of rows and a plurality of columns in a top view (see, e.g., fig. 15), and the rows extend in a first direction L and the columns extend in a second direction W perpendicular to the first direction, wherein each of the first interlayer elements in a first column (column corresponding to 11b) are non-overlapping with the component 100 in the a third direction T substantially perpendicular an upper surface 1s of the electronic element (see, e.g., fig. 11 and par.0088/ll.9-10) and each of the first interlayer elements in a second column (column corresponding to 11a) are overlapping with the component in the third direction (see, e.g., fig. 11 and par.0088/ll.1-3)
Chikuma shows most aspects of the invention. Furthermore, Chikuma teaches that Chikuma’s electronic element may be a circuit board and that Chikuma’s component may be configured to filter noise from Chikuma’s electronic element (see, e.g. pars.0003/ll.1-3, 0005, and 0030/ll.5). Chikuma, however, fails to explicitly specify that Chikuma’s electronic element may be a chip. Yang, in the same field of endeavor, teaches chips to be suitable substrates for mounting noise-filtering components, pads, and interlayer elements, wherein such a chip is shown to be mounted on a circuit board (see, e.g., Yang: fig. 6). Yang further teaches that having a noise-filtering component directly installed on a chip, which is itself installed on a circuit board, reduces the number of devices needed on the circuit board, saving board space and making it possible to shrink the size of the circuit board, which subsequently reduces costs (see, e.g., Yang: pars.0010 and 0044).
Yang is evidence showing that one of ordinary skill in the art would appreciate that an electronic device comprising a chip would be equivalent to an electronic device comprising a circuit board, and that such differences would result in no unexpected changes in the performance of the device of Chikuma. That is, the electronic substrates of both Chikuma and Yang would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting other electronic components.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chikuma’s electronic device comprise either a chip, as taught by Yang, or a circuit board, as taught by Chikuma, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting other electronic components. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Moreover, Yang teaches that at the time of filing the invention one of ordinary skill in the art would find particular incentive to have Chikuma’s electronic element comprise a chip installed on Chikuma’s circuit board, as taught by Yang, so as to reduce the number of devices needed on Chikuma’s circuit board, saving space and making it possible to shrink the size of Chikuma’s circuit board, subsequently reducing costs.
Regarding claim 3, Chikuma (see, e.g., figs. 10, 11, and 15) further shows a plurality of second interlayer elements 12b, 12a disposed over a second pad 3 of the chip 1 (see, e.g., fig. 11 and par.0079/ll.1-6) (see the comments stated above in paragraphs 27-35 regarding the chip, which are considered to be repeated here), wherein the component 100 comprises a first terminal 120 electrically connected to the first interlayer elements 11b, 11a and a second terminal 130 electrically connected to the second interlayer elements 12b, 12a (see, e.g., par.0065), wherein the second interlayer elements are arranged in a second array configuration identical to the first array configuration and separated from each other, wherein each of the second interlayer elements in a third column (column corresponding to 12b) are non-overlapping with the component in the first direction T (see, e.g., fig. 11 and par.0090/ll.9-10) and each of the second interlayer elements in a fourth column (column corresponding to 12a) are overlapping with the component in the first direction (see, e.g., fig. 11 and par.0090/ll.1-3).
Regarding claim 7, Chikuma (see, e.g., figs. 10, 11, and 15) shows that the columns (columns corresponding to 11b and 11a, respectively) each have an axis substantially perpendicular to a longitudinal edge (edge of 100 corresponding to L) of the component 100 in the top view.
Regarding claim 8, Chikuma (see, e.g., figs. 10, 11, and 15 and pars.0031/ll.1-3 and 0100/ll.1-5) shows that the component has a first terminal 120 and a decoupling capacitor 110, wherein, along the first direction T, a first height of the first terminal 120 is greater than a second height of the decoupling capacitor (see, e.g., fig. 11, wherein 120 is shown to cover both top and side surfaces of 110).
Regarding claim 9, Chikuma (see, e.g., figs. 10, 11, and 15 and par.0088/ll.1-3) shows that a first number (e.g., 2) of the first interlayer elements 11b, 11a in the second column (column corresponding to 11a) that entirely overlaps the component 100 is greater than a second number (e.g., 0) of the first interlayer elements in the second column that partially overlaps the component.
Regarding claim 12, Chikuma (see, e.g., figs. 10, 11, and 15 and pars.0036/ll.1-4, 0064/ll.1-4, and 0119/ll.6-8) shows that, along the third direction W, a first length of the first terminal 120 is greater than a second length of the decoupling capacitor 110.
Regarding claim 16, Chikuma (see, e.g., figs. 10, 11, and 15 and pars.0057/ll.7-11 and 0065) shows that the first interlayer elements 11b, 11a in the second column (column corresponding to 11a) are disposed below the terminal 120, and wherein the first interlayer elements in the second column is electrically connected to the first interlayer elements in the first column (column corresponding to 11b) through the pad 2.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chikuma in view of Yang and Ko (US 2020/0105694).
Regarding claim 17, Chikuma (see, e.g., figs. 10, 11, and 15) shows most aspects of the instant invention, including an electronic device comprising:
an electronic element 1 having a pad 2 and an exposed portion of the pad;
a component 100 disposed over the electronic element and comprising a terminal 120;
a plurality of interlayer elements 11b, 11a spaced apart from each other and disposed over the exposed portion of the pad to connect the terminal and the pad;
wherein:
the first interlayer elements 11b, 11a are arranged in an array configuration and separated from each other, the array configuration comprising a plurality of rows and a plurality of columns in a top view (see, e.g., fig. 15), and the rows extend in a first direction L and the columns extend in a second direction W perpendicular to the first direction, wherein each of the first interlayer elements in a first column (column corresponding to 11b) are non-overlapping with the component 100 in the a third direction T substantially perpendicular an upper surface 1s of the electronic element (see, e.g., fig. 11 and par.0088/ll.9-10) and each of the first interlayer elements in a second column (column corresponding to 11a) are overlapping with the component in the third direction (see, e.g., fig. 11 and par.0088/ll.1-3)
Chikuma shows most aspects of the invention. Furthermore, Chikuma teaches that Chikuma’s electronic element may be a circuit board and that Chikuma’s component may be configured to filter noise from Chikuma’s electronic element (see, e.g. pars.0003/ll.1-3, 0005, and 0030/ll.5). Chikuma, however, fails to explicitly specify that Chikuma’s electronic element may be a chip. Yang, in the same field of endeavor, teaches chips to be suitable substrates for mounting noise-filtering components, pads, and interlayer elements, wherein such a chip is shown to be mounted on a circuit board (see, e.g., Yang: fig. 6). Yang further teaches that having a noise-filtering component directly installed on a chip, which is itself installed on a circuit board, reduces the number of devices needed on the circuit board, saving board space and making it possible to shrink the size of the circuit board, which subsequently reduces costs (see, e.g., Yang: pars.0010 and 0044).
Yang is evidence showing that one of ordinary skill in the art would appreciate that an electronic device comprising a chip would be equivalent to an electronic device comprising a circuit board, and that such differences would result in no unexpected changes in the performance of the device of Chikuma. That is, the electronic substrates of both Chikuma and Yang would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting other electronic components.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chikuma’s electronic device comprise either a chip, as taught by Yang, or a circuit board, as taught by Chikuma, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting other electronic components. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Moreover, Yang is evidence that at the time of filing the invention one of ordinary skill in the art would find particular incentive to have Chikuma’s electronic element comprise a chip installed on Chikuma’s circuit board, as taught by Yang, so as to reduce the number of devices needed on Chikuma’s circuit board, saving space and making it possible to shrink the size of Chikuma’s circuit board, subsequently reducing costs.
Furthermore, although Chikuma teaches most aspects of the invention, including that a portion of Chikuma’s pad is exposed to connect with the plurality of interlayer elements, Chikuma fails to teach that Chikuma’s chip (see the comments stated above in paragraphs 27-35 regarding the chip, which are considered to be repeated here) has an insulating layer exposing an exposed portion of the pad.
Yang, in the same field of endeavor and in a similar device to Chikuma, teaches a chip 60 having an insulating layer 67, wherein the insulating layer exposes an exposed portion of a pad 61 so that a terminal 53 may be connected to the pad (see, e.g., Yang: fig. 5). Yang teaches that such an insulating layer may act as a protection layer for the device while facilitating connection between the pad and terminal (see, e.g., Yang: par.0029/ll.11-16). Furthermore, Ko, also in the same field of endeavor and in a similar device to Chikuma, additionally teaches that using an insulating layer 190 to expose an exposed portion of a pad 182a, wherein the pad connects to a terminal 34 of a component 30 through the exposed portion of the pad and an interlayer element 40, allows the device and pad to be protected from external physical and chemical damages whilst simultaneously facilitating connections between the terminal and the pad (see, e.g., Ko: fig. 19 and pars.0072/ll.1-3 and 0116).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chikuma’s chip (see the comments stated above in paragraphs 27-35 regarding the chip, which are considered to be repeated here) have an insulating layer exposing an exposed portion of the pad such that the plurality of interlayer elements are disposed over the exposed portion of the pad to connect the terminal and the pad, as taught by Yang and Ko, so as to protect Chikuma’s device and pad from external physical and chemical damages whilst simultaneously facilitating connecting Chikuma’s pad to Chikuma’s terminal.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chikuma/Yang in view of Nakamura (US 2011/0304016).
Regarding claim 11, Chikuma/Yang shows most aspects of the instant invention (see paragraphs 27-35 above). Chikuma (see, e.g., figs. 10, 11, and 15) further shows empty space in a region defined by a lower surface of the component 100 and the upper surface of the chip 1 (see the comments stated above in paragraphs 27-35 regarding the chip, which are considered to be repeated here). Chikuma, however, fails to specify that a molding material is formed in this region, wherein the region is void-free. Nakamura, in the same field of endeavor and in a similar device to Chikuma, teaches that including a molding material in a region defined by a lower surface of a component and an upper surface of an electronic substrate helps to insulate and protect the exposed conductive portions of the component from the outside, wherein it is noted that such a disposition mirrors the empty space of Chikuma (see, e.g., Nakamura: pars.0034/ll.6-11 and 0035/ll.5-7). Nakamura further teaches that when such a region is void-free that short defects are mitigated and insulation reliability is improved (see, e.g., Nakamura: par.0085/ll.11-15).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a molding material in the empty space of Chikuma, that is, in a region defined by a lower surface of the component and the upper surface of the chip (see the comments stated above in paragraphs 27-35 regarding the chip, which are considered to be repeated here), wherein the region is void-free, as taught by Nakamura, so as to better insulate and protect the exposed conductive portions of Chikuma’s component from the outside in a matter that simultaneously improves insulation reliability and mitigates undesired short defects.
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chikuma/Yang in view of Onoko (US 2022/0102330).
Regarding claim 14, Chikuma shows that a portion of the first connecting element 4 is over a lower surface of the terminal 120, and the portion of the first connecting element has a width gradually decreasing in a direction facing away from the pad 2. Chikuma (see, e.g., figs. 11 and 15) further shows that the first connecting element is disposed adjacent to another connecting element. Chikuma, however, fails to specify that the portion is trapezoidal. Onoko, in the same field of endeavor and in a similar device to Chikuma, teaches trapezoidal connecting element portion shapes to be suitable shapes for connecting a pad and component through a connecting element, wherein Onoko further teaches that trapezoidal connecting element portion shapes improve the bonding strength between attached pads and terminals of components while simultaneously preventing short circuiting between adjacent connecting elements (see, e.g., Onoko: par.0068/ll.1-2 and 14-24).
Onoko is evidence showing that one of ordinary skill in the art would appreciate that a trapezoidal portion shape would be equivalent to a portion of another shape, and that such differences would result in no unexpected changes in the performance of the device of Chikuma/Yang. That is, the portion shapes of both Chikuma and Onoko would yield the predictable result of providing suitable connective structures adequately positioned for connecting a terminal of a component with an underlying pad.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a trapezoidal portion shape, as taught by Onoko, or a portion of another shape, as taught by Chikuma, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable connective structures adequately positioned for connecting a terminal of a component with an underlying pad. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Moreover, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the portion in Chikuma’s device be trapezoidal, as taught by Onoko, so as to improve the bonding strength between Chikuma’s pad and terminal while simultaneously preventing short circuiting between adjacent connecting element portions.
Allowable Subject Matter
Claims 4-5, 15, and 19-20 are rejected and objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
Claims 2, 6, 10, and 18 are rejected and objected to as being dependent upon a rejected base claim, but would be allowable if (1) rewritten or otherwise established to overcome the 35 U.S.C. 112 rejections put forth in this Office action and (2) rewritten in independent form including all the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s amendments to the drawings have overcome most of the objections to the drawings put forth in the previous Office action mailed on 12/23/2025. Accordingly, the corresponding objections to the drawings have been withdrawn and the remaining objections to the drawings are maintained.
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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