Attorney Docket Number: 102351-2044-01727/US13041 Filing Date: 01/18/2023 Claimed Priority Date: none Inventors: Hsu et al. Examiner: Shamita S. Hanumasagar DETAILED ACTION This Office action responds to the election filed on 10/13/2025 . Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis ( i.e. , changing from AIA to pre-AIA) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Elections/Restrictions Applicant’s election without traverse of Species 8 , reading on figure 3 -3A , in the reply filed on 10/13/2025 , is acknowledged. The applicant indicated that claims 1-20 read on the elected species. The examiner agrees. Accordingly, pending in this Office action are claims 1-20. Initial Remarks For all non-U.S. -reference paragraph and line number citations, please refer to the translated English versions of the documents, which are attached to this Office action. Drawings Quotes from the specification are from the published application US 2024/0243086. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they ( e.g. , figure 3A) do not include the following reference signs mentioned in the description: FILLIN "Enter reference sign(s) not found in the drawings and include page and line number where they first occur in the specification" \* MERGEFORMAT H1 . The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference characters not mentioned in the description: FILLIN "Enter the appropriate information " \* MERGEFORMAT DR2 , 321e , L51 , L52 , 31′, 32′ . The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters " DR2 " and " DR3 " have both been used to designate a same orientation perpendicular to DR1 (se e, as a non-limited single example, fig s . 2- 2A and par.0079/ll.11 ). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections The claims are objected to because of the following informalities: In line 2 of claim 7, “wherein the columns each has” should read “wherein the columns each ha ve ” In line 2 of claim 16, “wherein a second group of the first interlayer elements are disposed” should read “wherein a second group of the first interlayer elements is disposed” Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 5 is rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 5 recites the limitation “two of the adjacent first interlayer elements”. No arrangement or disposition for the first interlayer elements was ever recited in the claim or in any parental claim for claim 5. As such, there is insufficient antecedent basis for the limitation “two of the adjacent first interlayer elements ” in the claim, as no first interlayer elements were previously recited in the claim or in any applicable parental claim to be adjacent. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 1-3, 7 , and 12 are rejected under 35 U.S.C. 102 FILLIN "Insert either \“(a)(1)\” or \“(a)(2)\” or both. If paragraph (a)(2) of 35 U.S.C. 102 is applicable, use form paragraph 7.15.01.aia, 7.15.02.aia or 7.15.03.aia where applicable." \d "[ 2 ]" (a)(1) as being FILLIN "Insert either—clearly anticipated—or—anticipated—with an explanation at the end of the paragraph." \d "[ 3 ]" anticipated by FILLIN "Insert the prior art relied upon." \d "[ 4 ]" Yang (US 2004/0099934) . Regarding claim 1 , Yang (see, e.g. , fig. 6 ) shows all aspects of the instant invention, including an electronic device comprising: a chip 60 having an upper surface (top of 60 closest to 51 , including below 41 ) and a first pad (rightmost 4 1 ) disposed over the upper surface ; a component 50 disposed over the chip and configured to filter noise from the chip (see, e.g. , pars.0011 and 0029/ll.22-23); a plurality of first interlayer elements (rightmost 42 ) , 6 2 ’ connecting the first pad (see, e.g. , pars.0028/ll.7-9 and 0030/ll.8-9) , wherein at least one (rightmost 42 ) of the plurality of the first interlayer elements is non-overlapping with the component in a direction substantially perpendicular to the upper surface of the component ( horizontal top surface of 5 1 farthest from 60 ) Regarding claim 2, Yang (see, e.g. , fig. 6) shows that the plurality of the first interlayer elements (rightmost 42 ) , 62’ are spaced apart from each other. Regarding claim 3, Yang (see, e.g. , fig. 6 and par s . 0028/ll.7-9 and 0030/ll.8-10 and ll. 20-24 ) further shows a plurality of second interlayer elements (leftmost 42 ) , 61’ disposed over a second pad (leftmost 41 ) of the chip 60 , wherein the component 50 comprises a first terminal (rightmost 53 ) electrically connected to the first interlayer elements (rightmost 42 ) , 62’ and a second terminal (leftmost 53 ) electrically connected to the second interlayer elements. Regarding claim 7, Yang (see, e.g. , fig. 6) shows that the first interlayer elements (rightmost 42 ) , 62’ are arranged in a plurality of columns ( e.g. , a n effective vertical column corresponding to a horizontal width of (rightmost 42 ) and another effective vertical column corresponding to a horizontal width of 62’ ), wherein the columns each has an axis substantially perpendicular to a longitudinal axis ( e.g. , a horizontal axis parallel to the component’s upper surface ) of the component. Regarding claim 12, Yang (see, e.g. , par.0030/ll.26-27) shows that the component 50 comprises a decoupling capacitor. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 1- 5, 7 -11 , 13-14, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art relied upon." \d "[ 2 ]" Lu (US 2020/0286980) in view of Yang . Regarding claim 1, Lu (see, e.g. , fig. 2H) shows most aspects of the instant invention, including an electronic device comprising: a substrate 205 having an upper surface ( horizontal top surface of 205 closest to 201 ) and a first pad (rightmost 203 disposed in 204D ) disposed over the upper surface; a component 201 disposed over the substrate and configured to filter noise (see, e.g. par.0052/ll.6-13); and a plurality of first interlayer elements 204M, 204N connecting the first pad, wherein at least one 204N of the plurality of first interlayer elements is non-overlapping with the component in a direction substantially perpendicular to the upper surface ( horizontal top surface of 201 farthest from 205 ) of the component Lu shows most aspects of the invention. Furthermore, Lu teaches that Lu’s substrate may be a printed circuit board having circuits therein and that Lu’s component may be configured to filter noise (see, e.g. par.0052/ll.6-13). Lu, however, fails to explicitly specify that Lu’s substrate may be a chip and that Lu’s component is configured to filter noise from the chip. Yang, in the same field of endeavor, teaches chips to be suitable substrates for mounting noise-filtering components, pads, and interlayer elements, wherein such a chip is shown to be mounted on a printed circuit board (see, e.g. , Yang: fig. 6). Yang further teaches that having a noise-filtering component directly installed on a chip , which is itself installed on a printed circuit board , reduces the number of devices needed on the printed circuit board, saving board space and making it possible to shrink the size of the printed circuit board, which subsequently reduces costs (see, e.g. , Yang: pars.0010 and 0044). Yang additionally teaches that having the noise-filtering component configured to filter noise from the chip can further enhance the performance of the electronic device by reducing simultaneous switching noise (see, e.g. , Yang: pars. 0006/ll.1-3, 0007 , 0042-0043 ). Yang is evidence showing that one of ordinary skill in the art would appreciate that an electronic device comprising a chip and a component configured to filter noise from the chip would be equivalent to an electronic device comprising a printed circuit board having circuits therein and a component generally configured to filter noise , and that such differences would result in no unexpected changes in the performance of the electronic device of Lu. That is, the electronic substrates of both Lu and Yang would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting external electronic and noise-filtering components. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Lu’s electronic device comprise either a chip and a component configured to filter noise from the chip , as taught by Yang, or a printed circuit board having circuits therein and a component generally configured to filter noise , as taught by Lu, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting external electronic and noise-filtering components. KSR International Co. v. Teleflex Inc. , 550 U.S.-- ,82 USPQ2d 1385 (2007). Furthermore, Yang teaches that at the time of filing the invention one of ordinary skill in the art would find particular incentive to have Lu’s substrate comprise a chip installed on Lu’s printed circuit board, wherein Lu’s component is further configured to filter noise from the chip, as taught by Yang, so as to reduce the number of devices needed on Lu’s printed circuit board, saving space and making it possible to shrink the size of Lu’s printed circuit board, subsequently reducing costs in a manner further allowing enhancement of the performance of Lu’s electronic device through reduction of simultaneous switching noise . Furthermore, and accordingly, the specific claim limitation that Lu’s component is configured to filter noise from the chip is a property of the component of Lu and Yang’s device. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best , 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada , 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best , 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp. v. Banner , 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985). In the instant case, Lu teaches the same component with noise-filtering capabilities as recited in the claim, therefore, the component will have the chip noise-filtering configuration and capacity also recited in the claim. Regarding claim 2, Lu (see paragraphs REF _Ref216907223 \r \h \* MERGEFORMAT 23 - REF _Ref216907227 \r \h \* MERGEFORMAT 30 above and , e.g. , fig. 2H) shows that the plurality of the first interlayer elements 204M, 204N are spaced apart from each other. Regarding claim 3, Lu (see paragraphs REF _Ref216907223 \r \h \* MERGEFORMAT 23 - REF _Ref216907227 \r \h \* MERGEFORMAT 30 above and, e.g. , fig. 2H and pars.0074/ll.10-17 , 0083/ll.8-12 , and 0102/ll.5-9 ) shows that Lu’s electronic device further comprises a plurality of second interlayer elements 204K, 204L disposed over a second pad (leftmost 203 disposed in 204C ) of the chip 205 (see the comments stated above in paragraphs REF _Ref216907223 \r \h \* MERGEFORMAT 23 - REF _Ref216907227 \r \h \* MERGEFORMAT 30 regarding the chip, which are considered to be repeated here), wherein the component comprises a first terminal 224 electrically connected to the first interlayer elements and a second terminal 222 electrically connected to the second interlayer elements. Regarding claim 4, Lu (see paragraphs REF _Ref216907223 \r \h \* MERGEFORMAT 23 - REF _Ref216907227 \r \h \* MERGEFORMAT 30 above and, e.g. , fig. 2H) shows a first connecting element (rightmost 203 directly contacting both 224 and 204B ) connecting the component 201 and the first interlayer elements 204M, 204N . Regarding claim 5, Lu (see paragraphs REF _Ref216907223 \r \h \* MERGEFORMAT 23 - REF _Ref216907227 \r \h \* MERGEFORMAT 30 and REF _Ref216964679 \r \h \* MERGEFORMAT 33 above and, e.g. , fig. 2H) shows that a portion of the first connecting element (rightmost 203 directly contacting both 224 and 204B ) is disposed between two 204M, 204N adjacent first interlayer elements 204M, 204N (see, e.g. , fig. 2H, in which a n orthographic projection of a horizontal portion of the first conductive element on the pad (rightmost 203 disposed in 204D ) falls laterally and horizontally between orthographic projections of first interlayer elements 204M and 204 N on the pad ). With regards to other language recited in claim 5, see the comments stated above in paragraph REF _Ref216969830 \r \h \* MERGEFORMAT 13 . Regarding claim 7, Lu (see paragraphs REF _Ref216907223 \r \h \* MERGEFORMAT 23 - REF _Ref216907227 \r \h \* MERGEFORMAT 30 above and, e.g. , fig. 2H) shows that the first interlayer elements 204M, 204N are arrange d in a plurality of columns ( e.g. , an effective vertical column corresponding to a horizontal width of 204M and another effective vertical column corresponding to a horizontal width of 204N ), wherein the columns each has an axis substantially perpendicular to a longitudinal axis ( e.g. , a horizontal axis corresponding to the component’s upper surface ) of the component 201 . Regarding claim 8, Lu (see paragraphs REF _Ref216907223 \r \h \* MERGEFORMAT 23 - REF _Ref216907227 \r \h \* MERGEFORMAT 30 and REF _Ref216964679 \r \h \* MERGEFORMAT 33 above and, e.g. , fig. 2H) shows that the component 201 has a first terminal 224 , and a portion of the first connecting element (rightmost 203 directly contacting both 224 and 204B ) is in contact with a lateral surface of the first terminal. Regarding claim 11, Lu (see paragraphs REF _Ref216907223 \r \h \* MERGEFORMAT 23 - REF _Ref216907227 \r \h \* MERGEFORMAT 30 above and, e.g. , fig. 2H) shows a molding material 210 formed in a region defined by a lower surface (horizontal bottom surface of 201 closest to 205 ) of the component 201 and the upper surface (horizontal top surface of 205 closest to 201 ) of the chip 205 (see the comments stated above in paragraphs REF _Ref216907223 \r \h \* MERGEFORMAT 23 - REF _Ref216907227 \r \h \* MERGEFORMAT 30 regarding the chip, which are considered to be repeated here). Regarding claim 1, Lu (see, e.g. , fig. 2H) shows most aspects of the instant invention, including an electronic device comprising: a substrate 205 having an upper surface (horizontal top surface of 205 closest to 201 ) and a first pad (rightmost 203 disposed in 204D ) disposed over the upper surface; a component 201 disposed over the substrate and configured to filter noise (see, e.g. par.0052/ll.6-13); and a plurality of first interlayer elements 204M, 204B, 204N connecting the first pad, wherein at least one 204N of the plurality of first interlayer elements is non-overlapping with the component in a direction substantially perpendicular to the upper surface (horizontal top surface of 201 farthest from 205 ) of the component Lu shows most aspects of the invention. Furthermore, Lu teaches that Lu’s substrate may be a printed circuit board having circuits therein and that Lu’s component may be configured to filter noise (see, e.g. par.0052/ll.6-13). Lu, however, fails to explicitly specify that Lu’s substrate may be a chip and that Lu’s component is configured to filter noise from the chip. Yang, in the same field of endeavor, teaches chips to be suitable substrates for mounting noise-filtering components, pads, and interlayer elements, wherein such a chip is shown to be mounted on a printed circuit board (see, e.g. , Yang: fig. 6). Yang further teaches that having a noise-filtering component directly installed on a chip, which is itself installed on a printed circuit board, reduces the number of devices needed on the printed circuit board, saving board space and making it possible to shrink the size of the printed circuit board, which subsequently reduces costs (see, e.g. , Yang: pars.0010 and 0044). Yang additionally teaches that having the noise-filtering component configured to filter noise from the chip can further enhance the performance of the electronic device by reducing simultaneous switching noise (see, e.g. , Yang: pars.0006/ll.1-3, 0007, 0042-0043). Yang is evidence showing that one of ordinary skill in the art would appreciate that an electronic device comprising a chip and a component configured to filter noise from the chip would be equivalent to an electronic device comprising a printed circuit board having circuits therein and a component generally configured to filter noise, and that such differences would result in no unexpected changes in the performance of the electronic device of Lu. That is, the electronic substrates of both Lu and Yang would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting external electronic and noise-filtering components. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Lu’s electronic device comprise either a chip and a component configured to filter noise from the chip, as taught by Yang, or a printed circuit board having circuits therein and a component generally configured to filter noise, as taught by Lu, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting external electronic and noise-filtering components. KSR International Co. v. Teleflex Inc. , 550 U.S.-- ,82 USPQ2d 1385 (2007). Furthermore, Yang teaches that at the time of filing the invention one of ordinary skill in the art would find particular incentive to have Lu’s substrate comprise a chip installed on Lu’s printed circuit board, wherein Lu’s component is further configured to filter noise from the chip, as taught by Yang, so as to reduce the number of devices needed on Lu’s printed circuit board, saving space and making it possible to shrink the size of Lu’s printed circuit board, subsequently reducing costs in a manner further allowing enhancement of the performance of Lu’s electronic device through reduction of simultaneous switching noise. Furthermore, and accordingly, the specific claim limitation that Lu’s component is configured to filter noise from the chip is a property of the component of Lu and Yang’s device. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best , 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada , 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best , 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp. v. Banner , 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985). In the instant case, Lu teaches the same component with noise-filtering capabilities as recited in the claim, therefore, the component will have the chip noise-filtering configuration and capacity also recited in the claim. Regarding claim 9, Lu (see paragraphs REF _Ref216963979 \r \h \* MERGEFORMAT 38 - REF _Ref216963980 \r \h \* MERGEFORMAT 45 above and, e.g. , fig. 2H) shows that the first interlayer elements 204M, 204B, 204N has a first group 204M, 204B overlapping the component 201 in the direction substantially perpendicular to the upper surface (horizontal top surface of 201 farthest from 205 ) of the component and a second group 204N non-overlapping with the component in the direction substantially perpendicular to the upper surface of the component, and wherein a first number of the first group of the first interlayer elements is greater than a second number of the second group of the first interlayer elements. Regarding claim 10, Lu (see paragraphs REF _Ref216963979 \r \h \* MERGEFORMAT 38 - REF _Ref216964292 \r \h \* MERGEFORMAT 46 above and, e.g. , fig. 2H and par.0074/ll.9-17) shows that one 204M of Lu’s first group 204M, 204B of first interlayer elements 204M, 204B, 204N is formed in the same manner as one 204N of Lu’s second group 204N of first interlayer elements . Accordingly , Lu (see paragraphs REF _Ref216963979 \r \h \* MERGEFORMAT 38 - REF _Ref216964292 \r \h \* MERGEFORMAT 46 above and, e.g. , fig. 2H and par.0074/ll.9-17) shows that the first group 204M, 204B of the first interlayer elements 204M, 204B, 204N has a first height ( e.g. , a height of 204M ) substantially the same as a second height ( e.g. , a height of 204N ) of the second group 204N of the plurality of the first interlayer elements. Regarding claim 1 3 , Lu (see, e.g. , fig. 2H) shows most aspects of the instant invention, including a n electronic device comprising: a substrate 205 having a pad ( rightmost 203 disposed in 204D ) ; a component 201 disposed over the substrate and having a terminal 224 ; a first plurality of interlayer elements 204M, 204B, 204N disposed over the pad and configured to guide a first connecting element (rightmost 203 directly contacting both 224 and 204B ) to partially cover a lateral surface of the terminal Lu shows most aspects of the instant invention . Furthermore, Lu teaches that Lu’s substrate may be a printed circuit board having circuits therein and that Lu’s component may be configured to filter noise (see, e.g. par.0052/ll.6-1 3) . Lu , however, fails to explicitly specify that Lu’s substrate may be a chip. Yang, in the same field of endeavor, teaches chips to be suitable substrates for mounting noise-filtering components, pad s , and interlayer elements , wherein such a chip is shown to be mounted on a printed circuit board (see, e.g. , Yang: fig. 6). Yang further teaches that having a noise- filtering component directly installed on a chip, which is itself installed on a printed circuit board, reduces the number of devices needed on the printed circuit board, saving board space and making it possible to shrink the size of the printed circuit board, which subsequently reduces costs (see, e.g. , Yang: pars.0010 and 0044) . Yang is evidence showing that one of ordinary skill in the art would appreciate that an electronic device comprising a chip would be equivalent to an electronic device comprising a printed circuit board having circuits therein , and that such differences would result in no unexpected changes in the performance of the device of Lu. That is, the electronic substrates of both Lu and Yang would yield the predictable result of providing an electrically - conductive circuit-hosting support structure for mounting other electronic components. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Lu’s electronic device comprise either a chip , as taught by Yang , or a printed circuit board having circuits therein , as taught by Lu , because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting other electronic components . KSR International Co. v. Teleflex Inc. , 550 U.S.-- ,82 USPQ2d 1385 (2007). Furthermore, Yang teaches that at the time of filing the invention one of ordinary skill in the art would find particular incentive to have Lu’s substrate comprise a chip installed on Lu’s printed circuit board, as taught by Yang, so as to reduce the number of devices needed on Lu’s printed circuit board, saving space and making it possible to shrink the size of Lu’s printed circuit board, subsequently reducing costs. Regarding claim 14, Lu (see paragraphs REF _Ref216964786 \r \h \* MERGEFORMAT 48 - REF _Ref216964788 \r \h \* MERGEFORMAT 51 above and, e.g. , fig. 2H) shows that a portion of the first connecting element (rightmost 203 directly contacting both 224 and 204B ) is over a lower surface (horizontal bottom surface of 224 closest to 205 ) of the terminal 224 , and the portion of the first connecting element has a width gradually decreasing in a direction facing away from the pad (rightmost 203 disposed in 204D ) . Regarding claim 17, Lu (see, e.g. , fig. 2H) shows most aspects of the instant invention, including an electronic device comprising: a substrate 205 having a pad (rightmost 203 disposed in 204D ) and an insulating layer 210 (see, e.g. , pars.0064 and 0081/ll.8-9) exposing an exposed portion of the pad; a component 201 disposed over the substrate and comprising a terminal 224 ; and a plurality of interlayer elements 204M, 204N spaced apart from each other and disposed over the exposed portion of the pad to connect the terminal and the pad Lu shows most aspects of the instant invention. Furthermore, Lu teaches that Lu’s substrate may be a printed circuit board having circuits therein and that Lu’s component may be configured to filter noise (see, e.g. par.0052/ll.6-13). Lu, however, fails to explicitly specify that Lu’s substrate may be a chip. Yang, in the same field of endeavor, teaches chips to be suitable substrates for mounting noise-filtering components, pads, and interlayer elements, wherein such a chip is shown to be mounted on a printed circuit board (see, e.g. , Yang: fig. 6). Yang further teaches that having a noise- filtering component directly installed on a chip, which is itself installed on a printed circuit board, reduces the number of devices needed on the printed circuit board, saving board space and making it possible to shrink the size of the printed circuit board, which subsequently reduces costs (see, e.g. , Yang: pars.0010 and 0044). Yang is evidence showing that one of ordinary skill in the art would appreciate that an electronic device comprising a chip would be equivalent to an electronic device comprising a printed circuit board having circuits therein , and that such differences would result in no unexpected changes in the performance of the device of Lu. That is, the electronic substrates of both Lu and Yang would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting other electronic components. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Lu’s electronic device comprise either a chip, as taught by Yang, or a printed circuit board having circuits therein , as taught by Lu, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting other electronic components. KSR International Co. v. Teleflex Inc. , 550 U.S.-- ,82 USPQ2d 1385 (2007). Furthermore, Yang teaches that at the time of filing the invention one of ordinary skill in the art would find particular incentive to have Lu’s substrate comprise a chip installed on Lu’s printed circuit board, as taught by Yang, so as to reduce the number of devices needed on Lu’s printed circuit board, saving space and making it possible to shrink the size of Lu’s printed circuit board, subsequently reducing costs. Regarding claim 20, Lu (see paragraphs REF _Ref216964997 \r \h \* MERGEFORMAT 53 - REF _Ref216964998 \r \h \* MERGEFORMAT 56 above and , e.g. , fig. 2H) shows a connecting element (rightmost 203 directly contacting both 224 and 204B ) connecting the terminal 224 and the interlayer elements 204M, 204N , wherein a distance between a lateral surface of the connecting element and a lateral surface of the terminal increases in a direction toward a lower surface (horizontal surface of 224 closest to 205 ) of the terminal. Claims FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 6 and 1 5-16 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art relied upon." \d "[ 2 ]" Lu/Yang in view of Oshima (JP 2000022315 A) . Regarding claim 6, Lu/Yang shows most aspects of the instant invention (see paragraphs REF _Ref216907223 \r \h \* MERGEFORMAT 23 - REF _Ref216907227 \r \h \* MERGEFORMAT 30 above). Lu (see, e.g. , fig. 2H) further shows that the component 201 has a first terminal 224 , and the first interlayer elements 204M, 204N are arranged in array configuration ( e.g. , a 1D array) and extending along a side of the first terminal of the component in a potentially side view perspective. Accordingly, one of ordinary skill in the art would find it within their understanding and ability to extrapolate Lu’s configuration and apply Lu’s configuration to a top view perspective . Additionally, as “top” and “side” are relative terms, one could interpret the view shown in Lu’s fig. 2H as a “top view perspective”. Lu , however, fails to explicitly specify this arrangement for a top view perspective. Oshima, in the same field of endeavor and in a similar structure to Lu, teaches an electronic device wherein a component 9 has a first terminal 9A , and a first plurality of interlayer elements 2, 11 are arranged in array configuration ( e.g. , a 1D array) and extending along a side of the first terminal of the component in both a side view and a top view perspective (see, e.g. , Oshima: figs. 2-4). Oshima is evidence showing that one of ordinary skill in the art would appreciate that having first interlayer elements arranged in array configuration and extending along a side of a first terminal of a component in a top view perspective would be equivalent to having first interlayer elements arranged in array configuration and extending along a side of a first terminal of a component in a side view and not necessarily top view perspective , and that such differences would result in no unexpected changes in the performance of the electronic device of Lu. That is, the first interlayer element s dispositions of both Lu and Oshima would yield the predictable result of providing a suitable plurality of first interlayer elements for appropriate connection to an external terminal-housing electronic component. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either Lu’s device comprise either first interlayer elements arranged in array configuration and extending along a side of the first terminal of the component in a top view perspective , as taught by Oshima, or first interlayer elements arranged in array configuration and extending along a side of the first terminal of the component in a side view and not necessarily top view perspective , as taught by Lu, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitable plurality of first interlayer elements for appropriate connection to an external terminal-housing electronic component. KSR International Co. v. Teleflex Inc. , 550 U.S.-- ,82 USPQ2d 1385 (2007). Regarding claim 15, Lu /Yang shows most of the instant invention (see paragraphs REF _Ref216964786 \r \h \* MERGEFORMAT 48 - REF _Ref216964902 \r \h \* MERGEFORMAT 52 above). Lu (see, e.g. , fig. 2H) further shows that a first group 204N of the first interlayer elements 204M, 204B, 204N is non-overlapping with the terminal 224 in a potentially side view perspective. Furthermore, Lu (see, e.g. , fig. 2H) shows that an orthogonal projection of Lu’s first group on Lu’s pad (rightmost 203 disposed in 204D ) does not overlap or fall within an orthogonal projection of Lu’s terminal on Lu’s pad, and vice versa. Accordingly, although Lu does not explicitly illustrate a “top view perspective”, one of ordinary skill in the art would understand that Lu’s first group 204N of first interlayer elements 204M, 204B, 204N is non-overlapping with Lu’s terminal 224 in a top view perspective. Additionally, as “top” and “side” are relative terms, one could interpret the view shown in Lu’s fig. 2H as a “top view perspective”. Furthermore, Oshima, in the same field of endeavor and in a similar structure to Lu, teaches an electronic device wherein a first group 2 of first interlayer elements 2, 11 is non-overlapping with a terminal 9A in both a side and a top view perspective (see, e.g. , Oshima: figs. 2-4). Oshima is evidence showing that one of ordinary skill in the art would appreciate that having a first group of first interlayer elements non-overlapping with a terminal in a top view perspective would be equivalent to a first group of first interlayer elements non-overlapping with a terminal in a side view perspective and potentially being not non-overlapping with a terminal in a top view perspective, and that such differences would result in no unexpected changes in the performance of the electronic device of Lu. That is, the first group of first interlayer elements dispositions of both Lu and Oshima would yield the predictable result of providing a suitable first group of a first plurality of interlayer elements for appropriate connection to an external terminal-housing electronic component. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either Lu’s device comprise either a first group of first interlayer elements non-overlapping with the terminal in a top view perspective, as taught by Oshim a , or a first group of first interlayer elements non-overlapping with the terminal in a side view perspective and potentially being not non-overlapping with the terminal in a top view perspective, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitable first group of a first plurality of interlayer elements for appropriate connection to an external terminal-housing electronic component. KSR International Co. v. Teleflex Inc. , 550 U.S.-- ,82 USPQ2d 1385 (2007). Regarding claim 16, Lu /Yang /Oshima shows most aspects of the instant invention (see paragraphs REF _Ref216964786 \r \h \* MERGEFORMAT 48 - REF _Ref216964902 \r \h \* MERGEFORMAT 52 and REF _Ref216965185 \r \h \* MERGEFORMAT 62 - REF _Ref216964961 \r \h \* MERGEFORMAT 64 above). Lu (see, e.g. , fig. 6H) further shows that a second group 204M , 204B of the first interlayer elements 204M , 204B , 204N are disposed below the terminal 224 . Furthermore, Lu (see, e.g. , fig. 6H and pars.0039/ll.4-5 and 0052/ll.25-29) teaches that Lu’s pad (rightmost 203 disposed in 204D ) is electrically connected to components below the pad. Therefore, electric current flowing through Lu’s pad from Lu’s lower electrical components would be distributed to Lu’s first group 204N and second group through Lu’s pad. Accordingly, Lu teaches that the first group is electrically connected to the second group through the pad. Claims FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 1 7-1 9 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art relied upon." \d "[ 2 ]" Oshima in view of Lu. Regarding claim 17, Oshima (see, e.g. , figs. 4 and 6- 8 ) shows most aspects of the instant invention, including an electronic device comprising: a substrate 1 having a pad 6 and an insulating layer 8 exposing an exposed portion of the pad; a component 9 disposed over the substrate and comprising a terminal 9A ; and a plurality of interlayer elements 2, 11 spaced apart from each other and disposed over the exposed portion of the pad to connect the terminal and the pad Although Oshima shows most aspects of the instant invention, including that Oshima’s substrate 1 may be a circuit board (see, e.g. , par.0053), Oshima fails to explicitly specify that Oshima’s substrate may be a chip. Yang, in the same field of endeavor, teaches chips to be suitable substrates for mounting components, pads, and interlayer elements, wherein such a chip is shown to be mounted on a circuit board (see, e.g. , Yang: fig. 6). Yang further teaches that having a component directly installed on a chip which is itself installed on a circuit board reduces the number of devices needed on the circuit board, saving board space and making it possible to shrink the size of the circuit board, which subsequently reduces costs (see, e.g. , Yang: pars.0010 and 0044). Yang is evidence showing that one of ordinary skill in the art would appreciate that an electronic device comprising a chip would be equivalent to an electronic device comprising a circuit board, and that such differences would result in no unexpected changes in the performance of the device of Oshima . That is, the electronic substrates of both Oshima and Yang would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting other electronic components. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Oshima’s electronic device comprise either a chip, as taught by Yang, or a circuit board, as taught by Oshima , because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing an electrically-conductive circuit-hosting support structure for mounting other electronic components. KSR International Co. v. Teleflex Inc. , 550 U.S.-- ,82 USPQ2d 1385 (2007). Furthermore, Yang teaches that at the time of filing the invention one of ordinary skill in the art would find particular incentive to have Oshima’s substrate comprise a chip installed on a circuit board, as taught by Yang, so as to reduce the number of devices needed on Oshima’s circuit board, saving space and making it possible to shrink the size of Oshima’s circuit board, subsequently reducing costs. Regarding claim 18, Oshima (see, e.g. , figs. 2, 4, and 8) shows wherein that, in a top view perspective , the interlayer elements 2, 11 comprises a first interlayer element 11 partially overlapping the terminal 9A and a second interlayer element 2 no n -overlapping with the terminal. Regarding claim 19, Oshima (see, e.g. , figs. 7-8) sh ows that Oshima’s electronic device further comprises a connecting element 10/12 connecting the terminal and the interlayer elements 2, 11 , wherein the connecting element has an irregular shape from a top view perspective. Conclusion Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300 . The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000. /Shamita S. Hanumasagar / Examiner, Art Unit 2814 /WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814