DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan et al. (US9627381B1) in view of Lee et al. (US20060283380A1) and in further view of Shiono et al. (US20060258126A1).
Regarding claim 1, Fig.4 of Balakrishnan teaches a method of forming a semiconductor device including a strain relaxed buffer (SRB) layer 104 (col.3, line18) on a substrate 102 (col.3, line18), comprising:
epitaxially depositing a first silicon germanium layer 104 (col.3, line18) over the substrate 102, wherein the first silicon germanium layer 104 has a first surface that contacts a frontside surface of the substrate 102 and a second surface opposite the first surface, wherein the first silicon germanium layer 104 has a first thickness and a germanium concentration gradient that increases from the first surface to the second surface (col.3, lines 29-33, wherein the Ge concentration of the SRB layer 104 can be gradually increased as the layer is grown (linearly) (rather than incrementally in different layers) until the top portion 106 of the SRB layer 104),
epitaxially depositing the silicon germanium capping layer 106 (col.3, line 32) on the first silicon germanium layer 104,
wherein the silicon germanium capping layer 106 has a backside surface that contacts the second surface of the first silicon germanium layer 104 and a frontside surface opposite the backside surface of the silicon germanium capping layer 106, wherein the silicon germanium capping layer 106 has a second thickness (col.3, lines 39-42, wherein the top portion 106 has a thickness of from about 1 micrometer (μm) to about 3 μm, and ranges therebetween) and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient (col.3, lines 29-33, wherein the Ge concentration of the SRB layer 104 can be gradually increased as the layer is grown (linearly) (rather than incrementally in different layers) until the top portion 106 of the SRB layer 104 is formed having a target Ge concentration), and wherein the first thickness is greater than the second thickness (as it is illustrated in Fig.4 first thickness in greater than second thickness).
Balakrishnan does not teach wherein epitaxially depositing the first silicon germanium layer over the substrate comprises increasing a flow rate of a germanium source gas to form the germanium concentration gradient that increases from the first surface to the second surface.
Fig.4 of Lee teaches wherein in the epitaxial growth process for forming the first silicon germanium layer 102, a flow rate of a germanium source gas provided onto the single crystalline silicon substrate 100 may be continuously increased at a controlled pace over the course of the growth process so as to form the first silicon germanium layer 102 having the desired concentration gradient of germanium (para.0063).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first silicon germanium layer 102 by continuously increasing the flow rate of a germanium source gas, as taught by Lee, in order to form the first silicon germanium layer 102 having the desired concentration gradient of germanium (Lee, [para.0063]).
However, Balakrishnan, as modified by Lee, does not expressly disclose exposing the first silicon germanium layer to a heating or rapid heating process after epitaxially depositing the first silicon germanium layer and before epitaxially depositing a silicon germanium capping layer.
Fig.3A of Shiono teaches wherein heat treatment is performed either during or after formation of the second SiGe layer 3 by epitaxial growth, at a temperature exceeding the epitaxial growth temperature, and irregularities in the surface due to heat treatment are removed by polishing after formation of the second SiGe layer 3, so that a thermal history is imparted to the substrate in advance, and worsening of the surface roughness due to lattice relaxation and dislocation movement is induced in advance. Consequently, when heat treatment is applied during device manufacturing processes or at other times, reoccurrence of worsening of the roughness at surfaces and interfaces can be prevented (para.0131). An Si.sub.1-yGe.sub.y relaxation layer 4, with constant Ge composition ratio, is epitaxially grown on the second SiGe layer 3 after heat treatment.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform heat treatment after the formation of the second SiGe layer 3 and before the formation of relaxation layer 4, as taught by Shiono, so that a thermal history is imparted to the substrate in advance, and worsening of the surface roughness due to lattice relaxation and dislocation movement is induced in advance and consequently, when heat treatment is applied during device manufacturing processes or at other times, reoccurrence of worsening of the roughness at surfaces and interfaces can be prevented (Shiono, [para.0131]).
Regarding claim 2, Balakrishnan further teaches the method of claim 1, wherein the first thickness is in a range from about 2000 nm to about 2500 nm and the germanium concentration gradient increases from 0 at% adjacent to an interface with the substrate to the maximum germanium concentration in a range from about 10 at% to about 15 at%. (col.3, lines 29-37, wherein the Ge concentration of the SRB layer 104 can be gradually increased as the layer is grown (linearly) (rather than incrementally in different layers) until the top portion 106 of the SRB layer 104 is formed having a target Ge concentration and the top portion 106 of the (SiGe) SRB layer 104 has a target Ge concentration of from about 15 atomic percent (at. %) to about 30 at. %, and ranges therebetween).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05(I).
Regarding claim 3, Balakrishnan further teaches the method of claim 2, wherein the second thickness is in a range from about 1000 nm to about 1200 nm and the substantially uniform germanium concentration is substantially equal to, equal to, or greater than the maximum germanium concentration of the first silicon germanium layer. (col.3, lines 39-42, wherein the top portion 106 of the SRB layer 104 preferably has a thickness of from about 1 micrometer (μm) to about 3 μm, and ranges therebetween and wherein portion 106 has a target Ge concentration which is the maximum Ge).
Regarding claim 4, Balakrishnan further teaches the method of claim 1, wherein the germanium concentration gradient increases from a first germanium concentration in a range from about 0 at% to about 2 at% of germanium to a second germanium concentration in a range from about 10 at% to about 15 at%. (col.3, lines 29-37, wherein the Ge concentration of the SRB layer 104 can be gradually increased as the layer is grown (linearly) (rather than incrementally in different layers) until the top portion 106 of the SRB layer 104 is formed having a target Ge concentration and the top portion 106 of the (SiGe) SRB layer 104 has a target Ge concentration of from about 15 atomic percent (at. %) to about 30 at. %, and ranges therebetween).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05(I).
Regarding claim 5, Balakrishnan further teaches the method of claim 1, wherein the substrate comprises silicon 102 (col.3, line 22).
Regarding claim 9, the combination of Balakrishnan, Lee and Shiono teaches the method of claim 1, wherein epitaxially depositing the first silicon germanium layer 102 (Lee, para.0063) over the substrate 100 (Lee, para.0063) comprises increasing a flow rate of a germanium source gas to form the germanium concentration gradient that increases from the first surface to the second surface the heating or rapid heating process comprises a rapid thermal processing anneal, a soak anneal, a spike anneal, a millisecond anneal, or a nanosecond anneal.
Claims 6-8 and 21-27 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan et al. (US9627381B1) in view of Lee et al. (US20060283380A1) and Shiono et al. (US20060258126A1) and in further view of Westhoff et al. (US7332417B2).
Regarding claim 6, the combination of Balakrishnan, Lee and Shiono does not teach method of claim 1, further comprising polishing the silicon germanium capping layer to reduce the second thickness to a third thickness.
Figs. 3 and 4 of Westhoff teach planarizing a surface of the SiGe cap layer by, e.g., chemical mechanical polishing (CMP), and cleaning the resulting planarized surface (col.2, lines 5-6); wherein planarizing may include chemical-mechanical polishing, plasma planarization, wet chemical etching, gas-phase chemical etching [preferably at elevated temperature, e.g., above 900.degree. C., in an ambient including an etch species, e.g., hydrogen chloride (HCl)] (col.3, lines 29-33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the planarization process steps of Westhoff in the teachings of Balakrishnan, as modified by Lee and Shiono, in order to improve the microstructure of semiconductor layers (Westhoff, [col.2, lines 37-38]).
Regarding claim 7, Westhoff further teaches the method of claim 6, wherein after polishing the silicon germanium capping layer, the silicon germanium capping layer has a top surface having a root mean square (RMS) roughness of 5 A or less. (col.11, lines 63-64, wherein after planarization the top surface 32 may have a roughness root-mean-square (RMS) of less than 5 .ANG).
Regarding claim 8, Westhoff further teaches the method of claim 6, further comprising exposing the silicon germanium capping layer to a wet clean process after polishing the silicon germanium capping layer. (wherein planarizing may include chemical-mechanical polishing, plasma planarization, wet chemical etching, gas-phase chemical etching [preferably at elevated temperature, e.g., above 900.degree. C., in an ambient including an etch species, e.g., hydrogen chloride (HCl)] (col.3, lines 29-33).
Regarding claim 21, the combination of Balakrishnan, Lee and Shiono does not teach wherein method of claim 1, further comprising: epitaxially depositing a superlattice structure on the silicon germanium capping layer, the superlattice structure comprising: a plurality of silicon germanium spacer layers; and a plurality of silicon channel layers, wherein the plurality of silicon germanium spacer layers and the plurality of silicon channel layers are disposed in an alternating stacked arrangement and a silicon germanium spacer layer of the plurality of silicon germanium spacer layers contacts the frontside surface of the silicon germanium capping layer.
Fig.11 of Westhoff further teaches wherein second layer 50 disposed over semiconductor layer 16 may be a regrowth layer having a lower portion 150 that includes a superlattice and an upper portion 152 that is substantially free of a superlattice (col.13, lines 55-59).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include layer 50, with a superlattice portion being in contact with layer 16, as taught by Westhoff because the superlattice of the lower portion 100 may help block the effects of an underlying misfit array, thereby enabling the suppression of the reappearance of cross-hatch during subsequent regrowth or post-planarization anneal steps. (Westhoff [col.13, lines 50-54]).
Regarding claim 22, Westhoff further teaches the method of claim 21, wherein each silicon germanium spacer layer has a thickness in a range from about 5 nm to about 7 nm and each silicon channel layer has a thickness in a range from about 7 nm to about 10 nm. (col.3, lines 7-11, wherein the superlattice periodicity may be preferably less than approximately 10 nm).
Regarding claim 23, Westhoff further teaches the method of claim 21, further comprising, before epitaxially depositing the superlattice structure, polishing the silicon germanium capping layer to form a smoothed surface having a root mean square (RMS) roughness of 5A or less, wherein epitaxially depositing the superlattice structure comprises epitaxially depositing the superlattice structure on the smoothed surface. (col.11, lines 63-64, wherein after planarization the top surface 32 may have a roughness root-mean-square (RMS) of less than 5 .ANG).
Regarding claim 24, Westhoff further teaches the method of claim 21, further comprising, after epitaxially depositing the superlattice structure, forming a plurality of trenches through the strain relaxed buffer layer and the superlattice structure. (col.7, lines 52-55, wherein undulation 30 may be formed during deposition of semiconductor layer 16. Undulation 30 has an amplitude A that may be greater than periodicity P.sub.1 of superlattice 24).
Regarding claim 25, Westhoff further teaches the method of claim 21, further comprising, after epitaxially depositing the superlattice structure, forming one or more etch-holes through the strain relaxed buffer layer and the superlattice structure. (col.7, lines 52-55, wherein undulation 30 may be formed during deposition of semiconductor layer 16. Undulation 30 has an amplitude A that may be greater than periodicity P.sub.1 of superlattice 24).
Regarding claim 26, Fig. 5 of Balakrishnan further teaches the method of claim 25, further comprising filling the one or more etch-holes with one or more of a poly material and an oxide material (col.4, lines 42-47, wherein STI generally involves using standard lithography and etching techniques to pattern one or more trenches in the active layer, and then filling the trenches with an insulator (such as an oxide that is generically referred to herein as an STI oxide) forming STI regions, e.g., STI regions 502).
Regarding claim 27, Fig. 5 of Balakrishnan further teaches the method of claim 26, wherein the poly material is a polycrystalline silicon material and the oxide material is silicon oxide (col.4, lines 42-47, wherein STI generally involves using standard lithography and etching techniques to pattern one or more trenches in the active layer, and then filling the trenches with an insulator (such as an oxide that is generically referred to herein as an STI oxide) forming STI regions, e.g., STI regions 502).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Shiono et al. (US20060258126A1) in view of Lee et al. (US20060283380A1) and in further view of Westhoff et al. (US7332417B2).
Regarding claim 20, Figs.3A-3C of Shiono teach a method of forming a semiconductor device, comprising:
forming a strain relaxed buffer layer 2/3 (para.0105) over a substrate 1 (para.0104), comprising:
epitaxially depositing a first silicon germanium layer 2/3 (para.0105) over the substrate 1, wherein the first silicon germanium layer 2/3 has a first thickness and a germanium concentration gradient that increases from a first surface to a second surface of the first silicon germanium layer 2/3 (para.0104-0105, a first SiGe layer 2, which is a gradient composition layer (gradient composition region) in which the Ge composition ratio x increases gradually from 0.3 with a gradient in the film deposition direction (toward the surface) and a second SiGe layer 3, which is a constant-composition layer with Ge composition ratio equal to the final Ge composition ratio of the first SiGe layer (0.3));
exposing the first silicon germanium layer 2/3 to a heating or rapid heating process after epitaxially depositing the first silicon germanium layer 2/3 (para.0110, wherein heat treatment is performed either during or after formation of the second SiGe layer 3 by epitaxial growth, at a temperature exceeding the epitaxial growth temperature, and irregularities in the surface due to heat treatment are removed by polishing after formation of the second SiGe layer 3) and before epitaxially depositing a silicon germanium capping layer 4 (para.0129); and
epitaxially depositing the silicon germanium capping layer 4 on the first silicon germanium layer 2/3, wherein the silicon germanium capping layer 4 has a backside surface that contacts the second surface of the first silicon germanium layer 2/3 and a frontside surface opposite the backside surface of the silicon germanium capping layer 4, wherein the silicon germanium capping layer 4 has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient (para.0129, wherein the Ge composition ratio z of which is the same as the final Ge composition ratio in the second SiGe layer 3 (for example, z=0.3)), and wherein the first thickness is greater than the second thickness (para.0157, wherein the thicknesses of the layers are, for example, 1.5 .mu.m for the second SiGe layer 3, 0.7 to 0.8 .mu.m for the relaxation layer 4);
Shiono does not teach wherein epitaxially depositing the first silicon germanium layer over the substrate comprises increasing a flow rate of a germanium source gas to form the germanium concentration gradient that increases from the first surface to the second surface of the first silicon germanium layer.
Fig.4 of Lee teaches wherein in the epitaxial growth process for forming the first silicon germanium layer 102, a flow rate of a germanium source gas provided onto the single crystalline silicon substrate 100 may be continuously increased at a controlled pace over the course of the growth process so as to form the first silicon germanium layer 102 having the desired concentration gradient of germanium (para.0063).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first silicon germanium layer 102 by continuously increasing the flow rate of a germanium source gas, as taught by Lee, in order to form the first silicon germanium layer 102 having the desired concentration gradient of germanium (Lee, [para.0063]).
However, Shiono, as modified by Lee, does not expressly disclose transferring the substrate to a chemical mechanical polishing (CMP) processing chamber positioned ex-situ to an integrated processing system;
polishing the silicon germanium capping layer to reduce the second thickness to a third thickness in the CMP processing chamber;
transferring the substrate to a wet clean chamber positioned ex- situ to the integrated processing system;
exposing the silicon germanium capping layer to a wet clean process in the wet clean chamber after polishing the silicon germanium capping layer;
transferring the substrate to a dry clean chamber of the integrated processing system;
exposing the substrate to a dry clean process in the dry clean chamber of the integrated processing system using a remote plasma source to generate an etchant species from a fluorine-containing precursor and a hydrogen-containing precursor;
transferring the substrate to an epitaxial deposition chamber of the integrated processing system; and epitaxially depositing a superlattice structure on the strain relaxed buffer layer in the epitaxial deposition chamber of the integrated processing system, wherein the superlattice structure contacts the frontside surface of the silicon germanium capping layer.
Figs. 3 and 4 of Westhoff teach planarizing a surface of the SiGe cap layer by, e.g., chemical mechanical polishing (CMP), and cleaning the resulting planarized surface (col.2, lines 5-6); wherein planarizing may include chemical-mechanical polishing, plasma planarization, wet chemical etching, gas-phase chemical etching [preferably at elevated temperature, e.g., above 900.degree. C., in an ambient including an etch species, e.g., hydrogen chloride (HCl)] (col.3, lines 29-33). Fig.11 of Westhoff further teaches wherein second layer 50 disposed over semiconductor layer 16 may be a regrowth layer having a lower portion 150 that includes a superlattice and an upper portion 152 that is substantially free of a superlattice (col.13, lines 55-59).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the planarization process steps and to include layer 50, with a superlattice portion being in contact with layer 16, as taught by Westhoff because the planarization process steps help to improve the microstructure of semiconductor layers and the superlattice of the lower portion 100 may help block the effects of an underlying misfit array, thereby enabling the suppression of the reappearance of cross-hatch during subsequent regrowth or post-planarization anneal steps. (Westhoff [col.2, lines 37-38/col.13, lines 51-54]).
Claims 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan et al. (US9627381B1) in view of Lee et al. (US20060283380A1) and Shiono et al. (US20060258126A1) and in further view of Ye et al. (US20060115933A1).
Regarding claim 28, the combination of Balakrishnan, Lee and Shiono does not wherein epitaxially depositing the first silicon germanium layer comprises flowing a carbon source gas with the germanium source gas and a silicon source gas to incorporate carbon into the first silicon germanium layer.
Fig.1 of Ye teaches wherein a germanium source and a carbon source may both be added during step 120 into the process chamber with the silicon source and carrier gas to form a silicon-containing compound, such as a silicon germanium carbon material (para.0045).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include carbon gas source and silicon gas source as taught by Ye in the teachings of Balakrishnan, as modified by Lee and Shiono, because the introduction of carbon into silicon epitaxial films may produce beneficial electrical properties such as improving the electrical characteristics of the channel of a metal oxide semiconductor field effect transistor (MOSFET). (Ye, [para.0024]).
Regarding claim 29, Ye further teaches the method of claim 28, wherein the first silicon germanium layer comprises carbon at a concentration in a range from about 200 ppm to about 5 atomic percent. (para.0045, wherein the carbon concentration of an epitaxial layer is in the range from about 200 ppm to about 5 at %).
Regarding claim 30, Ye further teaches the method of claim 28, wherein the first silicon germanium layer has a carbon concentration that increases from the first surface to the second surface (para.0045, wherein the carbon concentration may be graded within an epitaxial layer, preferably graded with a lower carbon concentration in the initial portion of the epitaxial layer than in the final portion of the epitaxial layer).
Conclusion
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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