DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 01/26/2026 have been fully considered but they are not persuasive. Applicant argues the combination of Kang ‘008, Lee ‘248, Tsuji ‘603 fail “as a whole” to be obvious as the “prior art and the invention are not identical and there are one or more differences between the subject matter sought to be patented and the prior art”. Examiner respectfully disagrees when referencing MPEP 2141.02. The cited prior art of record and the instant application are all directed to the same field of endeavor of packaging a semiconductor device. The cited prior art of record and the instant application specifically disclose encapsulations of the semiconductor package. One of ordinary skill in the art would have a reasonable expectation that the encapsulation taught in the prior art of record protect would be effective and finally the prior art of record states provides an advantage (Tsuji ‘603, Col 13, Lines 60-67 through Col 14, Lines 1-4) “the entire circuit board 10 is substantially protected by the sealing resin…it is possible to prevent the invasion of water (moisture) into the semiconductor device…”.
Applicant’s arguments with respect to claim(s) 1-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding Claim 5, the claim recites the limitation “…a conductive trace extending from a second side of the second semiconductor die…”. Examiner notes that Claim 4 cited “…a second conductive pad arranged on a first side of the second semiconductor die…” which is directed to the bottom side of die 140 of the instant application . Referring to Fig 1A of the instant application, Examiner notes that a conductive trace only extends from the bottom of semiconductor die 140. Further, the specification fails to disclose a specific definition for “a first side of the second semiconductor” or a conductive trace extending from the top side of the second semiconductor. It is confusing if the second side of the second semiconductor die is the top of the second semiconductor die or the bottom of the second semiconductor die. For purposed of examination, Examiner has interpreted “a second side of the second semiconductor die…” as “a first side of the second semiconductor die…”.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 9, the claim recites the limitation, “wherein the connectors form an array occupying an area overlapping at least a portion of the recess from a top-view perspective”. Claim 8, upon which claim 9 depends, defines the connectors as “…between the first side of the first substrate and the second substrate. The connecting elements of the instant application between the first side (lower side of 110) the first substrate (110) and the second substrate (120) are the connecting elements (152). The figure 1B of the instant application discloses a top view perspective but that figure, the side view of Fig 1A, which shows connections 152 and 110A/111A as outside region 110R, and the specification fail to clarify “connecting elements (152) form an array occupying an area overlapping at least a portion of the recess from a top-view perspective”. Therefore it is unclear how to interpret the cited limitations of claim 9.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "a second side of the second substrate" in the fourth line of the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 10 is dependent on Claim 7 which cites “a second side of the second substrate”. Therefore it is unclear if this is the same or different second side of the second substrate. For purposes of examination Examiner has interpreted “a second side of the second substrate” as “the second side of the second substrate”.
Further Claim 10 recites the limitation “the second side of the substate”. It is unclear of the substrate references the first or second substrate recited within the claim. For purposes of examination Examiner has interpreted “the second side of the substate” as “the second side of the first substrate”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2010/0102428 A1, hereinafter Lee ‘248) in view of Tsuji et al. (US 5,930,603, hereinafter Tsuji ‘603), in view of the following arguments.
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With respect to Claim 1 Lee ‘428 discloses a semiconductor structure (Figs 1 and 15), comprising:
a first substrate (112, Fig 15, Para [0030]) comprising a first side (113, Fig 15, Para [0030]) and a second side (111,Fig 15, Para [0029]) opposite (disclosed in Fig 15) to the first side (113), wherein the first side (113) includes a recess (114, Fig 15, Para 0030]) recessed from the first side (113);
a first semiconductor die (130, Fig 15, Para [0026]) arranged in the recess (114) and bonded to (Para [0026] discloses 130 bonding to 112 by connection 150) the first side (113) of the first substrate (112), wherein a first space (first space shown in annotated Fig 15 of Lee ‘428, hereinafter FS) is formed within the recess (114) and between (shown in annotated Fig 15 of Lee ‘428) the first substrate (112) and the first semiconductor die (130);
a second semiconductor die (120, Fig 15, Para [0026]) bonded to the second side (111) of the first substrate (112), wherein a second space (second space shown in annotated Fig 15 of Lee ‘428, hereinafter SS) is formed between (shown in annotated Fig 15 of Lee ‘428) the first substrate (112) and the second semiconductor die (120);
a second substrate (140, Fig 15, Para [0029]) electrically bonded (Para [0037] discloses 140 electrically connected to first side 113) to the first side (113) of the first substrate (112), wherein a third space (third space shown in annotated Fig 15 of Lee ‘428, hereinafter TS) is formed between the first substrate (112) and the second substrate (140); and
a molding material (105, Fig 15, Para [0027]) encapsulating (disclosed in Fig 15 and Para [0027]) the first substrate (112), the first semiconductor die (130), and the second semiconductor die (120), wherein the molding material (105) fills the first space (FS), the second space (SS), and the third space (TS)(105 filling FS, SS and TS is disclosed in annotated Fig 15 of Lee ‘248), such that the molding material (105) is filled between the first substrate (112) and the first semiconductor die (130), between the first substrate (112) and the second semiconductor die (120), and between the first substrate (112) and the second substrate (140)(annotated Fig 15 of Lee ‘248 discloses 105 is filled between 112 and 130, is between 112 and 120, is between 112 and 140).
But Lee ‘248 fails to explicitly disclose a molding material encapsulating the second substrate.
Nevertheless, in a related endeavor (Fig 10 of Tsuji ‘603), Tsuji ‘603 teaches molding over substrate and dies.(Fig 10 of Tsuji ‘603 and Col 13, Lines 60 to Col 14, Lines 1-5).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Tsuji ‘603’s teaching of using a molding material over the substrate into Lee ‘428’s semiconductor structure. Lee ‘428 teaches a packaging structure that has an mold layer over the entire package structure. Tsuji ‘603 teaches package structures and ways to overmold those packages to achieve protection of the package. One of ordinary skill in the art would recognize that the overmold provides mechanical and environmental protection to the package. Tsuji ‘603 further teaches an over-molding structure that further encapsulates the entire package, including the sides of the substrate to achieve the well-known advantage of protecting the entire package from moisture. Therefore, the ordinary artisan would have been motivated to further modify Lee ‘428 in the manner set forth above, at least, because as Tsuji ‘603 teaches in Col 14, Lines1-5, over-molding the second circuit board substrate along with the die prevents the invasion of moisture into the device and thereby improves the reliability of the semiconductor device.
As incorporated, the molding structure taught by Tsuji ‘603 would be used to encapsulate the second substrate (140) in Lee ‘428.
With respect to Claim 2 Lee ‘248 as modified by Tsuji ‘603 discloses all limitations of the semiconductor structure of claim 1, and Lee ‘248 discloses further wherein the recess (114) comprises a straight sidewall (straight sidewall of 114 shown in annotated Fig 15 of Lee ‘428, hereinafter SSW), and a bottom surface (bottom surface of 114 shown in annotated Fig 15 of Lee ‘428, hereinafter BS) connected (disclosed in annotated Fig 15 of Lee ‘428) to the straight sidewall (SSW), wherein the first space (FS) is formed within (FS in straight sidewall and bottom of 114 disclosed in Fig 15 and creation is disclosed in Para [0030]) the straight sidewall (SSW) and the bottom surface (BS) of the recess (114) of the first substrate (112).
With respect to Claim 3 Lee ‘248 as modified by Tsuji ‘603 discloses all limitations of the semiconductor structure of claim 1, and Lee ‘248 discloses further comprising a first conductive pad (150, Fig 15, Para 0041]) arranged on a first side (top of 130 as shown in Fig 15) of the first semiconductor die (130) facing (shown in annotated Fig 15 of Lee ‘248) the first side (113) of the first substrate (112), wherein the first conductive pad (150) is disposed within (disclosed in annotated Fig 15 of Lee ‘248) the first space (FS) and is electrically bonded (Para [0041] discloses 150 is electrically bonded to 117 on FS) to the first side (113) of the first substrate (112), such that the first conductive pad (150) is between the first side (top of 130) of the first semiconductor die (130) and the first side (113) of the first substrate (112), wherein the first conductive pad (150) is encapsulated by (150 encapsulated by 105 disclosed in Fig 15) the molding material (105).
With respect to Claim 4 Lee ‘248 as modified by Tsuji ‘603 discloses all limitations of the semiconductor structure of claim 1, and Lee ‘248 further discloses wherein the second semiconductor die (120) comprises a second conductive pad (160, Fig 15, Para [0034]) arranged on a first side (bottom of 120 as shown in Fig 15) of the second semiconductor die (120) facing (shown in Fig 15) the second side (111) of the first substrate (112), wherein the second conductive pad (160) is disposed within (160 within second space shown in annotated Fig 15 of Lee ‘248) the second space (SS) and is electrically bonded (disclosed in Para [0034]) to the second side (111) of the first substrate (112), wherein the second conductive pad (160) is encapsulated by (160 encapsulated by 105 disclosed in Fig 15) the molding material (105).
With respect to Claim 5 Lee ‘248 as modified by Tsuji ‘603 discloses all limitations of the semiconductor structure of claim 1, and Lee ‘248 discloses further comprising a conductive trace (116, Fig 15, Para [0031]) extending from a second side (bottom of 120 as shown in Fig 15) of the second semiconductor die (120)(Note Examiner’s interpretation above of “a second side” as “a first side” to the second side (111) of the first substrate (112) (Fig 15 and Para [0026] discloses 116 extending between bottom of 120 and second side (111) of 112).
With respect to Claim 7 Lee ‘248 as modified by Tsuji ‘603 discloses all limitations of the semiconductor structure of claim 1, further comprising bonding members (170, Fig 15, Para [0035]) arranged on formed and in contact between (Fig 15 and Para [0035] discloses 170 between first side of 113 and top of 140) the first side (113) of the first substrate (112) and a second side (top of 140 as shown in Fig 15) of the second substrate (140) and disposed in the third space (TS)(annotated Fig 15 discloses 170 in third space TS and between 112 and 140) between the first substrate (112) and the second substrate (140), wherein the bonding members (170) are encapsulated by the molding material (105)(Fig 15 discloses 170 encapsulated by 105).
With respect to Claim 8 Lee ‘248 as modified by Tsuji ‘603 discloses all limitations of the semiconductor structure of claim 1, and Lee ‘248 discloses further comprising connectors (170, Fig 15, Para [0035]) between the first side (113) of the first substrate (112) and the second substrate (140)(Fig 15 discloses 150 between first side (113) of 112 and 140), and configured to electrically couple (Fig 15 and Para [0035] disclose 170 electrically connect 112 to 140) the first substrate (112) to the second substrate (140).
With respect to Claim 9 Lee ‘248 as modified by Tsuji ‘603 discloses all limitations of the semiconductor structure of claim 8, wherein the connectors form an array occupying an area overlapping at least a portion of the recess from a top-view perspective.
With respect to Claim 10 Lee ‘248 as modified by Tsuji ‘603 discloses all limitations of the semiconductor structure of claim 7, wherein the first substrate (112) comprises a first conductive line (leftmost 116 as shown in annotated Fig 15 of Lee ‘248, Para [0031]) extending between (Fig 15 discloses leftmost 116 extends between first and second sides of 112) the first side (113) of the first substrate (112) and the second side (111) of the first substrate (112), wherein the first conductive line (leftmost 116) has a first portion (first portion of leftmost 116 as shown in annotated Fig 15 of Lee ‘248) extended (annotated Fig 15 of Lee ‘248 discloses first portion of leftmost 116 extended to first side of 112) to the first side (113) of the first substrate (112) and electrically coupled to (electrical coupling disclosed in Para [0035]) a second side (top of 140)(Note Examiner’s interpretation of “a second side of the second substrate” as “the second side of the second substrate”) of the second substrate (140) opposite to a first side (bottom of 140 as shown in Fig 15) of the second substrate (140), and a second portion (second portion of leftmost 116 as shown in annotated Fig 15 of Lee ‘248) extended to the second side (111) of the substate (112) (Note Examiners’ interpretation of “the substrate” as “the first substrate”) and electrically coupled (Para [0034] discloses 116 electrically connected to 120) to the second semiconductor die (120).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘248 in view of Tsuji ‘603 in further view of Kang et al. (US 2022/0045008 A1, hereinafter Kang ‘008) in view of the following arguments.
With respect to Claim 11 Lee ‘248 as modified by Tsuji ‘603 discloses all limitations of the semiconductor structure of claim 10, and Lee ‘248 further discloses wherein the second substrate (140) comprises a second conductive line extending on the second side of the second substrate and bonded to the first substrate (112) wherein the bonding members (170) are bonded and in contact between (annotated Fig 15 of Lee ‘248 and Para [0035] disclose 170 bonded to and in contact with first portion of the first conductive line) the first portion (first portion of leftmost 116 as shown in annotated Fig 15 of Lee ‘248) of the first conductive line (leftmost 116).
But Lee ‘248 as modified by Tsuji ‘603 fails to explicitly disclose wherein the second substrate comprises a second conductive line extending on the second side of the second substrate and bonded to the first substrate and bonding members are bonded and in contact between the second conductive line.
Nevertheless, in a related endeavor (Fig 3 of Kang ‘008), Kang ‘008 teaches wherein the second substrate (140, Fig 3 of Kang ‘008, Para [0017]) comprises a second conductive line (144, second conductive line disclosed in annotated Fig 3 of Kang ‘008, hereinafter SCL) extending on the second side (top of 140 as disclosed in annotated Fig 3 of Kang ‘008 and in Para [0019], “the lower core pads 117 may be exposed on the bottom surface of the core portion 110”) of the second substrate (140) and bonded to (Para [0019] discloses 140 electrically connected to lower pad 117 of 110) the first substrate (110’, Fig 3 of Kang ‘008) and bonding members (117, Fig 1 of Kang ‘008, Para [117})
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Kang ‘008’s teaching of wherein the second substrate comprises a second conductive line extending on the second side of the second substrate and bonded to the first substrate and bonding members into Lee ‘248 as modified by Tsuji ‘603’s device. Lee ‘248 as modified by Tsuji ‘603 teaches a semiconductor package on package structure but does not explicitly disclose the electrical connection details of the lower substrate. Kang ‘008 teaches a package on package structure and teaches details of the electrical connections in the lower substrate. The ordinary artisan would have been motivated, therefore, to modify Lee ‘248 as modified by Tsuji ‘603 in the manner set forth above, at least, because as Kang ‘008 teaches in Para [0103] using the configurations taught by Kang ‘008 can results in a package with improved electrical characteristics.
As incorporated, the second conductive line (144) extending on the second side (top of 140) as taught by Kang ‘008 would be used as the second conductive line extending on the second sides (top of 140) of Lee ‘248 as modified by Tsuji ‘603.
Therefore Lee ‘248 as modified by Tsuji ‘603 and further modified by Kang ‘008 discloses bonding members (170 of Lee ‘248) are bonded and in contact (as taught by Kang ‘008 and incorporated in Lee ‘248 as modified by Tsuji ‘603 as described above) between the first portion (first portion of leftmost 116 as shown in Fig 15 of Lee ‘248) of the first conductive line (leftmost 116 of Lee ‘248) the second conductive line (SCL of Kang’008 as incorporated in Lee ‘248 as modified by Tsuji ‘603 as described above).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘248 in view of Tsuji ‘603 in view of Kang ‘008 and in further view of Shaul et al. (US 2019/0304936 A1, hereinafter Shaul ‘936), in view of the following arguments.
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With respect to Claim 12 Lee ‘248 as modified by Tsuji ‘603 and further modified by Kang ‘008 discloses all limitations of the semiconductor structure of claim 11, and Lee ‘248 as modified by Tsuji ‘603 and further modified by Kang ‘008 further discloses wherein the first (leftmost 116) and second conductive lines (SCL of Kang ‘008 as incorporated above) include copper (Para [0033] of Kang ‘008 discloses 144 as copper), wherein the first portion (first portion of leftmost 116) of the first conductive line (leftmost 116) is embedded in (leftmost 116 embedded in the first side of 112 is disclosed in annotated Fig 15 of Lee ‘248) the first side (113) of the first substrate (112),
And Kang ‘008 further discloses wherein the second conductive line (SCL of Kang ‘008) is protruded out (SCL protruded out of top of 140 disclosed in annotated Fig 3 of Kang ‘008) of the second side (top side of 140) of the second substrate (140 of Kang ‘008).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the further teachings of Kang ‘008’s second conductive line is protruded out of the second side of the second substrate into Lee ‘248 as modified by Tsuji ‘603 and further modified by Kang ‘008’s device. Lee ‘248 as modified by Tsuji ‘603 and further modified by Kang ‘008 teaches a semiconductor package on package structure on a lower substrate. Kang ‘008 teaches a package on package structure and teaches details of the electrical connections in the lower substrate as it connects to the upper substrate. The ordinary artisan would have been motivated, therefore, to modify Lee ‘248 as modified by Tsuji ‘603 and further modified by Kang ‘008 in the manner set forth above, at least, because as Kang ‘008 teaches in Para [0103] using the configurations taught by Kang ‘008 can results in a package with improved electrical characteristics.
As incorporated, the second conductive line (SCL) is protruded out of the second side (top of 140) of the second substrate (140) of Kang ‘008 would be used as the second conductive line and would protrude on the second side (top of 140) of the second substrate (140) of Lee ‘248 as modified by Tsuji ‘603 and further modified by Kang ‘008.
But Lee ‘248 as modified by Tsuji ‘603 and further modified by Kang ‘008 fails to explicitly disclose the first conductive line include copper
Nevertheless in a related endeavor (Shaul ‘936), Shaul ‘936 teaches the first conductive line (leftmost 134, Fig 1 of Shaul ‘936, Para [0030]) include copper. (134 as copper is disclosed in Para [0030]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Shaul ‘936’s teaching of the first conductive line including copper into Lee ‘248 as modified by Tsuji ‘603 and further modified by Kang ‘008’s device. Lee ‘248 as modified by Tsuji ‘603 and further modified by Kang ‘008 teaches a semiconductor package on package structure on a lower substrate and in Para [0032] discloses the first conductive line is a conductive material but Lee ‘248 as modified by Tsuji ‘603 and further modified by Kang ‘008 does not explicitly state the composition of that conductive material. Shaul ‘936 teaches a second conductive line and discloses that line is copper. The ordinary artisan would have been motivated, therefore, to modify Lee ‘248 as modified by Tsuji ‘603 and further modified by Kang ‘008 in the manner set forth above, because they would recognize the advantage of copper having the well-known advantage of high electrical conductivity and it’s use as a well-known material for creating conductive patterns in a semiconductor package
As incorporated, the copper material used in the first conductive line (leftmost 134) of Shaul ‘936 would be used as the conductive material of the first conductive line (leftmost 116) of Lee ‘248 as modified by Tsuji ‘603 and further modified by Kang ‘008.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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