Prosecution Insights
Last updated: July 05, 2026
Application No. 18/098,827

PACKAGE STRUCTURE

Non-Final OA §102§103
Filed
Jan 19, 2023
Examiner
CHAN, CANDICE
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Semiconductor Engineering Inc.
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
400 granted / 551 resolved
+4.6% vs TC avg
Strong +19% interview lift
Without
With
+19.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
28 currently pending
Career history
606
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
78.8%
+38.8% vs TC avg
§102
11.3%
-28.7% vs TC avg
§112
6.1%
-33.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 551 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office action is in response to the election and amendment filed 21 January 2026. By this amendment, claims 12-13 are amended. Claims 1-20 are currently pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species I, claims 1-20, in the reply filed on 21 January 2026 is acknowledged. Claims 12-20 are directed to non-elected Species II, as set forth in the Restriction Requirement mailed 21 November 2025. Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 21 January 2026. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4 and 7-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2006/0197195 A1 to Diberardino et al. (hereinafter “Diberardino”). Regarding independent claim 1, Diberardino (Fig. 4) discloses a package structure, comprising: a die bonding region 12 (¶ 0015); and a first lead region (including leads on left side of 12) extending along a first direction (direction from top to bottom of Fig. 4), wherein the first direction is along a first edge of the die bonding region 12, and wherein the first lead region comprises a first high density lead region (portions of leads 22 disposed in slot 21) and a first low density lead region (portions of leads 22 furthest from 12), and the first high density lead region overlaps the first low density lead region in the first direction (Fig. 4; ¶ 0019). Regarding claim 2, Diberardino (Fig. 4) discloses the package structure of claim 1, wherein the first high density lead region (portions of leads 22 disposed in slot 21) is closer to an end portion (end portion closest to 12) of the first lead region than the first low density lead region (portions of leads 22 furthest from 12) is (Fig. 4). Regarding claim 3, Diberardino (Fig. 4) discloses the package structure of claim 2, wherein the first high density lead region comprises a plurality of first leads having a first pitch (portions of a subset of leads 22 disposed in slot 21), the first low density lead region comprises a plurality of second leads having a second pitch greater than the first pitch (portions of a different subset of leads 22 furthest from 12) (Fig. 4; ¶ 0019). Regarding claim 4, Diberardino (Figs. 4, 6) discloses the package structure of claim 3, wherein the first lead region (including leads on left side of 12) has an inner region proximal to the die bonding region 12 and an outer region distal from the die bonding region (Fig. 4), and a pitch of the plurality of first leads (portions of a subset of leads 22 disposed in slot 21) in the outer region is substantially equal to a pitch of the plurality of second leads (portions of a different subset of leads 22 furthest from 12) in the outer region (Fig. 4 - 22 have substantially equal pitch in the outer region). Regarding claim 7, Diberardino (Fig. 4) discloses the package structure of claim 1, wherein the first lead region (including leads on left side of 12) further comprises a second high density lead region (portions of a top subset of leads 22 disposed in slot 21) overlapping the first low density lead region (portions of middle subset of leads 22 furthest from 12) in the first direction, and wherein the first low density lead region is in between the first high density lead region (portions of a bottom subset of leads 22 disposed in slot 21) and the second high density lead region (Fig. 4). Regarding claim 8, Diberardino (Fig. 4) discloses the package structure of claim 3, further comprising: a second lead region (including leads on top of side of 12) extending along a second direction (direction from left to right of Fig. 4), wherein the second direction is along a second edge of the die bonding region 12, and the first edge is not parallel to the second edge, and wherein the second lead region comprises a second high density lead region (portions of leads 22 disposed in slot 21) and a second low density lead region (portions of leads 22 furthest from 12), and the second high density lead region overlaps the second low density lead region in the second direction (Fig. 4). Regarding claim 9, Diberardino (Fig. 4) discloses the package structure of claim 3, wherein an amount of the plurality of first leads is greater than or equal to an amount of the plurality of second leads (“plurality of first leads” and “plurality of second leads” can be defined to meet the claimed amount). Regarding independent claim 10, Diberardino (Fig. 4) discloses a package structure, comprising: a die paddle 12 (¶ 0015); a first lead region located at a first side (left side) of the die paddle 12, wherein the first lead region comprises a first inner region (portion of leads 22 closer to 12) and a first outer region (portion of leads 22 furthest from 12), and the first inner region is closer to the die paddle than the first outer region is (Fig. 4); and a plurality of first leads 22 (¶ 0016) disposed within the first lead region and extending from the first outer region to the first inner region (Fig. 4), and wherein a pitch of the plurality of first leads in the first outer region is greater than a pitch of the plurality of first leads in the first inner region (Fig. 4; ¶ 0019). Regarding claim 11, Diberardino (Fig. 4) discloses the package structure of claim 10, further comprising: a second lead region located at a second side (right side), different from the first side (left side), of the die paddle 12, wherein the second lead region comprises a second inner region (portion of leads closer to 12) and a second outer region (portion of leads 22 furthest from 12), and the second inner region is closer to the die paddle than the second outer region is (Fig. 4); a plurality of second leads 22 (right side) disposed within the second lead region and extending from the second outer region to the second inner region (Fig. 4), and wherein a pitch of the plurality of second leads in the second outer region is greater than a pitch of the plurality of second leads in the second inner region (Fig. 4; ¶ 0019). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Diberardino. Regarding claim 5, Diberardino discloses the package structure of claim 4, however fails to expressly disclose wherein a pitch of the plurality of first leads in the inner region is less than a pitch of the plurality of second leads in the inner region. Diberardino does disclose varying the pitch of leads on the inner and outer ends for the purpose of meeting design rules and to optimize device performance (¶¶ 0019-22). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a pitch of the plurality of first leads in the inner region less than a pitch of the plurality of second leads in the inner region (i.e., tapering the plurality of first leads in the inner region; ¶ 0021) for the purpose of adjusting the impedance of the lead fingers (¶ 0021). Regarding claim 6, Diberardino discloses the package structure of claim 1, however fails to expressly disclose wherein the first low density lead region is closer to a center of the first edge of the die bonding region than the first high density lead region is. Diberardino does disclose that there may be any number of slots at any position(s) on the edge of 12 (¶ 0015; see Fig. 4 - slot having a high density lead region disposed therein) and the pitch of leads may be varied in different areas for the purpose of meeting design rules and to optimize device performance (¶¶ 0019-22). Thus, in view of the teachings of Diberardino, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the first low density lead region closer to a center of the first edge of the die bonding region than the first high density lead region as a matter of design choice. Conclusion The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2006/0017142 A1 to Jang et al. disclosing a semiconductor device package with different pitch between contacts; US 2002/0121682 A1 to Azcarate et al. disclosing a strapless lead frame. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. CANDICE Y. CHAN Examiner Art Unit 2813 21 March 2026 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Jan 19, 2023
Application Filed
Apr 03, 2026
Non-Final Rejection mailed — §102, §103
May 13, 2026
Interview Requested
May 19, 2026
Examiner Interview Summary
May 19, 2026
Applicant Interview (Telephonic)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12666994
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
3y 0m to grant Granted Jun 23, 2026
Patent 12660678
EMBEDDED PACKAGE WITH DELAMINATION MITIGATION
4y 9m to grant Granted Jun 16, 2026
Patent 12660641
SEMICONDUCTOR DEVICES HAVING WETTABLE FLANKS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
3y 9m to grant Granted Jun 16, 2026
Patent 12641780
THREE-DIMENSIONAL FLASH MEMORY DEVICE AND METHOD FOR FORMING THE SAME
3y 4m to grant Granted May 26, 2026
Patent 12635188
SEMICONDUCTOR DEVICE INCLUDING MEMORY STRUCTURE ARRANGED ADJACENT TO PLANAR GATE STRUCTURE
3y 8m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
92%
With Interview (+19.2%)
3y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 551 resolved cases by this examiner. Grant probability derived from career allowance rate.

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