DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/04/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 10-14, 16, 18, and 21-27 are rejected under 35 U.S.C. 103 as being unpatentable over US 2004/0124461 to Gajda in view of Hiyoshi (US 2013/0065384), Matsunaga et al. (US 2023/0253458, hereinafter Matsunaga), Ikeda et al. (US 2016/0260608, hereinafter Ikeda), and Yamazaki (US Patent No. 7,659,571) (the reference US 2020/0020762 by Frank is presented as evidence).
With respect to claims 8 and 16, Gajda discloses a method of forming a structure for a field-effect transistor (e.g., silicon carbide trench-gate MOSFET) (Gajda, Figs. 1-2, 3-5, 8-10, ¶0001, ¶0006-¶0027, ¶0034-¶0050, ¶0066-¶0071, ¶0082), the method comprising:
forming a doped region (e.g., p-type channel region 15) (Gajda, Figs. 3-4, 8, ¶0045-¶0046, ¶0054, ¶0061-¶0062, ¶0066-¶0069) in a semiconductor substrate (100) adjacent to a top surface of the semiconductor substrate, wherein the semiconductor substrate (100) comprises a wide bandgap semiconductor material (e.g., silicon carbide (SiC)) Gajda, Figs. 3-4, 8, ¶0082);
forming a hardmask (51/52 or 510/520) (Gajda, Figs. 3-6, 8-9, ¶0061-¶0062, ¶0066-¶0069) on the top surface of the semiconductor substrate (100);
forming a trench (20) (Gajda, Figs. 3-4, 8, ¶0045-¶0046, ¶0069) in the semiconductor substrate (100), wherein the trench (20) extends through the hardmask (510/520) and the doped region (e.g., the p-type channel layer 15 is formed before forming trench gate) (Gajda, Figs. 3-4, 8, ¶0054) into the semiconductor substrate (100) beneath the doped region (15);
forming a gate structure (17/11) (Gajda, Figs. 6, 8-9, ¶0062, ¶0069-¶0070) including a gate conductor layer (11), wherein the gate conductor layer (11) has a first portion (11z) disposed above the top surface of the semiconductor substrate (100) and a second portion (11a) disposed inside the trench (20) below the top surface of the semiconductor substrate (100) (as claimed in claim 8).
Further, Gajda does not specifically disclose the method (1) wherein the hardmask comprises a material having a melting point that is greater than or equal to 2000°C (as claimed in claim 8); wherein the material comprises aluminum nitride (as claimed in claim 16); (2) activating a dopant of the doped region at a temperature of 1600°C to 1900°C with the hardmask on the top surface of the semiconductor substrate and after forming the trench (as claimed in claim 8); and (3) removing the hardmask after forming the gate structure to reveal the top surface of the semiconductor substrate over the doped region (as claimed in claim 8).
Regarding (1), Hiyoshi teaches forming a silicon carbide semiconductor device (Hiyoshi, Figs. 1-12, ¶0008-¶0015, ¶0051-¶0078) comprising a gate trench formed by etching portion of silicon carbide layer by using patterned mask layer (17), wherein the mask layer (17) (Hiyoshi, Figs. 4-6, ¶0061-¶0066) includes one or more materials from silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, and gallium nitride, to increase etching selectivity of SiC with respect to material for mask layer (17) (Hiyoshi, Figs. 4-6, ¶0066) to suppress consumption of the mask material during thermal etching, and thus to provide a high-quality semiconductor device having stable characteristics.
Further, it is known in the art (e.g., as evidenced by Frank, ¶0058) that a melting point of aluminum nitride (melting point 2200°C) and aluminum oxide (melting point 2070°C) is greater than 2000°C.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gajda by forming a hard mask layer including aluminum oxide and/or aluminum nitride for etching SiC material as taught by Hiyoshi to have the method, wherein the hardmask comprises a material having a melting point that is greater than or equal to 2000°C (as claimed in claim 8); wherein the material comprises aluminum nitride (as claimed in claim 16), in order to increase etching selectivity of SiC with respect to material for mask layer to suppress consumption of the mask material during thermal etching, and thus to provide a high-quality semiconductor device having stable characteristics (Hiyoshi, ¶0008-¶0015, ¶0066).
Regarding (2), Matsunaga teaches forming a silicon carbide semiconductor device comprising a trench (5) (Matsunaga, Fig. 6, ¶0044-¶0045, ¶0048) extending through the doped region (e.g., the implanted base region 3); and activating a dopant of the doped region (e.g., activation annealing for activation all regions formed by ion implantation is performed at a temperature of about 1700°C to implement an activation process of the p-type base region 3) at a temperature of about 1700°C (which is in the claimed range of 1600°C to 1900°C) after forming the trench (5).
Further, Ikeda teaches forming a silicon carbide semiconductor device (Ikeda, Fig. 9, ¶0008, ¶0020, ¶0026-¶0029, ¶0038) comprising a protective mask (62) including SiC material with a melting point equal or higher than 2000°C to protect the substrate during heating at a high temperature equal to or higher than 1700°C to activate the impurities after forming the gate trench, to provide MOSFET having a high withstand voltage.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gajda by performing activation annealing at specific high temperature (e.g., about 1700 °C) after forming the trench as taught by Matsunaga, and forming a hard mask including silicon carbide material having a high melting point as a protective mask during high temperature annealing (e.g., about 1700 °C) as taught by Ikeda to have the method comprising: activating a dopant of the doped region at a temperature of 1600°C to 1900°C with the hardmask on the top surface of the semiconductor substrate and after forming the trench (as claimed in claim 8), in order to provide a silicon carbide semiconductor device having improved performance characteristics (e.g., reduced On-state resistance, increased channel mobility, and suppressed channel leakage); and to provide a high heat resistance mask to withstand high implant and activation temperatures, and thus to obtain MOSFET having a high withstand voltage (Matsunaga, ¶0002-¶0003, ¶0032, ¶0045, ¶0048, ¶0056-¶0057; Ikeda, ¶0008, ¶0020, ¶0026-¶0029).
Regarding (3), Yamazaki teaches a method of forming a trench-gate-type transistor (Yamazaki, Figs. 12, 13A-13B, 14A-14C, Col. 1, lines 6-9; Col. 3, lines 50-67; Col. 8, lines 58-67; Col. 9, lines 1-31) comprising forming a gate electrode structure (109) (Yamazaki, Figs. 12, 13A-13B, 14A-14C, Col. 8, lines 58-67; Col. 9, lines 1-31) using a hardmask (103) in self-aligning with the gate trench (104) in the semiconductor substrate (101), to prevent misalignment of the gate electrode structure (109), wherein the hardmask (103) is removed after forming the gate structure (106/107) to reveal the top surface of the semiconductor substrate (101).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gajda by forming a gate electrode structure using a hardmask in self-aligning with the gate trench in the semiconductor substrate as taught by Yamazaki, wherein the semiconductor substrate includes a doped region formed before forming a trench-gate as taught by Gajda to have the method comprising: removing the hardmask after forming the gate structure to reveal the top surface of the semiconductor substrate over the doped region (as claimed in claim 8), in order to provide improved method of forming a trench-gate-type transistor by preventing misalignment of the gate electrode structure; and to provide silicide gate structure for reducing gate resistance (Yamazaki, Col. 1, lines 6-9; Col. 9, lines 24-31; Gajda, ¶0006-¶0027).
Regarding claim 10, Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki discloses the method of claim 8. Further, Gajda discloses the method further comprising: forming a silicide layer (11b) (Gajda, Figs. 1-2, 7, 9-10, ¶0062-¶0063, ¶0071, ¶0059) on the first portion (11z) of the gate conductor layer (11), but does not specifically disclose wherein the hardmask is removed after forming the silicide layer.
However, Yamazaki teaches a method of forming a trench-gate-type transistor comprising the silicide layer (107a), wherein the hardmask (103) (Yamazaki, Fig. 14C, Col. 9, lines 20-26) is removed after forming the silicide layer (107a), to form the gate electrode structure in self-aligning with the gate trench (104) to prevent misalignment of the gate electrode structure (109).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gajda/Hiyoshi/Matsunaga/Ikeda/Yamazaki by forming a gate electrode structure using a hardmask in self-aligning with the gate trench in the semiconductor substrate as taught by Yamazaki to have the method, wherein the hardmask is removed after forming the silicide layer, in order to provide improved method of forming a trench-gate-type transistor by preventing misalignment of the gate electrode structure (Yamazaki, Col. 1, lines 6-9; Col. 9, lines 20-31).
Regarding claim 11, Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki discloses the method of claim 8. Further, Gajda discloses the method further comprising: recessing the gate conductor layer (e.g., gate layer 11 is etched back and it is stopped when the gate layer 11 is lower or level with an upper surface of the mask 51/52 or 520) (Gajda, Figs. 6-7, 9, ¶0062-¶0063, ¶0070) relative to a top surface of the hardmask (51/52 or 510/520).
Regarding claim 12, Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki discloses the method of claim 11. Further, Gajda discloses the method wherein the gate conductor layer (11a/11z) (Gajda, Figs. 6-7, ¶0062-¶0063) has a top surface (e.g., after etch-back of the gate layer 11) disposed between the top surface of the hardmask (51/52) and the top surface of the semiconductor substrate (100).
Regarding claim 13, Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki discloses the method of claim 12. Further, Gajda discloses the method further comprising: forming a silicide layer (11b) (Gajda, Figs. 1-2, 7, ¶0062-¶0063) on the gate conductor layer (11); and forming a dielectric layer (e.g., 18b) inside a portion of the trench (20) over the silicide layer (e.g., oxidizing silicide layer 11b) (Gajda, Figs. 1-2, 7, ¶0073-¶0075) and the gate conductor layer (11a), but does not specifically disclose wherein the hardmask is removed after forming the silicide layer and the dielectric layer.
However, Yamazaki teaches a method of forming a trench-gate-type transistor comprising the silicide layer (107a), wherein the hardmask (103) (Yamazaki, Fig. 14C, Col. 9, lines 20-26) is removed after forming the silicide layer (107a), to form the gate electrode structure in self-aligning with the gate trench (104) to prevent misalignment of the gate electrode structure (109).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gajda/Hiyoshi/Matsunaga/Ikeda/Yamazaki by forming a gate electrode structure using a hardmask in self-aligning with the gate trench in the semiconductor substrate as taught by Yamazaki, wherein a portion of the silicide layer is oxidized as taught by Gajda to have the method, wherein the hardmask is removed after forming the silicide layer and the dielectric layer, in order to provide improved method of forming a trench-gate-type transistor by preventing misalignment of the gate electrode structure; and to provide silicide gate structure for reducing gate resistance (Yamazaki, Col. 1, lines 6-9; Col. 9, lines 20-31; Gajda, ¶0006-¶0027).
Regarding claim 14, Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki discloses the method of claim 11. Further, Gajda discloses the method further comprising: forming a dielectric layer (e.g., 18b, oxidized silicide layer 11b) (Gajda, Figs. 1-2, 7, ¶0073-¶0075) inside a portion of the trench (20) over the gate conductor layer (11a/11b).
Regarding claim 18, Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki discloses the method of claim 8. Further, Gajda discloses the method wherein the material (510/520) comprises silicon oxide (520a) and silicon nitride (510) (Gajda, Figs. 8-10, ¶0066-¶0067), but does not specifically disclose the method wherein the material comprises aluminum oxide and either aluminum nitride or polycrystalline silicon carbide.
However, Hiyoshi teaches forming a silicon carbide semiconductor device (Hiyoshi, Figs. 1-12, ¶0008-¶0015, ¶0051-¶0078) comprising a gate trench formed by etching portion of silicon carbide layer by using patterned mask layer (17), wherein the mask layer (17) (Hiyoshi, Figs. 4-6, ¶0061-¶0066) includes one or more materials from silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, and gallium nitride, to increase etching selectivity of SiC with respect to material for mask layer (17) (Hiyoshi, Figs. 4-6, ¶0066) to suppress consumption of the mask material during thermal etching, and thus to provide a high-quality semiconductor device having stable characteristics.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gajda/Hiyoshi/Matsunaga/Ikeda/Yamazaki by forming a hard mask layer including aluminum oxide and aluminum nitride for etching SiC material as taught by Hiyoshi to have the method wherein the material comprises aluminum oxide and aluminum nitride, in order to increase etching selectivity of SiC with respect to material for mask layer to suppress consumption of the mask material during thermal etching, and thus to provide a high-quality semiconductor device having stable characteristics (Hiyoshi, ¶0008-¶0015, ¶0066).
Regarding claim 21, Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki discloses the method of claim 8. Further, Gajda does not specifically disclose the method wherein forming the doped region in the semiconductor substrate adjacent to the top surface of the semiconductor substrate comprises: introducing the dopant by ion implantation into the semiconductor substrate to form the doped region.
However, Matsunaga teaches forming the doped region (e.g., p-type base region 3) (Matsunaga, Fig. 6, ¶0044-¶0045) in the semiconductor substrate (e.g., silicon carbide substrate 1) adjacent to the top surface of the semiconductor substrate by introducing the dopant (e.g., p-type impurity, such as aluminum) by ion implantation into the semiconductor layer to form the doped region (3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gajda/Hiyoshi/Matsunaga/Ikeda/Yamazaki by performing a p-type doped region by using a conventional ion implantation method as taught by Matsunaga to have the method wherein forming the doped region in the semiconductor substrate adjacent to the top surface of the semiconductor substrate comprises: introducing the dopant by ion implantation into the semiconductor substrate to form the doped region, in order to provide a silicon carbide semiconductor device having improved performance characteristics (e.g., reduced On-state resistance, increased channel mobility, and suppressed channel leakage) (Matsunaga, ¶0002-¶0003, ¶0032, ¶0045, ¶0048, ¶0056-¶0057).
Regarding claims 22 and 23, Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki discloses the method of claim 21 (claim 8). Further, Gajda does not specifically disclose the method wherein activating the dopant of the doped region at the temperature of 1600°C to 1900°C with the hardmask on the top surface of the semiconductor substrate comprises: performing a high-temperature anneal at the temperature of 1600°C to 1900°C (as claimed in claims 22 and 23).
However, Matsunaga teaches the method, wherein activating a dopant of the doped region (e.g., activation annealing for activation all regions formed by ion implantation is performed at a temperature of about 1700°C to implement an activation process of the p-type base region 3) (Matsunaga, Fig. 6, ¶0044-¶0045, ¶0048) is performed at a temperature of about 1700°C which is in the claimed range of 1600°C to 1900°C. Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
Further, Ikeda teaches using a protective mask (62) (Ikeda, Fig. 9, ¶0026-¶0029, ¶0038) including SiC material with a melting point equal or higher than 2000°C to protect the substrate during heating at a high temperature equal to or higher than 1700°C to activate the impurities after forming the gate trench, to provide MOSFET having a high withstand voltage.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gajda/Hiyoshi/Matsunaga/Ikeda/Yamazaki by performing activation annealing for activation all regions formed by ion implantation as taught by Matsunaga, and using a hard mask including silicon carbide material having a high melting point as a protective mask during high temperature annealing (e.g., about 1700 °C) as taught by Ikeda to have the method wherein activating the dopant of the doped region at the temperature of 1600°C to 1900°C with the hardmask on the top surface of the semiconductor substrate comprises: performing a high-temperature anneal at the temperature of 1600°C to 1900°C (as claimed in claims 22 and 23), in order to provide a silicon carbide semiconductor device having improved performance characteristics (e.g., reduced On-state resistance, increased channel mobility, and suppressed channel leakage); and to provide a high heat resistance mask to withstand high implant and activation temperatures (Matsunaga, ¶0002-¶0003, ¶0032, ¶0045, ¶0048, ¶0056-¶0057; Ikeda, ¶0008, ¶0020, ¶0026-¶0029).
Regarding claims 24 and 25, Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki discloses the method of claim 23 (claim 24). Further, Gajda does not specifically disclose the method further comprising: applying a carbon capping layer before performing the high-temperature anneal.
However, Ikeda teaches using a protective layer (60) (Ikeda, Fig. 9, ¶0026-¶0029, ¶0031, ¶0038) consisting of carbon material to suppress sublimation of Si from the front surface of the SC substrate, and to provide a highly heat-resistant material to protect the substrate during heating at a high temperature equal to or higher than 1700°C to activate the impurities after forming the gate trench, to provide MOSFET having a high withstand voltage.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gajda/Hiyoshi/Matsunaga/Ikeda/Yamazaki by forming a protective layer including carbon material before performing high temperature annealing (e.g., about 1700 °C) as taught by Ikeda to have the method further comprising: applying a carbon capping layer before performing the high-temperature anneal (as claimed in claims 24 and 25), in order to suppress sublimation of Si from the front surface of the SC substrate, and to provide a highly heat-resistant material to protect the substrate during heating at a high temperature equal to or higher than 1700°C to activate the impurities after forming the gate trench, to provide MOSFET having a high withstand voltage (Ikeda, ¶0008, ¶0020, ¶0026-¶0029, ¶0031, ¶0038).
Regarding claim 26, Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki discloses the method of claim 10. Further, Gajda discloses the method wherein the silicide layer (11b) (Gajda, Figs. 1-2, 7, 9-10, ¶0062-¶0063, ¶0071) and the trench (20) have equal width dimensions (e.g., when the gate oxide is formed by thermal oxidation of the sidewalls of the trench).
Regarding claim 27, Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki discloses the method of claim 13. Further, Gajda discloses the method wherein the silicide layer (e.g., a bottom portion of the silicide layer 11b, as in Fig. 7) (Gajda, Figs. 1-2, 7, ¶0062-¶0063, ¶0073-¶0075) and the trench (20) have equal width dimensions (e.g., when the gate oxide is formed by thermal oxidation of the sidewalls of the trench).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over US 2004/0124461 to Gajda in view of Hiyoshi (US 2013/0065384), Matsunaga (US 2023/0253458), Ikeda (US 2016/0260608), and Yamazaki (US Patent No. 7,659,571) as applied to claim 8, and further in view of Moore et al. (US Patent No. 5,641,695, hereinafter Moore).
Regarding claim 17, Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki discloses the method of claim 8. Further, Gajda does not specifically disclose the method wherein the material comprises polycrystalline silicon carbide.
However, Ikeda teaches forming a silicon carbide semiconductor device (Ikeda, Fig. 9, ¶0008, ¶0020, ¶0026-¶0029) comprising a protective mask (62) including SiC material with a melting point equal or higher than 2000°C to protect the substrate during heating at a high temperature to activate the impurities formed at the bottom of the gate trench, to provide MOSFET having a high withstand voltage.
Further, Moore teaches forming polycrystalline silicon carbide mask (14) (Moore, Figs. 1-3, Col. 1 lines 47-67; Col. 2, lines 1-43) as an etch mask and ion implantation mask to withstand high implant and activation temperatures.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gajda/Hiyoshi/Matsunaga/Ikeda/Yamazaki by forming a hard mask including silicon carbide material having a high melting point as taught by Ikeda, wherein the silicon carbide is polycrystalline silicon carbide mask material as taught by Moore to have the method wherein the material comprises polycrystalline silicon carbide, in order to provide a high heat resistance mask to withstand high implant and activation temperatures, and thus to obtain MOSFET having a high withstand voltage (Moore, Col. 1 lines 59-67; Col. 2, lines 1-5; lines 38-43; Ikeda, ¶0008, ¶0020, ¶0026-¶0029).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over US 2004/0124461 to Gajda in view of Hiyoshi (US 2013/0065384), Matsunaga (US 2023/0253458), Ikeda (US 2016/0260608), and Yamazaki (US Patent No. 7,659,571) as applied to claim 8, and further in view of Lee et al. (US 2016/0293441, hereinafter Lee) and Moore (US Patent No. 5,641,695).
Regarding claim 19, Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki discloses the method of claim 8. Further, Gajda discloses the method wherein the hardmask (510/520) includes a first layer (e.g., silicon nitride 510) (Gajda, Figs. 8-10, ¶0066-¶0067) and a second layer (e.g., silicon oxide 520) that is disposed on the first layer (510), but does not specifically disclose the method wherein the first layer comprises aluminum nitride, and the second layer comprises polycrystalline silicon carbide.
However, Lee teaches forming a mask (104) (Lee, Figs. 1A-1D, ¶0064-¶0078) for patterning semiconductor layer (e.g., 102), wherein the mask (104) including a stack of antireflection layer (ARC) on a layer including a carbon, to increase accuracy of transferring pattern form the photoresist layer to the underlying layer; specifically, the hard mask (104) includes aluminum nitride and silicon carbide.
Further, Moore teaches forming polycrystalline silicon carbide mask (14) (Moore, Figs. 1-3, Col. 1 lines 47-67; Col. 2, lines 1-43) as an etch mask and ion implantation mask to withstand high implant and activation temperatures.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gajda/Hiyoshi/Matsunaga/Ikeda/Yamazaki by forming a hard mask including aluminum nitride and silicon carbide as taught by Lee, wherein the silicon carbide is polycrystalline silicon carbide mask material as taught by Moore to have the method wherein the first layer comprises aluminum nitride, and the second layer comprises polycrystalline silicon carbide, in order to increase accuracy of transferring pattern form the photoresist layer to the underlying layer, and to provide a high heat resistance mask to withstand high implant and activation temperatures (Lee, ¶0061, ¶0076; Moore, Col. 1 lines 59-67; Col. 2, lines 1-5; lines 38-43).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US 2004/0124461 to Gajda in view of Hiyoshi (US 2013/0065384), Matsunaga (US 2023/0253458), and Ikeda (US 2016/0260608) (the reference US 2020/0020762 by Frank is presented as evidence).
With respect to claim 20, Gajda discloses a method of forming a structure for a field-effect transistor (e.g., silicon carbide trench-gate MOSFET) (Gajda, Figs. 1-2, 3-5, 8-10, ¶0001, ¶0006-¶0027, ¶0034-¶0050, ¶0066-¶0071, ¶0082), the method comprising:
forming a doped region (e.g., p-type channel region 15) (Gajda, Figs. 3-4, 8, ¶0045-¶0046, ¶0054, ¶0061-¶0062, ¶0066-¶0069) in a semiconductor substrate (100) adjacent to a top surface of the semiconductor substrate, wherein the semiconductor substrate (100) comprises a wide bandgap semiconductor material (e.g., silicon carbide (SiC)) Gajda, Figs. 3-4, 8, ¶0082);
forming a hardmask (51/52 or 510/520) (Gajda, Figs. 3-6, 8-9, ¶0061-¶0062, ¶0066-¶0069) on the top surface of the semiconductor substrate (100);
forming a trench (20) (Gajda, Figs. 3-4, 8, ¶0045-¶0046, ¶0069) in the semiconductor substrate (100), wherein the trench (20) extends through the hardmask (510/520) and the doped region (e.g., the p-type channel layer 15 is formed before forming trench gate) (Gajda, Figs. 3-4, 8, ¶0054) into the semiconductor substrate (100) beneath the doped region (15);
forming a gate structure (17/11) (Gajda, Figs. 6, 8-9, ¶0062, ¶0069-¶0070) including a gate conductor layer (11), wherein the gate conductor layer (11) has a first portion (11z) disposed above the top surface of the semiconductor substrate (100) and a second portion (11a) disposed inside the trench (20) below the top surface of the semiconductor substrate (100);
removing the hardmask (e.g., 52) (Gajda, Figs. 1-2, 7, ¶0064, ¶0073, ¶0075) after forming the gate structure (11); and
forming a dielectric layer (18b) by an oxidation process on the gate conductor layer (11b) after removing the hardmask (52) (Gajda, Figs. 1-2, 7, ¶0064, ¶0073, ¶0075).
Further, Gajda does not specifically disclose the method (1) wherein the hardmask comprises a material having a melting point that is greater than or equal to 2000°C; (2) activating a dopant of the doped region at a temperature of 1600°C to 1900°C with the hardmask on the top surface of the semiconductor substrate and after forming the trench.
Regarding (1), Hiyoshi teaches forming a silicon carbide semiconductor device (Hiyoshi, Figs. 1-12, ¶0008-¶0015, ¶0051-¶0078) comprising a gate trench formed by etching portion of silicon carbide layer by using patterned mask layer (17), wherein the mask layer (17) (Hiyoshi, Figs. 4-6, ¶0061-¶0066) includes one or more materials from silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, and gallium nitride, to increase etching selectivity of SiC with respect to material for mask layer (17) (Hiyoshi, Figs. 4-6, ¶0066) to suppress consumption of the mask material during thermal etching, and thus to provide a high-quality semiconductor device having stable characteristics.
Further, it is known in the art (e.g., as evidenced by Frank, ¶0058) that a melting point of aluminum nitride (melting point 2200°C) and aluminum oxide (melting point 2070°C) is greater than 2000°C.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gajda by forming a hard mask layer including aluminum oxide and/or aluminum nitride for etching SiC material as taught by Hiyoshi to have the method, wherein the hardmask comprises a material having a melting point that is greater than or equal to 2000°C, in order to increase etching selectivity of SiC with respect to material for mask layer to suppress consumption of the mask material during thermal etching, and thus to provide a high-quality semiconductor device having stable characteristics (Hiyoshi, ¶0008-¶0015, ¶0066).
Regarding (2), Matsunaga teaches forming a silicon carbide semiconductor device comprising a trench (5) (Matsunaga, Fig. 6, ¶0044-¶0045, ¶0048) extending through the doped region (e.g., the implanted base region 3); and activating a dopant of the doped region (e.g., activation annealing for activation all regions formed by ion implantation is performed at a temperature of about 1700°C to implement an activation process of the p-type base region 3) at a temperature of about 1700°C (which is in the claimed range of 1600°C to 1900°C) after forming the trench (5).
Further, Ikeda teaches forming a silicon carbide semiconductor device (Ikeda, Fig. 9, ¶0008, ¶0020, ¶0026-¶0029, ¶0038) comprising a protective mask (62) including SiC material with a melting point equal or higher than 2000°C to protect the substrate during heating at a high temperature equal to or higher than 1700°C to activate the impurities after forming the gate trench, to provide MOSFET having a high withstand voltage.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gajda by performing activation annealing at specific high temperature (e.g., about 1700 °C) after forming the trench as taught by Matsunaga, and forming a hard mask including silicon carbide material having a high melting point as a protective mask during high temperature annealing (e.g., about 1700 °C) as taught by Ikeda to have the method comprising: activating a dopant of the doped region at a temperature of 1600°C to 1900°C with the hardmask on the top surface of the semiconductor substrate and after forming the trench, in order to provide a silicon carbide semiconductor device having improved performance characteristics (e.g., reduced On-state resistance, increased channel mobility, and suppressed channel leakage); and to provide a high heat resistance mask to withstand high implant and activation temperatures, and thus to obtain MOSFET having a high withstand voltage (Matsunaga, ¶0002-¶0003, ¶0032, ¶0045, ¶0048, ¶0056-¶0057; Ikeda, ¶0008, ¶0020, ¶0026-¶0029).
Claims 28 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over US 2004/0124461 to Gajda in view of Hiyoshi (US 2013/0065384), Matsunaga (US 2023/0253458), Ikeda (US 2016/0260608), and Yamazaki (US Patent No. 7,659,571) as applied to claim 27 (claim 14), and further in view of Hsu (US 2006/0197148).
Regarding claims 28 and 29, Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki discloses the method of claim 27 (claim 14). Further, Gajda does not specifically disclose the method wherein the dielectric layer and the trench have equal width dimensions (as claimed in claims 28 and 29).
However, Hsu teaches a method of forming a trench power MOSFET, wherein a silicide layer (222) (Hsu, Figs. 2I-2K, ¶0041, ¶0048-¶0050, ¶0056, ¶0056) is formed on the gate conductor layer (210a) inside the trench (206), gat oxide (208) is formed by thermal oxidation of surfaces of the trench (206), and a dielectric layer (224) is formed inside a portion of the trench over the silicide layer (222) and the gate conductor layer (110a), wherein the silicide layer (222) and the trench (206) have equal width dimensions, and wherein the dielectric layer (224) and the trench (206) have equal width dimensions, to provide the MOSFET structure with reduce gate resistance, and improved on-off response rate.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gajda/Hiyoshi/Matsunaga/Ikeda/Yamazaki by forming a gate dielectric layer having the same width as the gate trench as taught by Hsu to have the method, wherein the dielectric layer and the trench have equal width dimensions (as claimed in claims 28 and 29), in order to provide the MOSFET structure with reduce gate resistance, and improved on-off response rate (Hsu, ¶0033, ¶0048-¶0050, ¶0056, ¶0056).
Response to Arguments
Applicant's arguments filed 02/04/2026 have been fully considered but they are not persuasive.
In response to applicants’ argument that “After removal of the hardmask, Gajda fails to disclose that the top surface of the semiconductor substrate 100 is revealed”, the examiner submits that newly discovered prior art by Yamazaki teaches a method of forming a trench-gate-type transistor wherein after removal of the hardmask (103), the top surface of the semiconductor substrate (101) is revealed, to form the gate electrode structure in self-aligning with the gate trench (104) to prevent misalignment of the gate electrode structure (109).
Thus, the above applicant’s argument is not persuasive, and the rejection of claim 8 under 35 USC 103 over Gajda in view of Hiyoshi, Matsunaga, Ikeda, and Yamazaki is maintained.
Regarding dependent claims 10-14, 16-19, and 21-29 which depend on the independent claim 8, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891