Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/26/2025 has been entered.
Applicant’s election without traverse of species 2 in the reply filed on 2/5/2026 is acknowledged.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dunne (US 20080142940 A1).
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CLAIM 1. Dunne disclose an electronic device, comprising: a substrate 150 having an upper surface; an electronic component 130 disposed over the upper surface of the substrate 150;
an intermediate structure disposed over the upper surface of the substrate 150 and comprising
an interposer 110 and a first conductive element 12/13 over the interposer; and a protective layer [i.e. encapsulant] disposed over the upper surface of the substrate 150 and encapsulating the electronic component 130 and having an upper surface 140a substantially level with an upper surface 140a of the at least one conducive element (Dunne Fig. 1 – See marked relevant portion of Fig. 1 presented below.)
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wherein the upper surface 140a of the first conductive element 12/13 comprises a first portion adjacent to the protective layer [encapsulant/molding], wherein the first portion is substantially level with the upper surface of the protective layer [coplanar surface 140a], and wherein the first portion vertically covers the protective layer to produce a mold lock (Note: The claim language, as interpreted in light of the elected invention illustrated in Applicant’s Figure 2B, requires a conductive portion with an upper surface coplanar to the protective layer and a conductive element that extends, flares or slopes out in the direction away from the substrate such that it is also over a portion of the protective layer. A T-shaped or upside-down triangle (sloped/tapered) allows the conductive feature to remain substantially level while extending over the protective material. As shown in Dunne, the conductive element as being tapered and extending laterally at the surface of the protective layer such that it possesses an upper surface which is both coplanar and covers a portion of the protective layer, thereby meeting the broad scope of the claim. Because Dunne provides the required structure to achieve the recited functionality, it would have been obvious to a PHOSITA at the time of the invention to recognize the capability of achieving the same results using this commonly known shape.
Claim(s) 12, 14-15, 25-29 & 35-36, 38-40, 46-51 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dunne et al. (Dunne (US 20080142940 A1)) in view of (US 20220045008 A1)
CLAIM 12. Dunne discloses an electronic device, comprising: a substrate 150; an electronic component 130 disposed over the substrate;
an interposer 110 disposed over the substrate 150;
an electrical connection 112 disposed between the substrate 150 and the interposer 110, wherein the electrical connection 112 comprises a reflowable material (This functional limitation does not provide any structural distinction, as conventional metals have a melting point and liquid state at some temperature. ); and
a first non-reflowable pillar disposed over the interposer 112/113 and configured to electrically connect to the electronic component through the interposer (generic functionality and purpose of interconnects/via/pillars), the electrical connection and the substrate 150; wherein the interposer 110 comprises a conductive via,.
Dunne is merely silent upon wherein the conductive via is tapered from a surface of the interposer on which the electrical connection is disposed toward a surface of the interposer on which the first non-reflowable pillar is disposed. This however is a known conventional shape for a via when forming interposers. Kang et al. teaches forming vias for a analogous interposer 110 having tapered vias 114. Note that the “core portion” 110 of Kang is analogous to the claimed interposer. It is a interposer with a opening with a “electronic component” 120 therein. As shown, the conductive via of Kang is directly analogous to the tapered via sandwiched between conductive pads as depicted in Applicant’s elected invention shown in figure 2BA tapered same may simply be an artifact of being formed by wet etching via opening during formation or a design choice to increase or decrease the ends of the vias to tailor a size of its contact surface.
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Conventional change in shape of conductive vias, is considered a obvious modification to a PHOSITA at the time of the invention, as the change in shape is not understood to provide any further unexpected result or benefit, under the guidance of MPEP 2144.04.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the via shape of Dunne with a tapered shape as taught by Kang, since simple substitution of one known element for another to obtain predictable results of a operable electrical passthrough is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 14. Dunne in view of Kang disclose an electronic device of claim 12, but may be silent upon specifically wherein a height of the electrical connection is in a range from about 30 um to about 50 um, and wherein a height of the first non-reflowable pillar is in a range from about 70 um to about 100 um. Dunne paragraph, [0008, 33, 37-44, etc..] does however demonstrate that these recited ranges over with conventional known ranges of thickness of the analogous components in the art.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the thickness through routine experimentation and optimization to obtain optimal or desired device performance because the thickness is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
CLAIM 15. Dunne in view of Kang disclose an electronic device of claim 14, wherein the first non-reflowable pillar is tapered (Dunne Fig. 1 & Kang Fig. 5 – Both demonstrate the known convention in the art that both pillars and vias may have tapered shapes. This is a known generic shape in the art, and understood to achieve well known expected results.).
CLAIM 25. Dunne in view of Kang disclose an electronic device of claim 24 wherein a second portion of the upper surface of the first conductive element is recessed with respect to the first portion of the upper surface of the first conductive element (Dunne Fig. 1).
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CLAIM 26. Dunne in view of Kang disclose an electronic device of claim 1, further comprising a finish layer (i.e. solder) disposed over the upper surface of the first conductive element, wherein the finish layer covers the first portion and the second portion of the upper surface of the first conductive element. (Dunne Fig. 1 ).
CLAIM 27. Dunne in view of Kang disclose an electronic device of claim 26, wherein the finish layer comprises electroless nickel immersion gold (Dunne Fig. 1 & ¶53 –“ [0053] Alternatively, an additional surface finish step including electrolytic nickel/gold, electroless nickel, and immersion gold, or a copper plating step may be used to define the circuit pattern 502 of both via sides.” & Kang Fig. 5 – Selection of a material in the absence of unexpected results is considered a obvious design choice. Recited material is understood for adhesion, conductivity, etc..).
CLAIM 28. Dunne in view of Kang disclose an electronic device of claim 26, wherein the finish layer comprises pre-solder, and wherein the pre-solder comprises a void (Dunne Fig. 1 & ¶53 –“ [0053] Alternatively, an additional surface finish step including electrolytic nickel/gold, electroless nickel, and immersion gold, or a copper plating step may be used to define the circuit pattern 502 of both via sides.” & Kang Fig. 5 – Selection of a material in the absence of unexpected results is considered a obvious design choice. Recited material is understood for adhesion, conductivity, etc..).
CLAIM 29. Dunne in view of Kang disclose an electronic device of claim 1, wherein a lateral surface of the first conductive element has a recess adjacent to the interposer, and wherein the protective layer extends into the recess (Dunne Fig. 1 ).
CLAIM 35. Dunne in view of Kang disclose an electronic device of claim 12, wherein the surface of the interposer 110 on which the first non-reflowable pillar 12/13 is disposed is higher than an upper surface of the electronic component (Dunne Fig. 1 ).
CLAIM 36. Dunne in view of Kang disclose an electronic device of claim 35, wherein the surface of the interposer on which the electrical connection is disposed is higher than a lower surface of the electronic component (Dunne Fig. 1 ).
CLAIM 38. Dunne in view of Kang disclose an electronic device of claim 12, further comprising a second non-reflowable pillar 12/13 disposed over the interposer adjacent to the first non-reflowable pillar (Dunne Fig. 1 ).
CLAIM 39. Dunne in view of Kang disclose an electronic device of claim 38, however may not explicitly recite wherein a pitch between the first non-reflowable pillar and the second non-reflowable pillar is about 300 um.. In the art pitch is a well known optimizable parameter. Pitch determines the maximum density of interconnections, directly limiting how much data can travel between trough a cross sectional area.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the pitch through routine experimentation and optimization to obtain optimal or desired device performance because the pitch is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
CLAIM 40. Dunne in view of Kang disclose an electronic device of claim 38, wherein each of the first non-reflowable pillar and the second non-reflowable pillar is tapered from a lower surface adjacent to the interposer toward an upper surface facing away from the interposer, such that a distance between the first non-reflowable pillar and the second non-reflowable pillar increases in a direction away from the interposer (Dunne Fig. 1 & Kang Fig. 5 – Both demonstrate the known convention in the art that both pillars and vias may have tapered shapes. This is a known generic shape in the art, and understood to achieve well known expected results.).
CLAIM 46. Dunne in view of Kang disclose an electronic device of claim 12, wherein the interposer comprises a first pad adjacent to the surface of the interposer on which the first non-reflowable pillar is disposed, and wherein a width of the first pad is greater than a maximum width of the first non-reflowable pillar. (Dunne Fig. 1 ).
CLAIM 47. Dunne in view of Kang disclose an electronic device of claim 46, wherein the interposer comprises a second pad adjacent to the surface of the interposer on which the electrical connection is disposed, and wherein a width of the first pad is smaller than a maximum width of the electrical connection. (Dunne Fig. 1 ).
CLAIM 48. Dunne in view of Kang disclose an electronic device of claim 26, wherein the interposer comprises a second pad adjacent to the surface of the interposer on which the electrical connection is disposed, and wherein a width of the first pad is smaller than a maximum width of the electrical connection. (Dunne Fig. 1 ).
CLAIM 49. Dunne in view of Kang disclose an electronic device of claim 48, wherein the finish layer vertically overlaps the lateral surface of the first conductive element (Dunne Fig. 1 ).
CLAIM 50. Dunne in view of Kang disclose an electronic device of claim 49, wherein the finish layer (ie. solder connections) vertically overlaps the protective layer. (Dunne Fig. 1 ).
CLAIM 51. Dunne in view of Kang disclose an electronic device of claim 29, wherein the first conductive element comprises a tapered section above the recess, and wherein a width of the tapered section decreases in a direction away from the interposer. Dunne Fig. 1 & Kang Fig. 5 – Both demonstrate the known convention in the art that both pillars and vias may have tapered shapes. This is a known generic shape in the art, and understood to achieve well known expected results.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
2/27/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898