DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
The indicated allowability of claim17-20 is withdrawn in view of the newly discovered reference(s) to Chen et. al. (US PGPub 2021/0091022, hereinafter referred to as “Chen”). Rejections based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipate by Chen et. al. (US PGPub 2021/0091022, hereinafter referred to as “Chen”).
Chen discloses the semiconductor method as claimed. See figures 1-5 and corresponding text, where Chen teaches, in claim 17, a semiconductor manufacturing method, comprising:
forming a first semiconductor element (10A, Fig. 5) with a first bonding film (15; [0044] describing bonding layers are formed on both 10A and 20A), wherein the first bonding film having a first concave surface (Figs. 2A & 2B) is fully formed on one side of the first semiconductor element;
forming a second semiconductor element (20A, Fig. 5) with a second bonding film (15; [0044] describing bonding layers are formed on both 10A and 20A), wherein the second bonding film is formed on one side of the second semiconductor element; and
bonding the first semiconductor element and the second semiconductor element by bonding the first bonding film and the second bonding film (Fig. 5; [0045]- [0046]).
Chen teaches, in claim 18, wherein the first semiconductor element is a chip, and the second semiconductor element is a wafer ([0047]).
Chen teaches, in claim 19, wherein the first semiconductor element is a wafer, and the second semiconductor element is a chip ([0047]).
Chen teaches, in claim 20, wherein the second bonding film has a second convex surface ([0036]).
REASONS FOR ALLOWANCE
Claims 1-16 are allowed over the prior art of record.
The following is an examiner’s statement of reasons for allowance: The closest prior art of record and to the examiner’s knowledge does not suggest or render obvious a semiconductor manufacturing method, particularly characterized by, forming a semiconductor element with a first bonding film and a first stressing film, wherein the first bonding film and the first stressing film are formed on two opposite sides of the first semiconductor element, and the first stressing film makes the first bonding film have a first convex surface; wherein in the first convex surface is formed by curing the first stressing film, as detailed in claim 1. Claims 2-9 depend from claim 1.
The closest prior art of record and to the examiner’s knowledge does not suggest or render obvious a semiconductor manufacturing method, particularly characterized by wherein the first convex surface is formed by etching the first bonding film and a mask bump formed on the first bonding film, as detailed in claim 10. Claims 11-16 depends from claim 10.
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Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 September 29, 2026
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