DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-13, 21-22, 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al (US Publication No. 2020/0135580) in view of Chen et al (US Publication No. 2021/0366786).
Regarding claim 8, Hsieh discloses a method, comprising: forming first, second, third fin structures over a substrate Fig 2, wherein a first trench Fig 2, 280 is formed between the first and second fin structures and a second trench Fig 2, 281 is formed between the second and third fin structures Fig 2;depositing a first dielectric layer Fig 6, 300/400 in the first and second trenches, wherein the first dielectric layer fills the first trench Fig 6; depositing a first dielectric material Fig 7, 410 on the first dielectric layer in the second trench Fig 7;recessing the first dielectric material Fig 8;depositing a second dielectric material Fig 9, 500 on the first dielectric material in the second trench; recessing a first portion of the first, second, third fin structures Fig 10-12, wherein an opening is formed in a first portion of the second dielectric layer during the recessing Fig 12; forming first, second, third source/drain (S/D) epitaxial features Fig 13, wherein the opening is expanded in the first dielectric material during the forming the first, second, third S/D epitaxial features Fig 12-13.
Hsieh discloses all the limitations but is silent on the additional dielectric layer.
Whereas Chen discloses depositing a high-k dielectric layer Fig 4A-4B, 70C ¶0042 in the opening and on the first, second, third S/D epitaxial features Fig 4A-4B, wherein the high-k dielectric layer Fig 4A-4B, 70C fills a portion of the opening in the first dielectric material Fig 4A-4B; and removing portions of the high-k dielectric layer deposited on the first, second, third S/D epitaxial features Fig 8A-8B.
Hsieh and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hsieh and incorporate the teachings of Chen to provide protection to source/drain layers during subsequent processing.
Regarding claim 9, Hsieh and Chen teach the device of claim 8. However, Chen discloses forming a contact etch stop layer Fig 9A-9B, 94 on the high-k dielectric layer Fig 4A-4B, 70C after the removing the portions of the high-k dielectric layer ¶0058-0059. Hsieh and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hsieh and incorporate the teachings of Chen to provide protection to source/drain layers during subsequent processing.
Regarding claim 10, Hsieh discloses forming one or more sacrificial gate stacks over a second portion of the first, second, third fin structures prior to recessing the first portion of the first, second, third fin structures ¶0021, 0059.
Regarding claim 11, Hsieh and Chen teach the device of claim 8. However, Chen discloses wherein the opening has a "keyhole" shaped cross-section after expanding in the first dielectric material Fig 14A-15B. Hsieh and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hsieh and incorporate the teachings of Chen since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 12, Hsieh discloses depositing a second dielectric layer Fig 15, 850 ¶0061, wherein the first dielectric layer is deposited on the second dielectric layer Fig 15.
Regarding claim 13, Hsieh discloses recessing the second dielectric layer after depositing the second dielectric material and before forming the one or more sacrificial gate stacks¶0061 Fig 14-15.
Regarding claim 21, Hsieh discloses a method, comprising: depositing a first dielectric material Fig 6, 300/400 between first and second fin structures Fig 6;depositing a second dielectric material Fig 7, 410 over the first dielectric material; forming first and second sacrificial gate electrodes over the second dielectric material ¶0061 Fig 14-15, wherein a portion of the second dielectric material is exposed between the first and second sacrificial gate electrodes Fig 13-15;recessing the first and second fin structures to form an opening in the exposed portion of the second dielectric material Fig 12;forming source/drain epitaxial features over the recessed first and second fin structures Fig 13, wherein the opening is expanded into the first dielectric material during the formation of the source/drain epitaxial features Fig 12-13.
Hsieh discloses all the limitations but silent on the additional dielectric layer.
Whereas Chen discloses forming a high-k dielectric layer Fig 4A-4B, 70C ¶0042 in the opening wherein an upper surface of the high-k dielectric layer is located at a level between an upper surface of the second dielectric material and a lower surface of the second dielectric material Fig 5A-7B.
Hsieh and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hsieh and incorporate the teachings of Chen to provide protection to source/drain layers during subsequent processing.
Regarding claim 22, Hsieh and Chen teach the device of claim 21. However, Chen discloses wherein the high-k dielectric layer is formed by depositing the high-k dielectric layer in the opening and over the source/drain epitaxial features and removing portions of the high-k dielectric layer formed in the opening and over the source/drain epitaxial features Fig 8A-10B. Hsieh and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hsieh and incorporate the teachings of Chen to provide protection to source/drain layers during subsequent processing.
Regarding claim 25, Hsieh and Chen teach the device of claim 21. However, Chen discloses wherein the high-k dielectric layer is seamless Fig 4A-10B. Hsieh and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hsieh and incorporate the teachings of Chen since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 26, Hsieh and Chen teach the device of claim 21. However, Chen discloses depositing a contact etch stop layer Fig 9A-9B, 94 in the opening over the high-k dielectric layer Fig 4A-4B, 70C and over the source/drain epitaxial features Fig 9A-9B. Hsieh and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hsieh and incorporate the teachings of Chen to provide protection to source/drain layers during subsequent processing.
Regarding claim 27, Hsieh and Chen teach the device of claim 21. However, Chen discloses comprising depositing an interlayer dielectric (ILD) layer on the contact etch stop layer in the opening Fig 12B. Hsieh and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hsieh and incorporate the teachings of Chen to provide protection to source/drain layers during subsequent processing.
Claims 14, 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al (US Publication No. 2020/0135580) in view of Chen et al (US Publication No. 2021/0366786) and in further view of Kao et al (US Publication No. 2021/0376113).
Regarding claim 14, Hsieh discloses all the limitations except for the deposition process. Whereas Kao discloses wherein the high-k dielectric layer is deposited by an atomic layer deposition (ALD) process ¶0028. Hsieh and Kao are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the deposition of Hsieh and incorporate the teachings of Kao as an alternative method known in the art for forming the high k dielectric.
Regarding claim 23, Hsieh discloses wherein the high-k dielectric layer is deposited by an atomic layer deposition process¶0028.
Regarding claim 24, Hsieh and Chen teach the device of claim 21. However, Chen discloses wherein a thickness of the high-k dielectric layer ranges from about 5 nm to about 15 nm ¶0042. Hsieh and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hsieh and incorporate the teachings of Chen since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
Allowable Subject Matter
Claims 15-20 are allowed over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: After further search and consideration, it is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach or suggest “depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer is deposited on the first portion of the second dielectric material, and a second portion of the high-k dielectric layer is deposited on the second portion of the second dielectric material; depositing a third dielectric material on the second portion of the high-k dielectric layer; performing a planarization process to remove the first portion of the high-k dielectric layer and a portion of the third dielectric material; forming one or more sacrificial gate stacks over a first portion of the first, second, third fin structures and over a first portion of the second portion of the high-k dielectric layer; forming spacers on sidewalls of the one or more sacrificial gate stacks and on second portions of the second portion of the high-k dielectric layer; forming an opening in a third portion of the second portion of the high-k dielectric layer; and depositing a contact etch stop layer in the opening”, as recited in independent claim 15.
Claims 16-20 are also allowed as being directly or indirectly dependent of the allowed independent base claims.
Response to Arguments
Applicant's arguments filed 5/21/2026 have been fully considered but they are not persuasive. In response to applicants’ argument that the prior art of record does not teach the removal of part of the first dielectric material 410, the examiner disagrees and finds the argument unpersuasive. Fig 12 and Fig 13 shows dishing of layer 400 and 410. Paragraph 0051 of Hsieh described the process in detail. Therefore the prior art of record teach the above claimed limitations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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