Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2, 8-9, 21-36 have been considered but are moot in view of the newly cited prior art.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-36 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 9, Claim 9 contains the phrase, “one of the two bonding structures”, but the presence of two bonding structures was not established prior. This is seen as indefinite. Further, the recitation “wherein in one of the two bonding structures” appears to be an incomplete statement and lacks the specifics of what is “in one of the two bonding structures”. Claims 26-30 are dependent upon Claim 9 and, therefore, inherit the above deficiencies.
Regarding Claim 31, Claim 31 recites the limitation “the supporting silicon layer” at line 5 and the limitation “the supporting layer” at line 6. It is unclear as to what element said limitations are referring to. While the phrase, “the supporting silicon layer” is seen, whether the supporting layer and the supporting silicon layer are meant to reference the same element of the disclosure is ambiguous, and this limitation is seen as indefinite. Appropriate correction is required. Claims 32-36 are dependent upon Claim 31 and therefore inherit the above deficiencies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 8, 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vadhavkar et al (USPGPUB 20160343687, hereinafter “Vadhavkar”) in view of Hou et al (DE 102020115288 A1, hereinafter “Hou”).
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Regarding Claim 1, Vadhavkar teaches (Fig. 3) a semiconductor device, comprising: a device die (102); a supporting silicon layer (SSM) over the device die (350); a thermal enhance module (TE) positioned between the device die (102) and the supporting silicon layer (SSM) ; and a memory module (128) adjacent to (memory module 128 is seen adjacent to the thermal enhance module TE) the thermal enhance module (TE) and positioned between (thermal enhance module is seen positioned between device die 102 and supporting silicon layer SSM) the device die (102) and the supporting silicon layer (SSM); wherein the supporting silicon layer (SSM) and the memory module (128) are bonded via a bonding structure (372).
Vadhavkar is silent with regards to a device, wherein the bonding structure includes at least one bonding film whose thickness is less than 200 Angstroms.
Hou (Fig. 4B) teaches at least one bonding film (415) whose thickness is less than 200 Angstroms ([0063], “The first wafer bond layer 415 can using any suitable method, such as atomic layer deposition (ALD), CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD or the like to a thickness between about 1 nm and about 1000 nm, for example about 5 nm, can be deposited.”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the dimensions of Hou into the device of Vadhavkar in order to arrive at the expected result of create a device which has the known benefit of being compact and compatible with the dimensions of modern IC devices with reasonable expectation of success.
Regarding Claim 2, Vadhavkar in view of Hou teaches the semiconductor device according to claim 1, wherein in the bonding structure, a first bonding film (top half of the bond pad seen between silicon supporting layer SSM and memory module 128 in Vadhavkar Fig. 3) is formed on the memory module (128); a second bonding film (bottom half of the bond pad seen between silicon supporting layer SSM and memory module 128 in Vadhavkar Fig. 3) is formed on the supporting silicon layer (SSM); the first bonding film and the second bonding film are bonded.
Regarding the process limitations recited in claim 2 ("the first bonding film and the second bonding film are bonded "), these would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced. Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Regarding Claim 21, Vadhavkar in view of Hou teaches the semiconductor device according to claim 2, wherein a thickness of the first bonding film (top half of the bond pad seen between silicon supporting layer SSM and memory module 128 in Vadhavkar Fig. 3) is equal to or less than 100 Å (Hou [0063], “The first wafer bond layer 415 can using any suitable method, such as atomic layer deposition (ALD), CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD or the like to a thickness between about 1 nm and about 1000 nm, for example about 5 nm, can be deposited.”; a thickness of 5nm would be obvious in view of the cited art to one of ordinary skill in the art).
Regarding Claim 22, Vadhavkar in view of Hou teaches the semiconductor device according to claim 2, wherein a thickness of the second bonding film (bottom half of the bond pad seen between silicon supporting layer SSM and memory module 128 in Vadhavkar Fig. 3) is equal to or less than 100 Å (Hou [0063], “The first wafer bond layer 415 can using any suitable method, such as atomic layer deposition (ALD), CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD or the like to a thickness between about 1 nm and about 1000 nm, for example about 5 nm, can be deposited.”; a thickness of 5nm would be obvious in view of the cited art to one of ordinary skill in the art).
Regarding Claim 23, Vadhavkar in view of Hou teaches the semiconductor device according to claim 2, wherein the first bonding film is an oxide film or a nitride film (Hou [0063], “the first wafer bond layer is 415 formed from a silicon-containing dielectric material such as silicon oxide”).
Regarding Claim 24, Vadhavkar in view of Hou teaches the semiconductor device according to claim 2, wherein the second bonding film is an oxide film or a nitride film. (Hou [0063], “the first wafer bond layer is 415 formed from a silicon-containing dielectric material such as silicon oxide”).
Regarding Claim 25, Vadhavkar in view of Hou teaches the semiconductor device according to claim 2, wherein a thickness of the second bonding film (bottom half of the bond pad seen between silicon supporting layer SSM and memory module 128 in Vadhavkar Fig. 3) is equal to a thickness of the first bonding film (top half of the bond pad seen between silicon supporting layer SSM and memory module 128 in Vadhavkar Fig. 3).
Regarding Claim 8, Vadhavkar teaches (Fig. 3) a semiconductor device, comprising: a supporting silicon layer (SSM); a semiconductor-based thermal enhance module (TE) bonded to a bottom side (thermal enhance module TE is seen bonded to a bottom side of supporting silicon layer SSM) of the supporting silicon layer (SSM); and a memory module (128), adjacent to (memory module 128 is seen adjacent to thermal enhance module TE) the semiconductor-based thermal enhance module (memory module 128 is seen bonded to the bottom side of supporting silicon layer SSM) and bonded to the bottom side of the supporting silicon layer (SSM); wherein the supporting silicon layer (SSM) and the semiconductor-based thermal enhance module (TE) are bonded via a bonding structure (372).
Vadhavkar is silent with regards to a device wherein the bonding structure includes at least one bonding film with thickness less than 200 Angstroms.
Hou teaches (Fig. 4B) a device wherein the bonding structure (415) includes at least one bonding film with thickness less than 200 Angstroms ([0063], “The first wafer bond layer 415 can using any suitable method, such as atomic layer deposition (ALD), CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD or the like to a thickness between about 1 nm and about 1000 nm, for example about 5 nm, can be deposited.”)
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the dimensions of Hou into the device of Vadhavkar in order to arrive at the expected result of create a device which has the known benefit of being compact and compatible with the dimensions of modern IC devices with reasonable expectation of success.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/V.J.L./Examiner, Art Unit 2898
/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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