DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on December 3, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 31, 33-36 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al (USPGPUB 20210066222, hereinafter “Chen”).
Regarding Claim 31, Chen teaches (Fig. 21) a manufacturing method of a semiconductor device, comprising: forming a supporting silicon layer (102); forming a memory module (400 [0046], “the second die structure 400”; [0093], “…the stacked dies 910 may be memory dies such as low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or the like memory modules…” a device with a die incorporating a memory device is an inherently present embodiment); and bonding (bonding films 312 and 412 form a bonding structure, hereinafter BST, which bonds supporting silicon layer 102 with the memory module understood to be in die 400 of Fig. 21) the supporting silicon layer (102) and the memory module (400) via a bonding structure (BST).
Regarding Claim 33, Chen teaches (Fig. 21) the manufacturing method of the semiconductor device according to claim 31, wherein the step of bonding the supporting silicon layer (102) and the memory module (400) via the bonding structure (BST) comprises: forming a first bonding film (412) on the memory module (400); forming a second bonding film (312) on the supporting silicon layer (102); bonding (Fig. 21, first bonding film 412 and second bonding film 312 are seen bonded) the first bonding film (412) and the second bonding film (312).
Regarding Claim 34, Chen teaches (Fig. 21) the manufacturing method of the semiconductor device according to claim 31, wherein the first bonding film (412) is formed by deposition or thermal oxidation ([0048], “The bonding layer 412 may be formed from similar materials or using similar techniques as described above for bond layer 126, bond layer 224, or bonding layer 312.”; [0029], “The bond layer 126 may be formed using a deposition process such as CVD, PECVD, PVD, ALD, the like, or a combination thereof.”).
Regarding Claim 35, Chen teaches the manufacturing method of the semiconductor device according to claim 31, wherein the second bonding film (312) is formed by deposition or thermal oxidation ([0048], “The bonding layer 412 may be formed from similar materials or using similar techniques as described above for bond layer 126, bond layer 224, or bonding layer 312.”; [0029], “The bond layer 126 may be formed using a deposition process such as CVD, PECVD, PVD, ALD, the like, or a combination thereof.”)..
Regarding Claim 36, Chen teaches the manufacturing method of the semiconductor device according to claim 31, wherein the first bonding film (412) and the second bonding (312) are bonded via fusion bonding process ( [0038], “the bond layer 224 is bonded to the bond layer 306 using direct bonding (e.g., “fusion bonding” or “dielectric-to-dielectric bonding”); [0057], “the second die structure 400 is bonded to the first die structure 300 to form package 500 using, e.g., direct bonding or hybrid bonding”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2,8-9 and 21-30, and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Hou et al (DE 102020115288 A1, hereinafter “Hou”).
Regarding Claim 1, Chen teaches (Fig. 21) a semiconductor device (530), comprising: a supporting silicon layer (102; [0012], “The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a semiconductor wafer, or the like … In some embodiments, the semiconductor material of the substrate may include silicon;”); and a memory module (400 [0046], “the second die structure 400”; [0093], “…the stacked dies 910 may be memory dies such as low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or the like memory modules…” a device with a die incorporating a memory device is an inherently present embodiment); wherein the supporting silicon layer (102) and the memory module (910A,B) are bonded via (supporting silicon layer 102 and the memory modules understood to be in die 400 are bonded by a bonding structure, as seen in Fig. 26) a bonding structure (bonding structure, hereinafter BST, is seen including two bonding films 312 and 412), the bonding structure (BST) includes at least one bonding film (412, 312 are both bonding films).
Chen is silent with regards to a device wherein the bonding structure thickness is less than 200 Angstroms
Hou (Fig. 4B) teaches at least one bonding film (415) whose thickness is less than 200 Angstroms ([0063], “The first wafer bond layer 415 can using any suitable method, such as atomic layer deposition (ALD), CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD or the like to a thickness between about 1 nm and about 1000 nm, for example about 5 nm, can be deposited.”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the dimensions of Hou into the device of Chen in order to arrive at the expected result of create a device which has the known benefit of being compact and compatible with the dimensions of modern IC devices with reasonable expectation of success.
Regarding Claim 2, Chen in view of Hou teaches (Chen Fig. 21) the semiconductor device according to claim 1, wherein in the bonding structure (BST), a first bonding film is (412) formed on (first bonding film 412 is seen formed on memory module 400) the memory module (400); a second bonding film (312) is formed on (second bonding film 312 is formed on supporting silicon layer 102) the supporting silicon layer (102); the first bonding film (412) and the second bonding film (312) are bonded (films 412 and 312 are seen bonded in Fig. 21 of Chen).
Regarding Claim 8, Chen teaches (Fig. 21) a semiconductor device (530; [0012], “The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a semiconductor wafer, or the like … In some embodiments, the semiconductor material of the substrate may include silicon;”), comprising: a supporting silicon layer (102); and a thermal enhance module (408, [0051], “through substrate vias (TSVs) 446 may extend through the substrate 442. The TSVs 446 may be formed by, for example, forming openings extending through the substrate 442 using a suitable photolithography and etching process. The openings may then be filled by a conductive material such as copper or the like”; the vias 408 seen in Fig. 21 of Chen would act as thermal enhance component as they have a structure that would enhance the heat-resistance/management of the device); wherein the supporting silicon layer (102) and the thermal enhance module (408) are bonded (the enhance module is seen bonded to the silicon layer 102) via a bonding structure (BST),
Chen is silent with regards to a device wherein the bonding structure includes at least one bonding film whose thickness is less than 200 Angstroms.
Hou teaches (Fig. 4B) a device wherein the bonding structure (415) includes at least one bonding film whose thickness is less than 200 Angstroms ([0063], “The first wafer bond layer 415 can using any suitable method, such as atomic layer deposition (ALD), CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD or the like to a thickness between about 1 nm and about 1000 nm, for example about 5 nm, can be deposited.”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the dimensions of Hou into the device of Chen in order to arrive at the expected result of create a device which has the known benefit of being compact and compatible with the dimensions of modern IC devices with reasonable expectation of success.
Regarding Claim 9, Chen in view of Hou teaches (Chen Fig. 21) the semiconductor device according to claim 8, wherein in the bonding structure, a first bonding film (412) is formed on (the first bonding film 412 is formed on the die structure 402 which includes thermal enhance component 408) the thermal enhance module (408); a second bonding film (312) is formed (second bonding film 312 is seen formed on supporting silicon layer 102) on the supporting silicon layer (102); the first bonding film (412) and the second bonding film (312) are bonded (first bonding film 412 and second bonding film 312 are seen bonded).
Regarding Claim 21, Chen in view of Hou teaches (Fig. 21 of Chen) the semiconductor device according to claim 2, wherein a thickness ([0063], “The first wafer bond layer 415 can using any suitable method, such as atomic layer deposition (ALD), CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD or the like to a thickness between about 1 nm and about 1000 nm, for example about 5 nm, can be deposited.”; a thickness of 5nm would be obvious in view of the cited art to one of ordinary skill in the art) of the first bonding film (412) is equal to or less than 100 Angstroms (5 nm is 50 Angstroms).
Regarding Claim 22, Chen in view of Hou teaches ([0063], “The first wafer bond layer 415 can using any suitable method, such as atomic layer deposition (ALD), CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD or the like to a thickness between about 1 nm and about 1000 nm, for example about 5 nm, can be deposited.”; a thickness of 5nm would be obvious in view of the cited art to one of ordinary skill in the art) the semiconductor device according to claim 2, wherein a thickness of the second bonding film (312) is equal to or less than 100 Angstroms (5 nm is 50 Angstroms).
Regarding Claim 23, Chen in view of Hou teaches the semiconductor device according to claim 2, wherein the first bonding film (412) is an oxide film or a nitride film ([0040], “The bonding layer 312 may be formed from one or more layers of one or more dielectric materials such as silicon oxide or the like”; the first bonding film 412 would have the same material as that of the second bonding film 312).
Regarding Claim 24, Chen in view of Hou teaches the semiconductor device according to claim 2, wherein the first bonding film (312) is an oxide film or a nitride film ([0040], “The bonding layer 312 may be formed from one or more layers of one or more dielectric materials such as silicon oxide or the like”).
Regarding Claim 25, Chen in view of Hou teaches the semiconductor device according to claim 2, wherein a thickness of the second bonding film (312) is equal to ([0048], “The bonding layer 412 may be formed from similar materials or using similar techniques as described above for bond layer 126, bond layer 224, or bonding layer 312”; As seen in Fig. 21 of Chen , the bonding layers 312 and 412 are seen having equal thicknesses) a thickness of the first bonding film (412).
Regarding Claim 26, Chen in view of 25 The semiconductor device according to claim 9, wherein a thickness of ([0063], “The first wafer bond layer 415 can using any suitable method, such as atomic layer deposition (ALD), CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD or the like to a thickness between about 1 nm and about 1000 nm, for example about 5 nm, can be deposited.”; a thickness of 5nm would be obvious in view of the cited art to one of ordinary skill in the art) the first bonding film (412) is equal to or less than 100 A (5nm is 50 Angstroms, which is less than 100 Angstroms).
Regarding Claim 27, Chen in view of Hou teaches the semiconductor device according claim 9, wherein a thickness of ([0063], “The first wafer bond layer 415 can using any suitable method, such as atomic layer deposition (ALD), CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD or the like to a thickness between about 1 nm and about 1000 nm, for example about 5 nm, can be deposited.”; a thickness of 5nm would be obvious in view of the cited art to one of ordinary skill in the art) the first bonding film (412) is equal to or less than 100 A (5nm is 50 Angstroms, which is less than 100 Angstroms).
Regarding Claim 28, Chen in view of Hou teaches the semiconductor device according to claim 9, wherein the first bonding (412) film is an oxide film or a nitride film([0040], “The bonding layer 312 may be formed from one or more layers of one or more dielectric materials such as silicon oxide or the like”; the first bonding film 412 would have the same material as that of the second bonding film 312).
Regarding Claim 29 Chen in view of Hou teaches the semiconductor device according to claim 9, wherein the second bonding film (312) is an oxide film or a nitride film ([0040], “The bonding layer 312 may be formed from one or more layers of one or more dielectric materials such as silicon oxide or the like”).
Regarding Claim 30, Chen in view of Hou teaches the semiconductor device according to claim 9, wherein a thickness of the second bonding film (312) is equal to ([0048], “The bonding layer 412 may be formed from similar materials or using similar techniques as described above for bond layer 126, bond layer 224, or bonding layer 312”; As seen in Fig. 21 of Chen , the bonding layers 312 and 412 are seen having equal thicknesses) a thickness of the first bonding film (412).
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 31 above, and further in view of Hou.
Regarding Claim 32, Chen teaches the manufacturing method of the semiconductor device according to claim 31, but is silent with regards to manufacture of a device wherein the bonding structure includes at least one bonding film whose thickness is less than 200 A.
Hou teaches the manufacture of a device wherein the bonding structure includes at least one bonding film whose thickness is less than 200 A ([0063], “The first wafer bond layer 415 can using any suitable method, such as atomic layer deposition (ALD), CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD or the like to a thickness between about 1 nm and about 1000 nm, for example about 5 nm, can be deposited.”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the dimensions of Hou into the device of Chen in order to arrive at the expected result of create a device which has the known benefit of being compact and compatible with the dimensions of modern IC devices with reasonable expectation of success.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR J LASASSO whose telephone number is (703)756-5668. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/V.J.L./Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898