DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/20/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0109055 to Preisler et al. (hereinafter Preisler) in view of Aitken et al. (US Patent No. 7,064,414, hereinafter Aitken).
With respect to claim 1, Preisler discloses a structure (e.g., SOI heterojunction bipolar transistor (HBT)) (Preisler, Fig. 1, ¶0002, ¶0011-¶0015, ¶0024-¶0041) comprising:
a heterojunction bipolar transistor (e.g., SOI HBT) (Preisler, Fig. 1, ¶0025) comprising a collector (e.g., 201), sub-collector region (e.g., 204/205), emitter (e.g., 245) and base region (e.g., 231); and
contacts (e.g., 261-266) (Preisler, Fig. 1, ¶0025) electrically coupled to the sub-collector region (e.g., through the collector contact/sinker region 202).
Further, Preisler does not specifically disclose heater terminal contacts which receive a current to generate heat to thermally anneal oxide interface traps.
However, Aitken teaches forming heater terminal contacts (e.g., heating contacts 6) (Aitken, Fig. 3, Col. 2, lines 58-64; Col. 3, lines 25-55; Col. 4, lines 44-67; Col. 5, lines 1-4) which receive a current (e.g., voltage suppled form the external power supply) to generate heat to thermally anneal oxide interface traps (e.g., trapped electrical charge in the insulator layer 12) to remove electrical charge buildup from the insulator layer (12) to prevent malfunction of the device. In Aitken, the insulator layer (12) (Aitken, Fig. 3, Col. 3, lines 11-55) is formed under the device layer (5) including active electrical devices (e.g., transistors, resistors), and a heating element (30) connected to the heater terminal contacts (6) is formed under the insulator layer (12), to form a semiconductor structure applicable to any type of circuitry.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Preisler by forming a SOI HBT structure including heating contacts to heat a portion of the substrate under the insulator layer as taught by Aitken to have the structure, comprising: heater terminal contacts which receive a current to generate heat to thermally anneal oxide interface traps, in order to remove electrical charge buildup from the insulator layer to prevent malfunction of the device (Aitken, Col. 2, lines 58-64; Col. 3, lines 25-55).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0109055 to Preisler in view of Aitken (US Patent No. 7,064,414) as applied to claim 1, and further in view of Wang et al. (US Patent No. 8,159,814, hereinafter Wang) and Wachter (US Patent No. 6,064,240).
Regarding claim 2, Preisler in view of Aitken discloses the structure of claim 1. Further, Preisler does not specifically disclose that heater terminal contacts are orthogonally positioned relative to a contact to the collector and the heater terminal contacts are electrically connected to a bias circuit configured to apply a voltage delta across the heater terminal contacts resulting in the heater terminal contacts generating heat to anneal or repair damage of the heterojunction bipolar transistor.
However, Aitken teaches forming heater terminal contacts (6) (Aitken, Fig. 3, Col. 2, lines 58-64) that are electrically connected to an external power supply circuit (Aitken, Fig. 3, Col. 3, lines 42-51) configured to apply a voltage across the heater terminal contacts (6) resulting in the heater terminal contacts generating heat to anneal or repair damage of the heterojunction bipolar transistor.
Further, Wang teaches forming a current supplying circuit (Wang, Figs. 4A-4B, 5A-5B, Col. 1, lines 7-11; Col. 2, lines 40-67; Cols. 3, lines 1-25; Col. 5, lines 1-28; Col. 7-9) that is adapted to provide an operating current or a repairing current to the poly wire heater (e.g., 531 in Fig. 5B) connected to the emitter or the collector of the heterojunction bipolar transistor, to provide heating based on the repairing current to heal and recover the interconnect structures for the HBT transistor, and thus to improve the reliability and lifetime of transistors.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Preisler/Aitken by biasing the heater terminals of the HBT transistor as taught by Aitken, wherein the heater terminals are connected to the collector of the HBT as taught by Wang to have the structure, wherein heater terminal contacts are orthogonally positioned relative to a contact to the collector and the heater terminal contacts are electrically connected to a bias circuit configured to apply a voltage across the heater terminal contacts resulting in the heater terminal contacts generating heat to anneal or repair damage of the heterojunction bipolar transistor, in order to remove electrical charge buildup from the insulator layer to prevent malfunction of the device; and to provide heating based on the repairing current to improve the reliability and lifetime of bipolar transistors (Aitken, Col. 2, lines 58-64; Col. 3, lines 25-55; Wang, Col. 1, lines 7-11; Col. 2, lines 40-51; Col. 5, lines 16-29).
Regrading limitation “delta voltage”, Watcher teaches a circuit (Watcher, Col. 8, lines 65-67; Col. 9, lines 1-2) to apply a bias current pulse only during a specific point, as in the case of a delta voltage to minimize the total current consumption of the circuit.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Preisler/Aitken/Wang by biasing the heater terminals of the HBT transistor as taught by Aitken, wherein a bias current pulse is provided only during a specific point, as in the case of a delta voltage as taught by Watcher to have the structure, wherein a bias circuit configured to apply a voltage delta, in order to minimize the total current consumption of the bias circuit (Watcher, Col. 8, lines 65-67; Col. 9, lines 1-2).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0109055 to Preisler in view of Aitken (US Patent No. 7,064,414) as applied to claim 1, and further in view of Ouyang et al. (US 2008/0102568, hereinafter Ouyang).
Regarding claim 3, Preisler in view of Aitken discloses the structure of claim 1. Further, Preisler does not specifically disclose that the heater terminal contacts comprise metal structures on a surface of a bulk semiconductor substrate.
However, Aitken teaches forming heater terminal contacts (6) (Aitken, Fig. 3, Col. 2, lines 24-64) on a surface of a bulk semiconductor substrate (20).
Further, Ouyang discloses the structure, wherein the terminal contacts to provide heat conductive paths (Ouyang, Fig. 4, ¶0023) comprise metal structures (e.g., a heat conductive material comprises a metal or polysilicon) (Ouyang, Fig. 4, page 2, Col. 2, claim 2) on a surface of a bulk semiconductor substrate (e.g., p-Si substrate including n-well and p-well).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Preisler/Aitken by forming heating terminal contacts of the HBT transistor as taught by Aitken, wherein contacts comprised of a specific metal material as taught by Ouyang to have the structure, wherein the heater terminal contacts comprise metal structures on a surface of a bulk semiconductor substrate, in order to remove electrical charge buildup from the insulator layer to prevent malfunction of the device by providing heating contacts with appropriate heat conducing material (Aitken, Col. 2, lines 58-64; Col. 3, lines 25-55; Ouyang, ¶0015).
Claims 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0109055 to Preisler in view of Aitken (US Patent No. 7,064,414) as applied to claim 1, and further in view of Dungan et al. (US 2017/0062595, hereinafter Dungan).
Regarding claims 5 and 8, Preisler in view of Aitken discloses the structure of claim 1. Further, Preisler discloses the structure, wherein a contact (264) (Preisler, Fig. 1, ¶0025) to the collector is coupled to the sub-collector region (e.g., through the collector contact/sinker region 202), but does not specifically disclose that the heater terminal contacts and a contact to the collector are not electrically isolated (as claimed in claim 5); wherein the sub-collector region extends to an upper surface of a bulk semiconductor substrate and the heater terminal contacts (as claimed in claim 8).
However, Dungan teaches forming a structure (Dungan, Fig. 2, ¶0001-¶0002, ¶0020-¶0021, ¶0022-¶0024, ¶0036-¶0038) comprising multiple HBT transistor fingers, wherein each heterojunction bipolar transistor (HBT) comprises a plurality of contacts (e.g., interconnects 231/232) to the sub-collector (214) and comprised of a copper material that is a thermally conductive material used to provide electrical and thermal conductivity (Dungan, Fig. 2, ¶0024), such that terminal contacts (231/232) comprised of a copper material of the multiple HBT transistor fingers and a contact to the collector (e.g., collector contacts 233 electrically connected to the collector 212) (Dungan, Fig. 2, ¶0023, ¶0026) are on the sub-collector region (214), wherein the terminal contacts (e.g., interconnects 231/232) and a contact (233) to the collector are not electrically isolated, and the sub-collector region (214) extends to the heater terminal contacts (231/232).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Preisler/Aitken by forming heating terminal contacts of the HBT transistor as taught by Aitken, wherein a plurality of contacts comprised of a thermally conductive material disposed on a collector contact as taught by Dungan to have the structure, wherein the heater terminal contacts and a contact to the collector are not electrically isolated (as claimed in claim 5); wherein the sub-collector region extends to an upper surface of a bulk semiconductor substrate and the heater terminal contacts (as claimed in claim 8), in order to provide improved electrical connections to the power semiconductor device generating heat during operation (Dungan, ¶0001-¶0002, ¶0020-¶0021, ¶0023-¶0024, ¶0036-¶0038).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0109055 to Preisler in view of Aitken (US Patent No. 7,064,414) as applied to claim 1, and further in view of Koshino et al. (US Patent No. 4,710,794, hereinafter Koshino).
Regarding claims 6 and 7, Preisler in view of Aitken discloses the structure of claim 1. Further, Preisler does not specifically disclose the structure, further comprising at least one airgap below the sub- collector region (as claimed in claim 6); further comprising a non-single crystal semiconductor region below the at least one airgap (as claimed in claim 7).
However, Aitken teaches at least one airgap (35) (Aitken, Fig. 3, Col. 4, lines 44-67; Col. 4, lines 1-4) below the device region (22a), to reduce an amount of power necessary for heating to anneal traps.
Further, Koshino teaches forming an integrated circuit (Koshino, Fig. 2, Col. 1, lines 6-10; Col. 2, lines 5-13; Col. 4, lines 3-28; Col. 5, lines 18-31; Col. 6, lines 56-58) on a substrate including a bipolar transistor, wherein at least one airgap (e.g., air-tightly sealing recess 11) is formed below the bipolar transistor (6) including a collector region, and further comprising a non-single crystal semiconductor region (e.g., polycrystalline silicon 8) is deposited on the inner surfaces of the recesses (11) such that the polycrystalline silicon (8) (Koshino, Fig. 2, Col. 5, lines 18-31; Col. 6, lines 56-58) is disposed below the airgap (11), to provide element isolation with a high breakdown voltage to reliably isolate the semiconductor element and to protect the integrated circuit from the heat generating by the power transistor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Preisler/Aitken by forming at least one airgap under the device region as taught by Aitken, wherein an isolation structure including airgap is under a bipolar transistor as taught by Koshino, and wherein the bipolar transistor includes a sub-collector region to have the structure, further comprising at least one airgap below the sub- collector region (as claimed in claim 6); further comprising a non-single crystal semiconductor region below the at least one airgap (as claimed in claim 7), in order to reduce an amount of power necessary for heating to anneal traps; and to provide element isolation with a high breakdown voltage to reliably isolate the semiconductor element and to protect the integrated circuit from the heat generating by the power transistor (Aitken, Fig. 3, Col. 4, lines 44-67; Col. 4, lines 1-4; Koshino, Col. 1, lines 6-10; Col. 2, lines 5-13; Col. 5, lines 18-31; Col. 6, lines 56-58).
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0109055 to Preisler in view of Aitken (US Patent No. 7,064,414) and Dungan (US 2017/0062595) as applied to claim 8, and further in view of Koshino (US Patent No. 4,710,794).
Regarding claims 9 and 10, Preisler in view of Aitken and Dungan discloses the structure of claim 8. Further, Preisler does not specifically disclose the structure, further comprising an airgap below the sub-collector region (as claimed in claim 9); further comprising a non-single crystal semiconductor region below the airgap (as claimed in claim 10).
However, Aitken teaches at least one airgap (35) (Aitken, Fig. 3, Col. 4, lines 44-67; Col. 4, lines 1-4) below the device region (22a), to reduce an amount of power necessary for heating to anneal traps.
Further, Koshino teaches forming an integrated circuit (Koshino, Fig. 2, Col. 1, lines 6-10; Col. 2, lines 5-13; Col. 4, lines 3-28; Col. 5, lines 18-31; Col. 6, lines 56-58) on a substrate including a bipolar transistor, wherein at least one airgap (e.g., air-tightly sealing recess 11) is formed below the bipolar transistor (6) including a collector region, and further comprising a non-single crystal semiconductor region (e.g., polycrystalline silicon 8) is deposited on the inner surfaces of the recesses (11) such that the polycrystalline silicon (8) (Koshino, Fig. 2, Col. 5, lines 18-31; Col. 6, lines 56-58) is disposed below the airgap (11), to provide element isolation with a high breakdown voltage to reliably isolate the semiconductor element and to protect the integrated circuit from the heat generating by the power transistor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Preisler/Aitken/Dungan by forming at least one airgap under the device region as taught by Aitken, wherein an isolation structure including airgap is under a bipolar transistor as taught by Koshino, and wherein the bipolar transistor includes a sub-collector region to have the structure, further comprising at least one airgap below the sub- collector region (as claimed in claim 9); further comprising a non-single crystal semiconductor region below the at least one airgap (as claimed in claim 10), in order to reduce an amount of power necessary for heating to anneal traps; and to provide element isolation with a high breakdown voltage to reliably isolate the semiconductor element and to protect the integrated circuit from the heat generating by the power transistor (Aitken, Fig. 3, Col. 4, lines 44-67; Col. 4, lines 1-4; Koshino, Col. 1, lines 6-10; Col. 2, lines 5-13; Col. 5, lines 18-31; Col. 6, lines 56-58).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0109055 to Preisler in view of Aitken (US Patent No. 7,064,414) as applied to claim 1, and further in view of Emrick et al. (US 2003/0015767, hereinafter Emrick) and Wang (US Patent No. 8,159,814).
Regarding claim 11, Preisler in view of Aitken discloses the structure of claim 1. Further, Preisler does not specifically disclose the structure further comprising redundant circuitry coupled to a common control circuit, each of the redundant circuitry comprises a performance sensor and a heat sensor coupled to the common control circuit, the performance sensor detects a change in circuit performance of the heterojunction bipolar transistor, the common control circuit receives the circuit performance from the performance sensor and governs whether the heat should be applied to anneal defects, and the heat sensor detects the heat.
However, Emrick teaches forming controlling and controlled circuits (Emrick, Figs. 24, 38, 49, ¶0002, ¶0037, ¶0109-¶0112, ¶0176-¶0186, ¶0223-¶0228) integrated onto a monolithic device, wherein semiconductor devices of the integrated circuits include hetero-junction bipolar transistor (HBT), and controlled circuits include temperature, bias, redundant circuit, feedback or control of an integrated circuit integrated on a semiconductor structure (Emrick, Figs. 38, 49, ¶0178); specifically, a redundant circuitry (e.g., amplifiers 462/464) (Emrick, Figs. 38, 49, ¶0223-¶0228) is coupled to a control circuit (e.g., processor 466), wherein the processor (466) select one amplifier (462/466) as a function of the desired performance by using a feedback circuit that estimates performance of the amplifier and provides a voltage responsive to the output of the amplifier. Also, integrating the temperature sensor (e.g., 302 in Fig. 38) (Emrick, Figs. 38, 49, ¶0180, ¶0186) with other circuitry provides efficient and accurate temperature control, and the temperature sensor (302) can be used with amplifier in the monolithic device including both control and controlled components.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Preisler/Aitken by forming controlling and controlled circuits including a processor, temperature sensor, and performance sensor as taught by Emrick, wherein the integrated circuit includes the hetero-junction bipolar transistor controlled by the processor to have the structure, further comprising redundant circuitry coupled to a common control circuit, each of the redundant circuitry comprises a performance sensor and a heat sensor coupled to the common control circuit, the performance sensor detects a change in circuit performance of the heterojunction bipolar transistor, the common control circuit receives the circuit performance from the performance sensor, and the heat sensor detects the heat, in order to provide a semiconductor device including controlling and controlled circuits with low loss implementation of control and controlling circuits with maximized application, and with efficient and accurate temperature control; and to allow for more versatile circuit design or operation on one semiconductor structure (Emrick, ¶0037, ¶0186, ¶0228).
The recitation of claim 11 "the common control circuit …governs whether the heat should be applied to anneal defects" is an intended-use recitation. The examiner submits that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Further, Wang teaches forming a current supplying circuit (Wang, Figs. 4A-4B, 5A-5B, Col. 1, lines 7-11; Col. 2, lines 40-67; Cols. 3, lines 1-25; Col. 5, lines 1-28; Col. 7-9) that is adapted to provide an operating current or a repairing current to the poly wire heater (e.g., 531 in Fig. 5B) connected to the heterojunction bipolar transistor to provide heating based on the repairing current to heal and recover the interconnect structures for the HBT transistor, and thus to improve the reliability and lifetime of transistors.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Preisler/Aitken/Emrick by forming a current supplying circuit connected to a control circuit and adapted to provide a repairing current for the HBT transistor as taught by Wang to have the structure, wherein the common control circuit …governs whether the heat should be applied to anneal defects, in order to provide heating based on the repairing current to heal and recover the interconnect structures for the HBT transistor, and thus to improve the reliability and lifetime of transistors (Wang, Col. 1, lines 7-11; Col. 2, lines 40-51; Col. 5, lines 16-29).
Claims 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0109055 to Preisler in view of Aitken (US Patent No. 7,064,414) and Dungan (US 2017/0062595).
With respect to claim 12, Preisler discloses a structure (e.g., SOI heterojunction bipolar transistor (HBT)) (Preisler, Fig. 1, ¶0002, ¶0011-¶0015, ¶0024-¶0041) comprising:
a heterojunction bipolar transistor (e.g., SOI HBT) (Preisler, Fig. 1, ¶0025) integrated with a semiconductor substrate (101);
contact coupled (e.g., through the collector contact/sinker region 202) (Preisler, Fig. 1, ¶0025) to a sub-collector region (e.g., 204/205) of the heterojunction bipolar transistor;
a base region contact (266) (Preisler, Fig. 1, ¶0025) to the heterojunction bipolar transistor; and
an emitter contact (265) to the heterojunction bipolar transistor.
Further, Preisler does not specifically disclose heater terminal contacts which receive a current to generate heat to thermally anneal oxide interface traps; a collector contact to the heterojunction bipolar transistor.
However, Aitken teaches forming heater terminal contacts (e.g., heating contacts 6) (Aitken, Fig. 3, Col. 2, lines 58-64; Col. 3, lines 25-55; Col. 4, lines 44-67; Col. 5, lines 1-4) which receive a current (e.g., voltage suppled form the external power supply) to generate heat to thermally anneal oxide interface traps (e.g., trapped electrical charge in the insulator layer 12) to remove electrical charge buildup from the insulator layer (12) to prevent malfunction of the device. In Aitken, the insulator layer (12) (Aitken, Fig. 3, Col. 3, lines 11-55) is formed under the device layer (5) including active electrical devices (e.g., transistors, resistors), and a heating element (30) connected to the heater terminal contacts (6) is formed under the insulator layer (12), to form a semiconductor structure applicable to any type of circuitry.
Further, Dungan teaches forming a structure (Dungan, Fig. 2, ¶0001-¶0002, ¶0020-¶0021, ¶0022-¶0024, ¶0036-¶0038) comprising multiple HBT transistor fingers, wherein each heterojunction bipolar transistor (HBT) comprises a plurality of contacts (e.g., interconnects 231/232) to the sub-collector (214) and comprised of a copper material that is a thermally conductive material used to provide electrical and thermal conductivity (as heat is generated primarily in the collector region) (Dungan, Fig. 2, ¶0024, ¶0036). In Dungan, the terminal contacts (e.g., interconnects 231/232) comprised of metal structures (231/231b and 232a/232b) including a copper material are positioned on a collector contact (e.g., collector contacts 233 electrically connected to the collector 212) (Dungan, Fig. 2, ¶0023, ¶0026) to the heterojunction bipolar transistor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Preisler by forming a SOI HBT structure including heating contacts to heat a portion of the substrate under the insulator layer as taught by Aitken, wherein the structure includes a plurality of contacts comprised of a thermally conductive material disposed on a collector contact as taught by Dungan to have the structure, comprising: heater terminal contacts which receive a current to generate heat to thermally anneal oxide interface traps; a collector contact to the heterojunction bipolar transistor, in order to remove electrical charge buildup from the insulator layer to prevent malfunction of the device; to provide improved electrical connections to the power semiconductor device generating heat during operation (Aitken, Col. 2, lines 58-64; Col. 3, lines 25-55; Dungan, ¶0001-¶0002, ¶0020-¶0021, ¶0023-¶0024, ¶0036-¶0038).
Regarding claim 16, Preisler in view of Aitken and Dungan discloses the structure of claim 12. Further, Preisler discloses the structure, wherein the collector contact (264) (Preisler, Fig. 1, ¶0025) is provided on a surface of the sub-collector region (e.g., through the collector contact/sinker region 202), but does not specifically disclose that the sub-collector region extends to an upper surface of a bulk semiconductor substrate, and the heater terminal contacts are provided on a surface of the sub-collector region.
However, Dungan teaches forming a structure (Dungan, Fig. 2, ¶0001-¶0002, ¶0020-¶0021, ¶0022-¶0024, ¶0036-¶0038) comprising multiple HBT transistor fingers, wherein each heterojunction bipolar transistor (HBT) comprises a plurality of contacts (e.g., interconnects 231/232) to the sub-collector (214) and comprised of a copper material that is a thermally conductive material used to provide electrical and thermal conductivity (Dungan, Fig. 2, ¶0024), such that terminal contacts (231/232) comprised of a copper material of the multiple HBT transistor fingers and a contact to the collector (e.g., collector contacts 233 electrically connected to the collector 212) (Dungan, Fig. 2, ¶0023, ¶0026) are on the sub-collector region (214), wherein the terminal contacts (e.g., interconnects 231/232) and a contact (233) to the collector are not electrically isolated, and the sub-collector region (214) extends to the heater terminal contacts (231/232).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Preisler/Aitken/Dungan by forming heating terminal contacts of the HBT transistor as taught by Aitken, wherein a plurality of contacts comprised of a thermally conductive material disposed on a collector contact as taught by Dungan to have the structure, wherein the sub-collector region extends to an upper surface of a bulk semiconductor substrate, and the heater terminal contacts are provided on a surface of the sub-collector region, in order to provide improved electrical connections to the power semiconductor device generating heat during operation (Dungan, ¶0001-¶0002, ¶0020-¶0021, ¶0023-¶0024, ¶0036-¶0038).
Claims 14-15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0109055 to Preisler in view of Aitken (US Patent No. 7,064,414) and Dungan (US 2017/0062595) as applied to claim 12 (claim 16), and further in view of Koshino (US Patent No. 4,710,794).
Regarding claims 14 and 15, Preisler in view of Aitken and Dungan discloses the structure of claim 12. Further, Preisler does not specifically disclose the structure, further comprising an airgap below the sub-collector region (as claimed in claim 14); further comprising a non-single crystal semiconductor region below the airgap (as claimed in claim 15).
However, Aitken teaches at least one airgap (35) (Aitken, Fig. 3, Col. 4, lines 44-67; Col. 4, lines 1-4) below the device region (22a), to reduce an amount of power necessary for heating to anneal traps.
Further, Koshino teaches forming an integrated circuit (Koshino, Fig. 2, Col. 1, lines 6-10; Col. 2, lines 5-13; Col. 4, lines 3-28; Col. 5, lines 18-31; Col. 6, lines 56-58) on a substrate including a bipolar transistor, wherein at least one airgap (e.g., air-tightly sealing recess 11) is formed below the bipolar transistor (6) including a collector region, and further comprising a non-single crystal semiconductor region (e.g., polycrystalline silicon 8) is deposited on the inner surfaces of the recesses (11) such that the polycrystalline silicon (8) (Koshino, Fig. 2, Col. 5, lines 18-31; Col. 6, lines 56-58) is disposed below the airgap (11), to provide element isolation with a high breakdown voltage to reliably isolate the semiconductor element and to protect the integrated circuit from the heat generating by the power transistor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Preisler/Aitken/Dungan by forming at least one airgap under the device region as taught by Aitken, wherein an isolation structure including airgap is under a bipolar transistor as taught by Koshino, and wherein the bipolar transistor includes a sub-collector region to have the structure, further comprising at least one airgap below the sub- collector region (as claimed in claim 14); further comprising a non-single crystal semiconductor region below the at least one airgap (as claimed in claim 15), in order to reduce an amount of power necessary for heating to anneal traps; and to provide element isolation with a high breakdown voltage to reliably isolate the semiconductor element and to protect the integrated circuit from the heat generating by the power transistor (Aitken, Fig. 3, Col. 4, lines 44-67; Col. 4, lines 1-4; Koshino, Col. 1, lines 6-10; Col. 2, lines 5-13; Col. 5, lines 18-31; Col. 6, lines 56-58).
Regarding claims 17 and 18, Preisler in view of Aitken and Dungan discloses the structure of claim 16. Further, Preisler does not specifically disclose the structure, further comprising an airgap below the sub-collector region (as claimed in claim 17); further comprising a non-single crystal semiconductor region below the airgap (as claimed in claim 18).
However, Aitken teaches at least one airgap (35) (Aitken, Fig. 3, Col. 4, lines 44-67; Col. 4, lines 1-4) below the device region (22a), to reduce an amount of power necessary for heating to anneal traps.
Further, Koshino teaches forming an integrated circuit (Koshino, Fig. 2, Col. 1, lines 6-10; Col. 2, lines 5-13; Col. 4, lines 3-28; Col. 5, lines 18-31; Col. 6, lines 56-58) on a substrate including a bipolar transistor, wherein at least one airgap (e.g., air-tightly sealing recess 11) is formed below the bipolar transistor (6) including a collector region, and further comprising a non-single crystal semiconductor region (e.g., polycrystalline silicon 8) is deposited on the inner surfaces of the recesses (11) such that the polycrystalline silicon (8) (Koshino, Fig. 2, Col. 5, lines 18-31; Col. 6, lines 56-58) is disposed below the airgap (11), to provide element isolation with a high breakdown voltage to reliably isolate the semiconductor element and to protect the integrated circuit from the heat generating by the power transistor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Preisler/Aitken/Dungan by forming at least one airgap under the device region as taught by Aitken, wherein an isolation structure including airgap is under a bipolar transistor as taught by Koshino, and wherein the bipolar transistor includes a sub-collector region to have the structure, further comprising an airgap below the sub-collector region (as claimed in claim 17); further comprising a non-single crystal semiconductor region below the airgap (as claimed in claim 18), in order to reduce an amount of power necessary for heating to anneal traps; and to provide element isolation with a high breakdown voltage to reliably isolate the semiconductor element and to protect the integrated circuit from the heat generating by the power transistor (Aitken, Fig. 3, Col. 4, lines 44-67; Col. 4, lines 1-4;Koshino, Col. 1, lines 6-10;Col. 2, lines 5-13;Col. 5, lines 18-31; Col. 6, lines 56-58).
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 5-12, and 14-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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