DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/27/2026 has been entered.
Response to Amendment
Applicant’s amendment filed on 4/27/2026 is acknowledged. Claims 7, 32, and 39 have been amended.
Response to Arguments
Applicant’s arguments with respect to claims 7-15, 32-42 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8, 11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US 2019/0074211 A1) in view of Ko et al. (US 2021/0335670 A1).
Regarding claim 7, Min teaches a method (method of forming the gate isolation structure in Fig. 9 as shown in Figs. 11A-20B of Min), comprising:
forming a plurality of fins (AF in Fig. 11A of Min) from a semiconductor substrate (101);
forming isolation regions (105) around each fin of the plurality of fins;
depositing a gate electrode (DG in Fig. 11B) over the plurality of fins;
forming an opening (trench T in Fig. 12B of Min) in the gate electrode;
depositing a first dielectric material (141 in Fig. 13A-B), wherein a void (V0/V0’ in Fig. 13B) is formed in the first dielectric material;
removing a portion (portion of dielectric 141 in the recess R is removed, as shown in Fig. 14B) of the first dielectric material to expose the void; and
depositing a second dielectric material (150 in Fig. 15B) in the void.
But Min does not teach that the method comprising: depositing a first liner in the opening, wherein the first liner comprises a first portion disposed on a bottom of the opening and a second portion disposed on a sidewall of the opening; the first dielectric material is deposited on the liner, and the first portion of the first liner is disposed between the first dielectric material and the bottom of the opening.
Ko teaches an isolation structure (50-54 in Fig. 8A-8B of Ko) that comprises a liner (54’) disposed on a bottom and sidewalls of the trench and a dielectric fill layer (54) on the liner.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the liner in the opening before forming the first dielectric of Min, as disclosed by Ko, in order to improve the isolation property of the gate/fin cut structure.
Regarding claim 8, Min in view of Ko teaches all limitations of the method of claim 7, and also teaches wherein the first liner is deposited by atomic layer deposition (as described in [0031] of Ko).
Regarding claim 11, Min in view of Ko teaches all limitations of the method of claim 7, and further comprising forming a mask structure (M in Fig. 11B of Min) over the gate electrode, wherein the opening is formed in the mask structure (see Fig. 11B of Min).
Regarding claim 15, Min in view of Ko teaches all limitations of the method of claim 7, and also teaches wherein the removing the portion of the first dielectric material is performed by a second planarization process (as described in [0029] of Ko).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Min in view of Ko, as applied to claim 8 above, and further in view of Lin et al. (US 2021/0335674 A1) (hereinafter referred to as Lin’674).
Regarding claim 9, Min in view of Ko teaches all limitations of the method of claim 8, but does not teach wherein first dielectric material is deposited by flowable chemical vapor deposition.
Lin’674 teaches a gate isolation structure where dielectric material is deposited into the isolation trench by a flowable CVD ([0078] of Lin’674).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the first dielectric material of Min-Ko using Lin’674’s flowable CVD in order to reduce stress on the surrounding structure.
Regarding claim 10, Min-Ko-Lin’674 teaches all limitations of the method of claim 9, and also teaches wherein the second dielectric material is deposited by atomic layer deposition (as described in [0038] of Min).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Min in view of Ko, as applied to claim 7 above, and further in view of Kumar et al. (US 2003/0129840 A1).
Regarding claim 12, Min in view of Ko teaches all limitations of the method of claim 11, but does not teach wherein the mask structure comprises one or more layers.
Kumar teaches a multilayer mask (12-20 in Fig. 1 of Kumar) used in etching step. The multilayer mask comprises: a lower silicon nitride layer (14); a silicon layer (18); and an antireflective coating (20).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used Kumar’s multilayer mask in order to have increased the resolution of the mask.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Min in view of Ko and Kumar, as applied to claim 12 above, and further in view of Huang et al. (US 10032640 B1).
Regarding claim 13, Min in view of Ko teaches all limitations of the method of claim 12, and also teaches wherein the one or more layers include a first SiN layer (as described in [0016] of Huang above), a second SiN layer, and a silicon layer (18 as described in [0016] of Huang)
But Min-Ko-Kumar does not teach that one or more layers include a second SiN layer, and the silicon layer is disposed between the first and second SiN layers.
Huang teaches that anti-reflective coating layer (106 in Fig. 1G of Huang) in a multilayer mask (103-107) is typically made of material such as silicon nitride (106 can be made of different material such as oxide or metal nitride, however, silicon nitride is preferred due to its robustness and chemical stability).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used silicon nitride as the anti-reflective coating in Kumar for its chemical stability and strong mechanical properties.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Min in view of Ko, as applied to claim 7 above, and further in view of Lin et al. (US 2021/0126109 A1).
Regarding claim 14, Min in view of Ko teaches all limitations of the method of claim 7, but does not teach the method further comprising performing a first planarization process to expose the gate electrode.
Lin teaches a finFET structure with an ILD (48 in Fig. 6 of Lin) covering the fin and gate structure (30). Lin discloses a planarization process is performed to level to top surface of the gate structure and the ILD (see [0027] of Lin).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have performed a planarization as disclosed by Lin in order to obtain a level surface. This is a typical method to have coplanar top surfaces.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Min in view of Ko.
Regarding claim 32, Min teaches a method (method of forming the gate isolation structure in Fig. 9 as shown in Figs. 11A-20B of Min), comprising:
forming a fin (AF in Fig. 11A of Min) from a semiconductor substrate (101);
forming an isolation region (105) around the fin;
depositing a gate electrode (DG in Fig. 11B) over the fin;
forming an opening (trench T in Fig. 12B of Min) in the gate electrode to expose a portion of the semiconductor substrate, wherein the opening has a first aspect ratio (aspect ratio of the trench T);
depositing a first dielectric material (141 in Fig. 13A-B) in the opening, wherein a void (V0/V0’ in Fig. 13B) is formed in the first dielectric material;
removing a portion (portion of dielectric 141 in the recess R is removed, as shown in Fig. 14B) of the first dielectric material to expose the void; and
depositing a second dielectric material (150 in Fig. 15B) on the first dielectric material.
But Min does not teach that the method comprising: depositing a liner in the opening, wherein the opening has a second aspect ratio smaller than the first aspect ratio, and the liner comprises a first portion disposed on a bottom of the opening and a second portion disposed on a sidewall of the opening, and the first portion of the liner is disposed between the first dielectric material and the bottom of the opening.
Ko teaches an isolation structure (50-54 in Fig. 8A-8B of Ko) that comprises a liner (54’) disposed on a bottom and sidewalls of the trench and a dielectric fill layer (54) on the liner.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the liner in the opening before forming the first dielectric of Min, as disclosed by Ko, in order to improve the isolation property of the gate/fin cut structure.
As incorporated, since a uniform thickness liner (54’ of Ko) is formed on the bottom and sidewalls of the opening (trench T of Min), the width of the trench is reduced by an amount twice as large as the depth of the trench T. Thus, the second aspect ratio of the opening (trench T of Min) is then smaller than the first aspect ratio (before deposition of the liner).
Claims 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Min in view of Ko, and further in view of Wang et al. (US 2021/0343709 A1).
Regarding claim 33, Min in view of Ko teaches all limitations of the method of claim 32, but does not teach wherein the liner comprises SiN.
Wang teaches an isolation structure (103/104 in Fig. 1A-1E of Wang) having a silicon nitride liner (103A/104A) and an oxide fill (103B/104B; see [0036] of Wang).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have selected SiN as material for liner, and oxide for dielectric fill, in order to have better material match with other surrounding dielectric materials (such as ILD…) while maintaining mechanical strength of the silicon nitride.
Regarding claim 34, Min-Ko-Wang teaches all limitations of the method of claim 33, and also teaches wherein the liner is deposited by an atomic layer deposition process ([0045] of Wang discloses that SiN layers are deposited using ALD method).
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Min in view of Ko and Wang, as applied to claim 34 above, and further in view of Tsai et al. (US 2019/0164839 A1).
Regarding claim 35, Min-Ko-Wang teaches all limitations of the method of claim 34, but does not teach wherein the first dielectric material comprises a low-k dielectric material.
Tsai teaches that a low-k material is used to form a gate cut structure (270 in Fig. 7B and [0033] of Tsai).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the first dielectric material from low-k dielectric material as disclosed by Tsai in order to have better isolation.
Claim 36-38 are rejected under 35 U.S.C. 103 as being unpatentable over Min in view of Ko, Wang, Tsai, as applied to claim 35 above, and further in view of Liaw et al. (US 2021/0202498 A1).
Regarding claim 36, Min-Ko-Wang teaches all limitations of the method of claim 35, but does not teach wherein the first dielectric material is deposited by a flowable chemical vapor deposition process.
Liaw teaches that low-k dielectric material can be deposited using a flowable CVD method ([0069] of Liaw. Both spin-on-glass and flowable CVD are disclosed but FCVD is preferred due to its high-volume scalability and consistent quality and conformity for complicated structure).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the first dielectric material using flowable CVD process in order to have a consistent quality and conformity while capable of high-volume scalability.
Regarding claim 37, Min-Ko-Wang-Tsai-Liaw teaches all limitations of the method of claim 36, and also teaches wherein the second dielectric material comprises a same material as the liner (as stated in [0038] of Min, 150 is SiN).
Regarding claim 38, Min-Ko-Wang-Tsai-Liaw teaches all limitations of the method of claim 37, and also teaches where the second dielectric material is deposited by an atomic layer deposition process (as stated in [0038] of Min).
Claims 39-41 are rejected under 35 U.S.C. 103 as being unpatentable over Min in view of Ko, Wang, Tsai and Liaw.
Regarding claim 39, Min teaches a method (method of forming the gate isolation structure in Fig. 9 as shown in Figs. 11A-20B of Min), comprising:
forming a fin (AF in Fig. 11A of Min) from a semiconductor substrate (101);
forming an isolation region (105) around the fin;
depositing a gate electrode (DG in Fig. 11B) over the fin;
forming an opening (trench T in Fig. 12B of Min) in the gate electrode;
depositing a first dielectric material (141 in Fig. 13A-B) in the opening, wherein a void (V0/V0’ in Fig. 13B) is formed in the first dielectric material;
removing a portion (portion of dielectric 141 in the recess R is removed, as shown in Fig. 14B) of the first dielectric material to expose the void; and
depositing a second dielectric material (150 in Fig. 15B) on the first dielectric material.
But Min does not teach that the method comprising: depositing a liner in the opening, wherein the liner comprises a first material and is deposited by an atomic layer deposition process, and the liner has a first portion disposed on a bottom of the opening and a second portion disposed on a sidewall of the opening; the first portion of the liner is disposed between the first dielectric material and the bottom of the opening, the first dielectric material comprises a second material different from the first material, and the second material is deposited by flowable chemical vapor deposition process; wherein the second dielectric material comprises a same material as the liner.
Ko teaches an isolation structure (50-54 in Fig. 8A-8B of Ko) that comprises a liner (54’) disposed on a bottom and sidewalls of the trench and a dielectric fill layer (54) on the liner.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the liner in the opening before forming the first dielectric of Min, as disclosed by Ko, in order to improve the isolation property of the gate/fin cut structure.
As incorporated, the liner 54’ of Ko would have a first portion disposed on a bottom of the opening (trench T of Ko) and a second portion disposed on a sidewall of the opening, and the first portion of the liner is disposed between the first dielectric material and the bottom of the opening.
But Min in view of Ko does not teach that wherein the liner comprises a first material and is deposited by an atomic layer deposition process, the first dielectric material comprises a second material different from the first material, and the second material is deposited by flowable chemical vapor deposition process; wherein the second dielectric material comprises a same material as the liner.
Wang teaches an isolation structure (103/104 in Fig. 1A-1E of Wang) having a silicon nitride liner (103A/104A) and an oxide fill (103B/104B; see [0036] of Wang).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have selected SiN as material for liner, and oxide for dielectric fill, in order to have better material match with other surrounding dielectric materials (such as ILD…) while maintaining mechanical strength of the silicon nitride.
As incorporated, the liner and the second dielectric material are made of SiN (as stated in [0038] of Min, 150 is also SiN), while the first dielectric material is made of silicon oxide. The liner is deposited by ALD method ([0045] of Wang).
But Min-Ko-Wang does not teach that the second material is deposited by flowable chemical vapor deposition process.
Tsai teaches that a low-k material is used to form a gate cut structure (270 in Fig. 7B and [0033] of Tsai).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the first dielectric material from low-k dielectric material as disclosed by Tsai in order to have better isolation.
But Min-Ko-Wang-Tsai does not teach that the second material is deposited by flowable chemical vapor deposition process.
Liaw teaches that low-k dielectric material can be deposited using a flowable CVD method ([0069] of Liaw. Both spin-on-glass and flowable CVD are disclosed but FCVD is preferred due to its high-volume scalability and consistent quality and conformity for complicated structure).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the first dielectric material using flowable CVD process in order to have a consistent quality and conformity while capable of high-volume scalability.
Regarding claim 40, Min-Ko-Wang-Tsai-Liaw teaches all limitations of the method of claim 39, and further comprising depositing a gate dielectric layer (gate dielectric layer is implicit in a gate structure) over the fin, wherein the gate electrode is deposited over the gate dielectric layer.
Regarding claim 41, Min-Ko-Wang-Tsai-Liaw teaches all limitations of the method of claim 40, but does not teach that the method further comprising depositing one or more conformal layers on the gate dielectric layer, wherein the gate electrode is deposited on the one or more conformal layers.
Tsai teaches a method of forming a gate isolation structure in which the dummy gate structure is replaced by a metal gate structure first, then the metal gate structure is cut (see [0038] of Tsai). Tsai also discloses that the metal gate structure typically has work function metal layer (see [0022] of Tsai).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate isolation structure of Min after the replacement gate process in order to make sure the functional gate structures are cut and completely isolated, and to have formed work function layers as disclosed by Tsai in order to improve the performance of the gate structures.
Allowable Subject Matter
Claim 42 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 42, the prior art of record does not disclose or fairly suggest a method of forming an isolation structure “wherein the opening is formed through the gate electrode, the one or more conformal layers, and the gate dielectric layer” along with other limitations of claim 41.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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