DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment filed on 8/4/2026 is acknowledged. Claims 7, 32, 38-39 have been amended. Claims 40-42 are canceled. Claims 43-45 are added.
Response to Arguments
Due to the discovery of the reference Anderson et al. (US 9373641 B2) and Wang et al. (US 2021/0343709 A1), the allowability of the previous claim 42 is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8, 11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US 2016/0056181 A1) in view of Min et al. (US 2019/0074211 A1) and Ko et al. (US 2021/0335670 A1).
Regarding claim 7, Anderson teaches a method (method in Fig. 1, and Figs. 2A-12 of Anderson), comprising:
forming a plurality of fins (210.1-210.2 of Fig. 2A) from a semiconductor substrate (202);
forming isolation regions (STI described in [0068]) around each fin of the plurality of fins;
depositing a gate dielectric layer (231 in Fig. 7A of Anderson) over the plurality of fins;
depositing one or more conformal layers (work function layers 232) on the gate dielectric layer;
depositing a gate electrode (233) over the plurality of fins, wherein the gate electrode is deposited over the gate dielectric layer and on the one or more conformal layers (as shown in Fig. 7A);
forming an opening (245 in Fig. 8A) in the gate electrode, wherein the opening is formed through the gate electrode, the one or more conformal layers, and the gate dielectric layer (as shown in Fig. 8A of Anderson);
depositing a first dielectric material (241 in Fig. 10A).
But Anderson does not teach that the method comprising: depositing a first liner in the opening, wherein the first liner comprises a first portion disposed on a bottom of the opening and a second portion disposed on a sidewall of the opening; the first dielectric material is deposited on the liner, wherein a void is formed in the first dielectric material, and the first portion of the first liner is disposed between the first dielectric material and the bottom of the opening; removing a portion of the first dielectric material to expose the void; and depositing a second dielectric material in the void.
Min teaches a method (method of forming the gate isolation structure in Fig. 9 as shown in Figs. 11A-20B of Min), comprising: forming a plurality of fins (AF in Fig. 11A of Min) from a semiconductor substrate (101); forming isolation regions (105) around each fin of the plurality of fins; depositing a gate electrode (DG in Fig. 11B) over the plurality of fins; forming an opening (trench T in Fig. 12B of Min) in the gate electrode; depositing a first dielectric material (141 in Fig. 13A-B), wherein a void (V0/V0’ in Fig. 13B) is formed in the first dielectric material; removing a portion (portion of dielectric 141 in the recess R is removed, as shown in Fig. 14B) of the first dielectric material to expose the void; and depositing a second dielectric material (150 in Fig. 15B) in the void.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the void in the isolation structure as according to Min in order to have better isolation structure between gate structures.
But Anderson in view of Min does not teach that the method comprising: depositing a first liner in the opening, wherein the first liner comprises a first portion disposed on a bottom of the opening and a second portion disposed on a sidewall of the opening; the first dielectric material is deposited on the liner.
Ko teaches a method of forming a gate isolation structure (see Figs. 8A-14 of Ko). The method comprises: forming a trench (trench of the gate isolation structure 54 in Figs. 8A-8B) through a gate stack (30 in Fig. 8A-8B); depositing a first liner (liner 54’ in Fig. 8B of Ko) in the opening, wherein the first liner comprises a first portion (portion of liner 54’ at the bottom of the trench) disposed on a bottom of the opening and a second portion (portion of liner 54’ on the sidewall of the trench) disposed on a sidewall of the opening; a first dielectric material (dielectric material 54 in Fig. 8B and [0031] of Ko) is deposited on the liner, and the first portion of the first liner is disposed between the first dielectric material and the bottom of the opening (as shown in Fig. 13 of Ko).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the liner in the opening before forming the first dielectric of Anderson-Min, as disclosed by Ko, in order to improve the isolation property and mechanical strength of the gate isolation structure.
Regarding claim 8, Anderson-Min-Ko teaches all limitations of the method of claim 7, and also teaches wherein the first liner is deposited by atomic layer deposition (as described in [0031] of Ko).
Regarding claim 11, Anderson-Min-Ko teaches all limitations of the method of claim 7, and further comprising forming a mask structure (M in Fig. 11B of Min) over the gate electrode, wherein the opening is formed in the mask structure.
Regarding claim 15, Anderson-Min-Ko teaches all limitations of the method of claim 7, and also teaches wherein the removing the portion of the first dielectric material is performed by a second planarization process (as described in [0029] of Ko).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson in view of Min and Ko, as applied to claim 8 above, and further in view of Lin et al. (US 2021/0335674 A1) (hereinafter referred to as Lin’674).
Regarding claim 9, Anderson-Min-Ko teaches all limitations of the method of claim 8, but does not teach wherein first dielectric material is deposited by flowable chemical vapor deposition.
Lin’674 teaches a gate isolation structure where dielectric material is deposited into the isolation trench by a flowable CVD ([0078] of Lin’674).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the first dielectric material of Min-Ko using Lin’674’s flowable CVD in order to reduce stress on the surrounding structure.
Regarding claim 10, Anderson-Min-Ko-Lin’674 teaches all limitations of the method of claim 9, and also teaches wherein the second dielectric material is deposited by atomic layer deposition (as described in [0038] of Min).
Claim 12 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson in view of Min and Ko, as applied to claim 11 above, and further in view of Kumar et al. (US 2003/0129840 A1).
Regarding claim 12, Anderson-Min-Ko teaches all limitations of the method of claim 11, but does not teach wherein the mask structure comprises one or more layers.
Kumar teaches a multilayer mask (12-20 in Fig. 1 of Kumar) used in etching step. The multilayer mask comprises: a lower silicon nitride layer (14); a silicon layer (18); and an antireflective coating (20).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used Kumar’s multilayer mask in order to have increased the resolution of the mask.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Anderson in view of Min, Ko and Kumar, as applied to claim 12 above, and further in view of Huang et al. (US 10032640 B1).
Regarding claim 13, Anderson-Min-Ko teaches all limitations of the method of claim 12, and also teaches wherein the one or more layers include a first SiN layer (as described in [0016] of Huang above), and a silicon layer (18 as described in [0016] of Huang) disposed between the first and second SiN layers.
But Anderson-Min-Ko does not teach that one or more layers include a second SiN layer, and the silicon layer is disposed between the first and second SiN layers.
Huang teaches that anti-reflective coating layer (106 in Fig. 1G of Huang) in a multilayer mask (103-107) is typically made of material such as silicon nitride (106 can be made of different material such as oxide or metal nitride, however, silicon nitride is preferred due to its robustness and chemical stability).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used silicon nitride as the anti-reflective coating in Kumar for its chemical stability and strong mechanical properties.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Anderson in view of Min and Ko, as applied to claim 7 above, and further in view of Lin et al. (US 2021/0126109 A1).
Regarding claim 14, Anderson-Min-Ko teaches all limitations of the method of claim 7, but does not teach the method further comprising performing a first planarization process to expose the gate electrode.
Lin teaches a finFET structure with an ILD (48 in Fig. 6 of Lin) covering the fin and gate structure (30). Lin discloses a planarization process is performed to level to top surface of the gate structure and the ILD (see [0027] of Lin).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have performed a planarization as disclosed by Lin in order to obtain a level surface. This is a typical method to have coplanar top surfaces.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Anderson in view of Min and Ko.
Regarding claim 32, Anderson teaches a method (method in Fig. 1, and Figs. 2A-12 of Anderson), comprising:
forming a fin (210.1-210.2 of Fig. 2A) from a semiconductor substrate (202);
forming an isolation region (STI described in [0068]) around the fin;
depositing a gate dielectric layer (231 in Fig. 7A of Anderson) over the fin;
depositing one or more conformal layers (work function layers 232) on the gate dielectric layer;
depositing a gate electrode (233) over the fin, wherein the gate electrode is deposited over the gate dielectric layer and on the one or more conformal layers (as shown in Fig. 7A);
forming an opening (245 in Fig. 8A) in the gate electrode to expose a portion of the semiconductor substrate, wherein the opening has a first aspect ratio (aspect ratio of the trench 245), and the opening is formed through the gate electrode, the one or more conformal layers, and the gate dielectric layer (as shown in Fig. 8A);
depositing a first dielectric material (241 in Fig. 10A) in the opening.
But Anderson does not teach that the method comprising: depositing a liner in the opening, wherein the opening has a second aspect ratio smaller than the first aspect ratio, and the liner comprises a first portion disposed on a bottom of the opening and a second portion disposed on a sidewall of the opening; wherein a void is formed in the first dielectric material, and the first portion of the liner is disposed between the first dielectric material and the bottom of the opening; removing a portion of the first dielectric material to expose the void; and depositing a second dielectric material on the first dielectric material.
Min teaches a method (method of forming the gate isolation structure in Fig. 9 as shown in Figs. 11A-20B of Min), comprising: forming a plurality of fins (AF in Fig. 11A of Min) from a semiconductor substrate (101); forming isolation regions (105) around each fin of the plurality of fins; depositing a gate electrode (DG in Fig. 11B) over the plurality of fins; forming an opening (trench T in Fig. 12B of Min) in the gate electrode; depositing a first dielectric material (141 in Fig. 13A-B), wherein a void (V0/V0’ in Fig. 13B) is formed in the first dielectric material; removing a portion (portion of dielectric 141 in the recess R is removed, as shown in Fig. 14B) of the first dielectric material to expose the void; and depositing a second dielectric material (150 in Fig. 15B) in the void.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the void in the isolation structure as according to Min in order to have better isolation structure between gate structures.
But Anderson in view of Min does not teach that the method comprising: depositing a liner in the opening, wherein the opening has a second aspect ratio smaller than the first aspect ratio, and the liner comprises a first portion disposed on a bottom of the opening and a second portion disposed on a sidewall of the opening.
Ko teaches a method of forming a gate isolation structure (see Figs. 8A-14 of Ko). The method comprises: forming a trench (trench of the gate isolation structure 54 in Figs. 8A-8B) through a gate stack (30 in Fig. 8A-8B); depositing a first liner (liner 54’ in Fig. 8B of Ko) in the opening, wherein the first liner comprises a first portion (portion of liner 54’ at the bottom of the trench) disposed on a bottom of the opening and a second portion (portion of liner 54’ on the sidewall of the trench) disposed on a sidewall of the opening; a first dielectric material (dielectric material 54 in Fig. 8B and [0031] of Ko) is deposited on the liner, and the first portion of the first liner is disposed between the first dielectric material and the bottom of the opening (as shown in Fig. 13 of Ko).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the liner in the opening before forming the first dielectric of Anderson-Min, as disclosed by Ko, in order to improve the isolation property and mechanical strength of the gate isolation structure.
Claims 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson in view of Min and Ko, and further in view of Wang et al. (US 2021/0343709 A1).
Regarding claim 33, Anderson-Min-Ko teaches all limitations of the method of claim 32, but does not teach wherein the liner comprises SiN.
Wang teaches an isolation structure (103/104 in Fig. 1A-1E of Wang) having a silicon nitride liner (103A/104A) and an oxide fill (103B/104B; see [0036] of Wang).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have selected SiN as material for liner, and oxide for dielectric fill, in order to have better material match with other surrounding dielectric materials (such as ILD…) while maintaining mechanical strength of the silicon nitride.
Regarding claim 34, Anderson-Min-Ko-Wang teaches all limitations of the method of claim 33, and also teaches wherein the liner is deposited by an atomic layer deposition process ([0045] of Wang discloses that SiN layers are deposited using ALD method).
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Anderson in view of Min, Ko and Wang, and further in view of Tsai et al. (US 2019/0164839 A1).
Regarding claim 35, Anderson-Min-Ko-Wang teaches all limitations of the method of claim 34, but does not teach wherein the first dielectric material comprises a low-k dielectric material.
Tsai teaches that a low-k material is used to form a gate cut structure (270 in Fig. 7B and [0033] of Tsai).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the first dielectric material from low-k dielectric material as disclosed by Tsai in order to have better isolation.
Claims 36-38 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson in view of Min, Ko, Wang and Tsai, and further in view of Liaw et al. (US 2021/0202498 A1).
Regarding claim 36, Anderson-Min-Ko-Wang-Tsai teaches all limitations of the method of claim 35, but does not teach wherein the first dielectric material is deposited by a flowable chemical vapor deposition process.
Liaw teaches that low-k dielectric material can be deposited using a flowable CVD method ([0069] of Liaw. Both spin-on-glass and flowable CVD are disclosed but FCVD is preferred due to its high-volume scalability and consistent quality and conformity for complicated structure).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the first dielectric material using flowable CVD process in order to have a consistent quality and conformity while capable of high-volume scalability.
Regarding claim 37, Anderson-Min-Ko-Wang-Tsai-Liaw teaches all limitations of the method of claim 36, and also teaches wherein the second dielectric material comprises a same material as the liner (as stated in [0038] of Min, 150 is SiN).
Regarding claim 38, Anderson-Min-Ko-Wang-Tsai-Liaw teaches all limitations of the method of claim 37, and also teaches wherein the second dielectric material is deposited by an atomic layer deposition process (as stated in [0038] of Min).
Claims 39, 43-45 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson in view of Min, Ko, Wang and Tsai, and Liaw.
Regarding claim 39, Anderson teaches a method (method in Fig. 1, and Figs. 2A-12 of Anderson), comprising:
forming a fin (210.1-210.2 of Fig. 2A) from a semiconductor substrate (202);
forming an isolation region (STI described in [0068]) around the fin;
depositing a gate dielectric layer (231 in Fig. 7A of Anderson) over the fin;
depositing one or more conformal layers (work function layers 232) on the gate dielectric layer;
depositing a gate electrode (233 in Fig. 7A) over the fin, wherein the gate electrode is deposited over the gate dielectric layer and on the one or more conformal layers;
forming an opening (245 in Fig. 8A) in the gate electrode, wherein the opening is formed through the gate electrode, the one or more conformal layers, and the gate dielectric layer (as shown in Fig. 8A);
depositing a first dielectric material (241 in Fig. 10A) in the opening.
But Anderson does not teach that wherein a void is formed in the first dielectric material, the first portion of the liner is disposed between the first dielectric material and the bottom of the opening, the first dielectric material comprises a second material different from the first material, and the second material is deposited by flowable chemical vapor deposition process; and that the method comprising: depositing a liner in the opening, wherein the liner comprises a first material and is deposited by an atomic layer deposition process, and the liner has a first portion disposed on a bottom of the opening and a second portion disposed on a sidewall of the opening; removing a portion of the first dielectric material to expose the void; and depositing a second dielectric material on the first dielectric material, wherein the second dielectric material comprises a same material as the liner.
Min teaches a method (method of forming the gate isolation structure in Fig. 9 as shown in Figs. 11A-20B of Min), comprising: forming a plurality of fins (AF in Fig. 11A of Min) from a semiconductor substrate (101); forming isolation regions (105) around each fin of the plurality of fins; depositing a gate electrode (DG in Fig. 11B) over the plurality of fins; forming an opening (trench T in Fig. 12B of Min) in the gate electrode; depositing a first dielectric material (141 in Fig. 13A-B), wherein a void (V0/V0’ in Fig. 13B) is formed in the first dielectric material; removing a portion (portion of dielectric 141 in the recess R is removed, as shown in Fig. 14B) of the first dielectric material to expose the void; and depositing a second dielectric material (150 in Fig. 15B) in the void.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the void in the isolation structure as according to Min in order to have better isolation structure between gate structures.
But Anderson in view of Min does not teach that the second material is deposited by flowable chemical vapor deposition process; and that the method comprising: depositing a liner in the opening, wherein the liner comprises a first material and is deposited by an atomic layer deposition process, and the liner has a first portion disposed on a bottom of the opening and a second portion disposed on a sidewall of the opening; wherein the second dielectric material comprises a same material as the liner.
Ko teaches an isolation structure (50-54 in Fig. 8A-8B of Ko) that comprises a liner (54’) disposed on a bottom and sidewalls of the trench and a dielectric fill layer (54) on the liner.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the liner in the opening before forming the first dielectric of Anderson-Min, as disclosed by Ko, in order to improve the isolation property and mechanical strength of the gate isolation structure.
As incorporated, the liner 54’ of Ko would have a first portion disposed on a bottom of the opening (trench T of Ko) and a second portion disposed on a sidewall of the opening, and the first portion of the liner is disposed between the first dielectric material and the bottom of the opening.
But Anderson-Min-Ko does not teach that the second material is deposited by flowable chemical vapor deposition process; and that the method comprising: depositing a liner in the opening, wherein the liner comprises a first material and is deposited by an atomic layer deposition process; wherein the second dielectric material comprises a same material as the liner.
Wang teaches an isolation structure (103/104 in Fig. 1A-1E of Wang) having a silicon nitride liner (103A/104A) and an oxide fill (103B/104B; see [0036] of Wang).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have selected SiN as material for liner, and oxide for dielectric fill, in order to have better material match with other surrounding dielectric materials (such as ILD…) while maintaining mechanical strength of the silicon nitride.
As incorporated, the liner and the second dielectric material are made of SiN (as stated in [0038] of Min, 150 is also SiN), while the first dielectric material is made of silicon oxide. The liner is deposited by ALD method ([0045] of Wang).
But Anderson-Min-Ko-Wang does not teach that the second material is deposited by flowable chemical vapor deposition process.
Tsai teaches that a low-k material is used to form a gate cut structure (270 in Fig. 7B and [0033] of Tsai).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the first dielectric material from low-k dielectric material as disclosed by Tsai in order to have better isolation.
But Anderson-Min-Ko-Wang-Tsai does not teach that the second material is deposited by flowable chemical vapor deposition process.
Liaw teaches that low-k dielectric material can be deposited using a flowable CVD method ([0069] of Liaw. Both spin-on-glass and flowable CVD are disclosed but FCVD is preferred due to its high-volume scalability and consistent quality and conformity for complicated structure).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the first dielectric material using flowable CVD process in order to have a consistent quality and conformity while capable of high-volume scalability.
Regarding claim 43, Anderson-Min-Ko-Wang-Tsai-Liaw teaches all limitations of the method of claim 39, and also teaches where the second dielectric material is deposited by an atomic layer deposition process (as described in [0038] of Min).
Regarding claim 44, Anderson-Min-Ko-Wang-Tsai-Liaw teaches all limitations of the method of claim 39, and also teaches wherein the liner comprises SiN (as taught by Wang above).
Regarding claim 45, Anderson-Min-Ko-Wang-Tsai-Liaw teaches all limitations of the method of claim 39, and also teaches wherein the first dielectric material comprises a low-k dielectric material (as taught by Tsai above).
Conclusion
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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