DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 01/26/2026. Claims 14-17, 19-22 and 24-35 are pending for this examination.
Response to Arguments
Applicant’s reply filed on 01/26/2026 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Thus, this rejection is properly made FINAL.
Election/Restrictions
Applicant’s election, without traverse group II, Species I, directed to an embodiment as depicted in FIGS. [1A-1B], with claims 8-27, in the “Response to Election / Restriction Filed” filed on 07/03/2025 is acknowledged.
However, the features of newly added claim 28 “forming a first oxide film with high dielectric constant on a substrate, a thickness of the first oxide film is less than a thickness to be crystallized” does not support elected species I, (Figure. [1A-1B]), Therefore, claim 28 is withdrawn.
Claims 29-35 are withdrawn based on the dependency of claim 28.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over OKAMOTO et al (US 2019/0074174 A1; hereafter OKAMOTO) in view of LEE et al (US 2021/0405498 A1; hereafter LEE) and further in view of Cho et al (US 2015/0357399 A1; hereafter Cho).
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Regarding claim 14. OKAMOTO discloses a method for suppressing a generation of leakage current for a gate insulating layer (Fig 1, gate insulating film GI, Para [ 0088-0090]), the gate insulating layer comprising multilayer oxide films stacked on each other (Fig 1, gate insulating film GI includes GIa-GId, Para [ 0088-0090]), the method for suppressing the generation of leakage current (Fig 1, Para [ 0088-0090]) comprising
forming at least one oxide interface layer (layer GIb, made with silicon oxide, Para [ 0088-0090]) between two adjacent layers of the multilayer oxide films ( GIa/GIc made with Al.sub.2O.sub.3 films, Para [ 0088-0090]), wherein a thickness of each layer of the oxide films is less than 30 angstroms ( Para [ 0108] discloses “ aluminum oxide film (a-Al.sub.2O.sub.3, c-Al.sub.2O.sub.3 is about 5 nm in this case, the thickness can be adjusted within a range from 2 to 20 nm”, GIb/Gid layers). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). "[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). >See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
But OKAMOTO does not disclose explicitly amorphous oxide interface layer and a number of layers of the oxide films is greater than or equal to 3, a number of layers of the amorphous oxide interface layer is greater than 2 or equal to 2 and a dielectric constant of the amorphous oxide interface layer is lower than a dielectric constant of the oxide films.
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In a similar field of endeavor, LEE discloses amorphous oxide interface layer (Fig 1, crystallization preventing layer 13 include amorphous silicon oxide, Para [ 0078-0079]), and a number of layers of the oxide films is greater than or equal to 3 (Fig 1, dielectric layers 12, Para [ 0078-0079]), a number of layers of the amorphous oxide interface layer is greater than 2 or equal to 2 (Fig 1, crystallization preventing layer 13 include amorphous silicon oxide, Para [ 0078-0079]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine OKAMOTO in light of LEE teaching “amorphous oxide interface layer (Fig 1, crystallization preventing layer 13 include amorphous silicon oxide, Para [ 0078-0079]), and a number of layers of the oxide films is greater than or equal to 3 (Fig 1, dielectric layers 12, Para [ 0078-0079]), a number of layers of the amorphous oxide interface layer is greater than 2 or equal to 2 (Fig 1, crystallization preventing layer 13 include amorphous silicon oxide, Para [ 0078-0079])” for further advantage such as simplify manufacturing process by using well know deposition methods.
But OKAMOTO in light of LEE do not disclose explicitly wherein a dielectric constant of the interface layer is lower than a dielectric constant of the oxide films.
In a similar field of endeavor, Cho discloses wherein a dielectric constant of the interface layer is lower than a dielectric constant of the oxide films (Para [ 0004, 0097]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine OKAMOTO and LEE in light of Cho teaching “wherein a dielectric constant of the interface layer is lower than a dielectric constant of the oxide films (Para [ 0004, 0097])” for further advantage such as to reduce the leakage current.
Regarding claim 15. OKAMOTO, LEE and Cho disclose the method according to claim 14, OKAMOTO further discloses wherein a material of the interface layer comprises silicon oxide (SiOx) (layer GIb, made with silicon oxide, Para [ 0088-0090]).
Regarding claim 16. OKAMOTO, LEE and Cho disclose the method according to claim 14, Cho further discloses wherein a thickness of the interface layer is less than or equal to 2 angstroms (Para [ 0004-0008] discloses “the second dielectric layer may have a thickness of about 3 Å to about 30 Å”.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine OKAMOTO and LEE in light of Cho teaching “wherein a thickness of the interface layer is less than or equal to 2 angstroms (Para [ 0004-0008] discloses “the second dielectric layer may have a thickness of about 3 Å to about 30 Å”. Therefore, it is obvious that, amorphous oxide layer can have thickness 2 angstroms)” for further advantage such as to reduce the leakage current.
In addition, Applicant has not presented persuasive evidence that the claimed “a thickness of the interface layer is less than or equal to 2 angstroms” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed thickness). Also, the applicant has not shown that the claimed amorphous oxide layer thickness 2 angstroms produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. It has been held that it is a prima facie obvious by change of size in view of In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), see MPEP 2144.04.
It would have been obvious to one of ordinary skill in the art before the effective filing date, to modify OKAMOTO and LEE in light of Cho teaching to optimize the thickness of amorphous oxide layer. The optimization of the claimed thickness would have been obvious to one of ordinary skill in the art for further advantages such as to reduce the leakage current.
Regarding claim 17. OKAMOTO, LEE and Cho disclose the method according to claim 14, Cho disclose wherein a material of the multilayer oxide films comprise hafnium oxide (HfO), zirconium oxide (ZrO), hafnium zirconium oxide (HZO), or a combination thereof (Para [ 0097]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine OKAMOTO and LEE in light of Cho teaching “wherein a material of the multilayer oxide films comprise hafnium oxide (HfO), zirconium oxide (ZrO), hafnium zirconium oxide (HZO), or a combination thereof (Para [ 0097])” for further advantage such as to improve device performance by using well-known materials.
Regarding claim 19. OKAMOTO, LEE and Cho disclose the method according to claim 14, OKAMOTO further discloses wherein a number of layers of the oxide films is less than or equal to 10 (Fig 1, GIa/GIc made with Al.sub.2O.sub.3 films, Para [ 0088-0090]).
Regarding claim 20. OKAMOTO, LEE and Cho disclose the method according to claim 14, OKAMOTO further discloses wherein the multilayer oxide films have a total height of 30 to 200 angstroms (Para [ 0108] discloses “aluminum oxide film (a-Al.sub.2O.sub.3, c-Al.sub.2O.sub.3 is about 5 nm in this case, the thickness can be adjusted within a range from 2 to 20 nm”, GIb/Gid layers). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). "[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). >See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Claims 21-22 and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Imai (US 2009/0127551 A1; hereafter Imai) in view of OKAMOTO et al (US 2019/0074174 A1; hereafter OKAMOTO) and LEE et al (US 2021/0405498 A1; hereafter LEE) and further in view of Cho et al (US 2015/0357399 A1; hereafter Cho).
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Regarding claim 21. Imai discloses a method of manufacturing a semiconductor device, comprising:
forming a gate insulating layer (Fig. [4], gate insulating layer 3, Para [ 0092-0093]) on a gate electrode (gate electrode 2, Para [ 0092]);
forming a source electrode (source electrode 5-1, Para [ 0093]) and a drain electrode (drain electrode 5-2, Para [ 0093]) on the gate insulating layer (Fig. [4], gate insulating layer 3, Para [ 0092-0093]); and
forming an active layer ( active layer 44, Para [ 0096]) on the gate insulating layer (Fig. [4], gate insulating layer 3, Para [ 0092-0093]), wherein the active layer ( active layer 44, Para [ 0096]) covers a top portion of the source electrode (source electrode 5-1, Para [ 0093]) and a top portion of the drain electrode (drain electrode 5-2, Para [ 0093]) and a channel region (Para [ 0079]) is formed between the source electrode (source electrode 5-1, Para [ 0093]) and the drain electrode (drain electrode 5-2, Para [ 0093]).
But Imai does not disclose explicitly wherein forming the gate insulating layer comprises forming a stack of a plurality of oxide films and at least one interface layer, and the interface layer is disposed between two adjacent layers of the oxide films, wherein a thickness of each layer of the oxide films is less than 30 angstroms, a number of layers of the oxide films is greater than or equal to 3, and a number of layers of the interface layer is greater than 2 or equal to 2, and a dielectric constant of the interface layer is lower than a dielectric constant of the oxide films.
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In a similar field of endeavor, OKAMOTO discloses wherein forming the gate insulating layer comprises forming a stack of a plurality of oxide films (Fig 1, gate insulating film GI includes GIb/GId, Para [ 0088-0090]) and at least one interface layer (Fig 1, gate insulating film GI includes GIC, Para [ 0088-0090]), and the interface layer (Fig 1, gate insulating film GI includes GIC, Para [ 0088-0090]) is disposed between two adjacent layers of the oxide films (Fig 1, gate insulating film GI includes GIb/GId, Para [ 0088-0090]), wherein a thickness of each layer of the oxide films is less than 30 angstroms ( Para [ 0108] discloses “ aluminum oxide film (a-Al.sub.2O.sub.3, c-Al.sub.2O.sub.3 is about 5 nm in this case, the thickness can be adjusted within a range from 2 to 20 nm”, GIb/Gid layers). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). "[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). >See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005)
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Imai in light of OKAMOTO teaching “wherein forming the gate insulating layer comprises forming a stack of a plurality of oxide films (Fig 1, gate insulating film GI includes GIb/GId, Para [ 0088-0090]) and at least one interface layer (Fig 1, gate insulating film GI includes GIC, Para [ 0088-0090]), and the interface layer (Fig 1, gate insulating film GI includes GIC, Para [ 0088-0090]) is disposed between two adjacent layers of the oxide films (Fig 1, gate insulating film GI includes GIb/GId, Para [ 0088-0090]), wherein a thickness of each layer of the oxide films is less than 30 angstroms ( Para [ 0108] discloses “ aluminum oxide film (a-Al.sub.2O.sub.3, c-Al.sub.2O.sub.3 is about 5 nm in this case, the thickness can be adjusted within a range from 2 to 20 nm”, GIb/Gid layers)” for further advantage such as suppressing the reduction in threshold voltage.
But Imai and OKAMOTO do not disclose explicitly a number of layers of the oxide films is greater than or equal to 3, a number of layers of the amorphous oxide interface layer is greater than 2 or equal to 2 and a dielectric constant of the amorphous oxide interface layer is lower than a dielectric constant of the oxide films.
In a similar field of endeavor, LEE discloses a number of layers of the oxide films is greater than or equal to 3 (Fig 1, dielectric layers 12, Para [ 0078-0079]), a number of layers of the amorphous oxide interface layer is greater than 2 or equal to 2 (Fig 1, crystallization preventing layer 13 include amorphous silicon oxide, Para [ 0078-0079]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Imai and OKAMOTO in light of LEE teaching “amorphous oxide interface layer (Fig 1, crystallization preventing layer 13 include amorphous silicon oxide, Para [ 0078-0079]), and a number of layers of the oxide films is greater than or equal to 3 (Fig 1, dielectric layers 12, Para [ 0078-0079]), a number of layers of the amorphous oxide interface layer is greater than 2 or equal to 2 (Fig 1, crystallization preventing layer 13 include amorphous silicon oxide, Para [ 0078-0079])” for further advantage such as simplify manufacturing process by using well know deposition methods.
But Imai and OKAMOTO in light of LEE do not disclose explicitly wherein a dielectric constant of the interface layer is lower than a dielectric constant of the oxide films.
In a similar field of endeavor, Cho discloses wherein a dielectric constant of the interface layer is lower than a dielectric constant of the oxide films (Para [ 0004, 0097]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Imai, OKAMOTO, LEE in light of Cho teaching “wherein a dielectric constant of the interface layer is lower than a dielectric constant of the oxide films (Para [ 0004, 0097])” for further advantage such as to reduce the leakage current.
Regarding claim 22. Imai, OKAMOTO, LEE in light of Cho discloses the the method according to claim 21, Cho discloses wherein a material of the oxide films comprises hafnium oxide (HfO), zirconium oxide (ZrO), hafnium zirconium oxide (HZO) or a combination thereof (Para [ 0097]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Imai, OKAMOTO and LEE in light of Cho teaching “wherein a material of the multilayer oxide films comprise hafnium oxide (HfO), zirconium oxide (ZrO), hafnium zirconium oxide (HZO), or a combination thereof (Para [ 0097])” for further advantage such as to improve device performance by using well-known materials.
Regarding claim 24. Imai, OKAMOTO, LEE in light of Cho discloses the method according to claim 21, OKAMOTO further discloses wherein a material of the interface layer comprises silicon oxide (SiOx), aluminum oxide (AlOx), titanium oxide (TiOx), Tantalum oxide (TaOx) or metal-oxides with Gibbs free energy (GFE) higher than the oxide film (Fig 1, gate insulating film GI includes GIC, Para [ 0088-0090]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Imai, LEE and Cho in light of OKAMOTO teaching “wherein a material of the interface layer comprises silicon oxide (SiOx), aluminum oxide (AlOx), titanium oxide (TiOx), Tantalum oxide (TaOx) or metal-oxides with Gibbs free energy (GFE) higher than the oxide film (Fig 1, gate insulating film GI includes GIC, Para [ 0088-0090])” for further advantage such as suppressing the reduction in threshold voltage.
Regarding claim 25. Imai, OKAMOTO, LEE in light of Cho discloses the method according to claim 21, LEE discloses wherein the interface layer is an amorphous oxide (Fig 1, crystallization preventing layer 13 include amorphous silicon oxide, Para [ 0078-0079]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Imai, OKAMOTO and Cho in light of LEE teaching “wherein the interface layer is an amorphous oxide (Fig 1, crystallization preventing layer 13 include amorphous silicon oxide, Para [ 0078-0079])” for further advantage such as an excellent leakage characteristic can be easily formed using an insulating film.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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