DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 06/12/2026. Claims 14-17, 19-22 and 24-35 are pending for this examination.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/12/2026 has been entered. An action on the RCE follows.
Response to Arguments
Applicant’s reply filed on 06/12/2026 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al (US 2010/0029054 A1; hereafter Ahn) in view of Yuan et al (US 2022/0293720 A1; hereafter Yuan) and PENG et al (US 2019/0164972 A1; hereafter PENG).
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Regarding claim 14. Ahn discloses a method for suppressing a generation of leakage current for a gate insulating layer, the gate insulating layer comprising multilayer oxide films stacked on each other ( Fig 7, plurality of layers 705-1, 705-2 to 705-N, Para [ 0022-0024, 0082-0083]) , the method for suppressing the generation of leakage current comprising forming at least one amorphous oxide interface layer between two adjacent layers of the multilayer oxide films ( stacked layers [705-1, 705-2 to 705-N] made with “HfO.sub.x/Hf.sub.xTa.sub.yO.sub.z”, Fig 7, Para [0082-0083], claim 3), a number of layers of the oxide films is greater than or equal to 3, a number of layers of the amorphous oxide interface layer is greater than 2 or equal to 2 (Fig 7, Para [0082-0083]), wherein a material of the interface layer comprises titanium oxide (TiOx), Tantalum oxide (TaOx) or a combination thereof, and a material of the multilayer oxide films comprises hafnium oxide (HfO), zirconium oxide (ZrO) or a combination thereof ( Fig 7, stacked layers “stacked layers [705-1, 705-2 to 705-N] made with “HfO.sub.x/Hf.sub.xTa.sub.yO.sub.z”, Fig 7, Para [0082-0083], claim 3).
But Ahn do not disclose explicitly a dielectric constant of the amorphous oxide interface layer is lower than a dielectric constant of the oxide films and wherein a thickness of each layer of the oxide films is less than 30 angstroms.
In a similar field of endeavor, Yuan discloses a dielectric constant of the amorphous oxide interface layer is lower than a dielectric constant of the oxide films (Para [0035, 0066 discloses different dielectric constant of metal oxide with variation of temperature and process. Therefore, dielectric constant of the amorphous oxide interface layer can lower than a dielectric constant of the oxide films).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ahn in light of Yuan teaching “a dielectric constant of the amorphous oxide interface layer is lower than a dielectric constant of the oxide films (Para [0035, 0066 discloses different dielectric constant of metal oxide with variation of temperature and process. Therefore, dielectric constant of the amorphous oxide interface layer can lower than a dielectric constant of the oxide films) for further advantage such as to reduce the leakage current.
But Ahn and Yuan do not disclose explicitly wherein a thickness of each layer of the oxide films is less than 30 angstroms.
In a similar field of endeavor, PENG discloses wherein a thickness of each layer of the oxide films is less than 30 angstroms (Para [ 0033]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ahn and Yuan in light of PENG teaching “wherein a thickness of each layer of the oxide films is less than 30 angstroms (Para [ 0033])” for further advantage such as to provide high gate control capability, and high stability with desire thickness.
Regarding claim 15. Ahn and Yuan in light of PENG disclose the method according to claim 14, Ahn further disclose wherein the interface layer has Gibbs free energy (GFE) higher than the oxide film (Fig 7, stacked layers “stacked layers [705-1, 705-2 to 705-N], based on the same material characteristic).
Regarding claim 16. Ahn and Yuan in light of PENG disclose the method according to claim 14, PENG further disclose wherein a thickness of the interface layer is less than or equal to 2 angstroms (Para [ 0033]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ahn and Yuan in light of PENG teaching “wherein a thickness of the interface layer is less than or equal to 2 angstroms (Para [ 0033])” for further advantage such as to provide high gate control capability, and high stability with desire thickness.
Regarding claim 17. Ahn and Yuan in light of PENG disclose the method according to claim 14, Ahn further disclose wherein the material of the multilayer oxide films further comprises comprise hafnium oxide (HfO), zirconium oxide (ZrO), hafnium zirconium oxide (HZO), or a combination thereof (Para [ 0082-0083]).
Regarding claim 19. Ahn and Yuan in light of PENG disclose the method according to claim 14, Ahn further disclose wherein a number of layers of the oxide films is less than or equal to 10 (Fig 7, stacked layers “stacked layers [705-1, 705-2 to 705-N], Para [ 0082-0083]).
Regarding claim 20. Ahn and Yuan in light of PENG disclose the method according to claim 14, Ahn further disclose wherein the multilayer oxide films.
But Ahn and Cho do not disclose explicitly have a total height of 30 to 200 angstroms.
In a similar field of endeavor, PENG discloses have a total height of 30 to 200 angstroms (The gate dielectric layer 212 is formed from a dielectric material such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, tantalum oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium silicate, zirconium aluminate, tin oxide, zirconium oxide, titanium oxide, aluminum oxide, high-k dielectric, combinations thereof, and/or another suitable material, and may have a thickness ranging from about 1 nm to about 5 nm (Para [ 0033]). Based on the thickness, as discloses by the PENG, height of the Ahn stacked multi-layer oxide film can have a total height of 30 to 200 angstroms.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ahn and Yuan in light of PENG teaching “have a total height of 30 to 200 angstroms (The gate dielectric layer 212 is formed from a dielectric material such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, tantalum oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium silicate, zirconium aluminate, tin oxide, zirconium oxide, titanium oxide, aluminum oxide, high-k dielectric, combinations thereof, and/or another suitable material, and may have a thickness ranging from about 1 nm to about 5 nm (Para [ 0033]). Based on the thickness, as discloses by the PENG, height of the Ahn stacked multi-layer oxide film can have a total height of 30 to 200 angstroms” for further advantage such as to provide high gate control capability with a desire thickness.
Claims 14-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al (US 2010/0029054 A1; hereafter Ahn) in view of Yuan et al (US 2022/0293720 A1; hereafter Yuan) and PENG et al (US 2019/0164972 A1; hereafter PENG) as applied claims above and further in view of CHENG et al (US 2020/0373206 A1; hereafter CHENG).
Regarding claim 34. Ahn and Yuan in light of PENG disclose the method according to claim 14, But Ahn and Yuan in light of PENG does not disclose wherein a thickness of the amorphous oxide interface layer is less than a thickness of each layer of the oxide films.
In a similar field of endeavor, PENG discloses wherein a thickness of the amorphous oxide interface layer is less than a thickness of each layer of the oxide films (Para [ 0043] discloses “Each of interfacial oxide layers 127A-127B can be disposed on respective nanostructured channel regions 120B and 122B and can include silicon oxide and a thickness ranging from about 0.5 nm to about 1.5 nm. Each of gate dielectric layers 128A-128B can have a thickness (e.g., about 1 nm to about 3 nm) that is about 2 to 3 times the thickness of interfacial oxide layers 127A-127B and can include (i) a layer of silicon oxide, silicon nitride, and/or silicon oxynitride, (ii) a high-k dielectric material, such as hafnium oxide (Hf.sub.2), titanium oxide (TiO.sub.2), hafnium zirconium oxide (HfZrO)”). Based on the thickness, as discloses by the CHENG, a thickness of the amorphous oxide interface layer can less than a thickness of each layer of the oxide films.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ahn and Yuan in light of PENG in light of CHENG teaching “wherein a thickness of the amorphous oxide interface layer is less than a thickness of each layer of the oxide films (Para [ 0043] discloses “Each of interfacial oxide layers 127A-127B can be disposed on respective nanostructured channel regions 120B and 122B and can include silicon oxide and a thickness ranging from about 0.5 nm to about 1.5 nm. Each of gate dielectric layers 128A-128B can have a thickness (e.g., about 1 nm to about 3 nm) that is about 2 to 3 times the thickness of interfacial oxide layers 127A-127B and can include (i) a layer of silicon oxide, silicon nitride, and/or silicon oxynitride, (ii) a high-k dielectric material, such as hafnium oxide (Hf.sub.2), titanium oxide (TiO.sub.2), hafnium zirconium oxide (HfZrO)”). Based on the thickness, as discloses by the CHENG, a thickness of the amorphous oxide interface layer can less than a thickness of each layer of the oxide films” for further advantage such as to provide high gate control capability with a desire thickness.
Claims 28-31 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al (US 2010/0029054 A1; hereafter Ahn) in view of PENG et al (US 2019/0164972 A1; hereafter PENG).
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Regarding claim 28. Ahn discloses a method of manufacturing an oxide film, comprising:
forming a first oxide film with high dielectric constant on a substrate (Fig 7, layer 705-1, Para [ 0022-0024, 0082-0083]);
forming an interface layer on the first oxide film (Fig 7, layer 705-2, Para [ 0022-0024, 0082-0083]); and
forming a second oxide film (Fig 7, another layer 705-1, Para [ 0022-0024, 0082-0083]) with high dielectric constant on the interface layer (Fig 7, layer 705-2, Para [ 0022-0024, 0082-0083]);
wherein the first and second oxide films are stacked on each other ( Fig 7, plurality of layers 705-1, 705-2 to 705-N, Para [ 0022-0024, 0082-0083]), and the interface layer is disposed between the first and second oxide films ( Fig 7, plurality of layers 705-1, 705-2 to 705-N, Para [ 0022-0024, 0082-0083]), a number of layers of the first and second oxide films is greater than or equal to 3, a number of layers of the interface layer is greater than 2 or equal to 2 ( Fig 7, plurality of layers 705-1, 705-2 to 705-N, Para [ 0022-0024, 0082-0083]), and wherein a material of the interface layer comprises Tantalum oxide (TaOx), and a material of the first and second oxide films comprises hafnium oxide (HfO) (Fig 7, Para [0082-0083]).
But Ahn do not disclose explicitly wherein a thickness of each layer of the oxide films is less than 30 angstroms.
In a similar field of endeavor, PENG discloses wherein a thickness of each layer of the oxide films is less than 30 angstroms (Para [ 0033]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ahn in light of PENG teaching “wherein a thickness of each layer of the oxide films is less than 30 angstroms (Para [ 0033])” for further advantage such as to provide high gate control capability, and high stability with desire thickness.
Regarding claim 29. Ahn in light of PENG disclose the method according to claim 28, Ahn further discloses wherein the interface layer is an amorphous oxide (Para [0082-0083], and claim 3).
Regarding claim 30. Ahn in light of PENG disclose the method according to claim 28, PENG further disclose wherein a thickness of the interface layer is less than or equal to 2 angstroms (Para [ 0033]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ahn in light of PENG teaching “wherein a thickness of the interface layer is less than or equal to 2 angstroms (Para [ 0033])” for further advantage such as to provide high gate control capability, and high stability.
Regarding claim 31. Ahn in light of PENG disclose the method according to claim 28, Ahn further discloses wherein the material of the first and second oxide films comprises hafnium oxide (HfO), zirconium oxide (ZrO), hafnium zirconium oxide (HZO) or a combination thereof (Para [0082-0083]).
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al (US 2010/0029054 A1; hereafter Ahn) in view of PENG et al (US 2019/0164972 A1; hereafter PENG) as applied claims above and further in view of Yuan et al (US 2022/0293720 A1; hereafter Yuan).
Regarding claim 32. Ahn in light of PENG disclose the method according to claim 28, But Ahn in light of PENG does not disclose wherein a dielectric constant of the interface layer is lower than a dielectric constant of the first and second oxide films.
In a similar field of endeavor, Yuan discloses wherein a dielectric constant of the interface layer is lower than a dielectric constant of the first and second oxide films (Para [0035, 0066 discloses different dielectric constant of metal oxide with variation of temperature and process. Therefore, dielectric constant of the amorphous oxide interface layer can lower than a dielectric constant of the oxide films).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ahn and PENG in light of Yuan teaching “wherein a dielectric constant of the interface layer is lower than a dielectric constant of the first and second oxide films (Para [0035, 0066 discloses different dielectric constant of metal oxide with variation of temperature and process. Therefore, dielectric constant of the amorphous oxide interface layer can lower than a dielectric constant of the oxide films)” for further advantage such as to reduce the leakage current.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al (US 2010/0029054 A1; hereafter Ahn) in view of PENG et al (US 2019/0164972 A1; hereafter PENG) as applied claims above and further in view of CHENG et al (US 2020/0373206 A1; hereafter CHENG).
Regarding claim 33. Ahn in light of PENG disclose the method according to claim 28, But Ahn in light of PENG does not disclose wherein a thickness of the interface layer is less than a thickness of the first oxide film or the second oxide film.
In a similar field of endeavor, CHENG discloses wherein a thickness of the interface layer is less than a thickness of the first oxide film or the second oxide film (Para [ 0043] discloses “Each of interfacial oxide layers 127A-127B can be disposed on respective nanostructured channel regions 120B and 122B and can include silicon oxide and a thickness ranging from about 0.5 nm to about 1.5 nm. Each of gate dielectric layers 128A-128B can have a thickness (e.g., about 1 nm to about 3 nm) that is about 2 to 3 times the thickness of interfacial oxide layers 127A-127B and can include (i) a layer of silicon oxide, silicon nitride, and/or silicon oxynitride, (ii) a high-k dielectric material, such as hafnium oxide (Hf.sub.2), titanium oxide (TiO.sub.2), hafnium zirconium oxide (HfZrO)”). Based on the thickness, as discloses by the CHENG, a thickness of the amorphous oxide interface layer can less than a thickness of each layer of the oxide films.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ahn and PENG in light of CHENG teaching “wherein a thickness of the interface layer is less than a thickness of the first oxide film or the second oxide film (Para [ 0043] discloses “Each of interfacial oxide layers 127A-127B can be disposed on respective nanostructured channel regions 120B and 122B and can include silicon oxide and a thickness ranging from about 0.5 nm to about 1.5 nm. Each of gate dielectric layers 128A-128B can have a thickness (e.g., about 1 nm to about 3 nm) that is about 2 to 3 times the thickness of interfacial oxide layers 127A-127B and can include (i) a layer of silicon oxide, silicon nitride, and/or silicon oxynitride, (ii) a high-k dielectric material, such as hafnium oxide (Hf.sub.2), titanium oxide (TiO.sub.2), hafnium zirconium oxide (HfZrO)”). Based on the thickness, as discloses by the CHENG, a thickness of the amorphous oxide interface layer can less than a thickness of each layer of the oxide films” for further advantage such as to provide high gate control capability with a desire thickness.
Allowable Subject Matter
Claims 21-22, 24-25 and 35 are allowed.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
wherein forming the gate insulating layer comprises forming a stack of a plurality of oxide films and at least one interface layer, and the interface layer is disposed between two adjacent layers of the oxide films, wherein a thickness of each layer of the oxide films is less than 30 angstroms, a number of layers of the oxide films is greater than or equal to 3, and a number of layers of the interface layer is greater than 2 or equal to 2, and a dielectric constant of the interface layer is lower than a dielectric constant of the oxide films, wherein a material of the interface layer comprises titanium oxide (TiOx), and a material of the oxide films comprises hafnium zirconium oxide (HZO). as recited in claim 21.
Claims 22, 24-25 and 35 are allowed based on the dependency of claim 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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