DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed 12/23/2025 have been entered and considered. The amendments to claims 16, 17, 20, 25, 26, 29, 33 and 35 are acknowledged.
Specification
The disclosure is objected to because of the following informalities: paragraphs 0041, 0062, and 0094 indicate that the outer acute angle A2 may be greater than 85°. However, subsequent sentences indicate that the outer acute angle A2 may range from 55° to 85°.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim recites “there is an outer acute angle included between the inner lateral sidewall and the substrate, and the outer acute angle is greater than 85°”. The specification teaches contradictory passages regarding this structural feature. In para. 0041 and 0062 indicate that the outer acute angle A2 is greater than 85°. On the contrary, the following sentence in each paragraph suggests the outer acute angle A2 may range from 55° to 85°. It is not clear how the outer acute angle can be greater than 85° when the example values are given as less than 85°.
Claim 1 is further rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claim recites “there is an outer acute angle included between the inner lateral sidewall and the substrate, and the outer acute angle is greater than 85°”. Angles greater than 90° are also greater than 85° but are not acute, which is contradictory to the claimed angle being acute. Furthermore, the specification gives support for outer acute angles being from 55° to 85° and not for values greater than 85°. The meets and bounds of the limitation are not clearly established.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 16, 21, 24, 30, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. US 20070023483 A1 (hereinafter referred to as Yoneyama), in view of Gatterbauer et al. US 9502248 B1 (hereinafter referred to as Gatterbauer), in view of Wang et al. US 20240006361 A1 (hereinafter referred to as Wang).
Regarding claim 16, Yoneyama teaches
A manufacturing method of a semiconductor device (“a packaging method for producing the packaging structure indicated in FIG. 1” para. 0032), comprising:
forming each of a first semiconductor die (“substrate 10” para. 0032 FIG. 1-2) and a second semiconductor die (“semiconductor device 20” para. 0032), comprising:
forming a conductive bump on a substrate (“pads 13” on “substrate 10”, para. 0027, and pads upon which “bumps 32” are disposed, FIG. 1);
forming a conductive contact (“bumps 31” para. 0027) on the conductive bump, wherein the conductive contact has an outer lateral sidewall (“bumps 31” have a sloped outer sidewall), there is an inner acute angle included between the outer lateral sidewall and the substrate (since the sidewalls of “primary bumps 31” are tapered, there is an inner acute angle between sidewalls of “primary bumps 31” and “substrate 10”),
connecting a conductive contact of the first semiconductor die opposite to the conductive contact of the second semiconductor die (“bumps 32” para. 0027, connected to “bumps 31” as seen in FIG. 1),
However, Yoneyama fails to expressly teach the inner acute angle is smaller than 85°, forming a photoresist on the substrate, wherein the photoresist has an opening having an inner lateral sidewall, there is an outer acute angle included between the inner lateral sidewall and the substrate, and the outer acute angle is greater than 85°, and forming the conductive contact through the opening of the photoresist, wherein forming each of the first semiconductor die and the second semiconductor die comprises: before forming the photoresist on the substrate, forming the base layer material on the substrate: and after forming the photoresist on the substrate, forming a protrusion on a portion of an upper surface of the base layer material through the opening of the photoresist.
Nevertheless, FIG. 2 appears to suggest “secondary bumps 32” having a slightly smaller inner acute angle than “primary bumps 31”. The “diameter d1” of the top surface of “primary bump 31” is larger than the “diameter d2” of the bottom surface of “secondary bumps 32” before bonding takes place (para. 0042). The examiner understands that for a fixed bump height and fixed greatest width, the slope of the sidewall of the bump will depend on the desired smallest width. For smaller values of “diameters d1 and d2” while having a same greatest width and height, smaller inner acute angles will be required for the bumps. In other words, the inner acute angle of the sidewall is smaller for bumps having larger differences between the widths at opposite ends of the bump. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the taper angle of the “primary bumps 31” depends on the desired “diameter d1” for a given height and a width in contact with “pad 13”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the angle of the inner acute angle is a result effective variable dependent on the difference between the width of the conductive contact at the conductive bump side and the width of the conductive contact at the bonding side. The greater the difference between opposite ends of the conductive contact, the smaller the inner acute angle.
However, Yoneyama fails to teach forming a photoresist on the substrate, wherein the photoresist has an opening having an inner lateral sidewall, there is an outer acute angle included between the inner lateral sidewall and the substrate, and the outer acute angle is greater than 85°, and forming the conductive contact through the opening of the photoresist, wherein forming each of the first semiconductor die and the second semiconductor die comprises: before forming the photoresist on the substrate, forming a base layer material on the substrate: and after forming the photoresist on the substrate, forming a protrusion on a portion of an upper surface of the base layer material through the opening of the photoresist.
Nevertheless, Gatterbauer teaches
forming a photoresist (“second mask structure 204” para. 0087, showing as element 202 in FIG. 6A-6C) on the substrate (“surface 111” para. 0085), wherein the photoresist has an opening (“second opening 204o” para. 0049, not seen in FIG. 6A-6B but analogous to that in FIG. 3C and having a common “second extension 204d”) having an inner lateral sidewall (not shown in FIG. 6A-6C but the examiner understands “sidewall 204s” in FIG. 5B is the same as the sidewall of “second mask structure 204” in FIG. 6A-6C), there is an outer acute angle included between the inner lateral sidewall and the substrate (there is an angle between “204s” and “surface 111” in “opening 204o”), and the outer acute angle is greater than 85° (as is analogous in FIG. 3C, “second angle 204w in the range from about 70° to about 85°” para. 0045. The examiner understands that being about 85° means that the angle is 85° plus or minus a small amount.), and
forming a conductive contact (“second layer 104” and “third layer 112” on “first layer 102”, para. 0085-0086) through the opening of the photoresist,
forming a base layer material (“first layer 102”, para. 0085) on the substrate,
after forming the photoresist on the substrate, forming a protrusion (“second layer 104” and “third layer 112”) on a portion of an upper surface of the base layer material through the opening of the photoresist (“second layer 104” and “third layer 112” are formed over “first layer 102”).
Yoneyama and Gatterbauer teach contacts having sloped sidewalls. “Bumps 31, 32” in Yoneyama are made by a wirebonding method (para. 0027, 0030). The conductive contact comprising “first layer 102”, “second layer 104” and “third layer 112” in Gatterbauer are formed by physical vapor deposition such as sputtering in the openings of different masks (para. 0027, 0030, 0056). Because multiple openings can be made in the masks, a plurality of “second layer stacks 514” can be made simultaneously instead of by wirebonding. Furthermore, the outer acute angle of the “second mask pattern 204” and the inner acute angle of the conductive pattern do not need to be the same; either can be between about 70° to about 85°. Because the conductive pattern is formed by sputtering, the examiner understands the inner acute angle is subject to the deposition angle which can depend on the position of the sputtering target. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the deposition and mask lift-off method of forming conductive contacts in Gatterbauer is a suitable way to form multiple contacts simultaneously. The conductive pattern can be formed in a photomask that has a range of appropriate outer acute angles.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Yoneyama with the contact formation method taught in Gatterbauer. The plurality of contacts in Gatterbauer can be made at the same time using photoresists with varying outer acute angles.
However, Yoneyama, modified by Gatterbauer, fails to teach, before forming the photoresist on the substrate, forming the base layer material on the substrate.
Nevertheless, Wang teaches
before forming the photoresist (“first photo resist layer 1000” para. 0057 FIG. 10A) on the substrate (“interconnect portion 122” over “die substrate 120”, para. 0027), forming the base layer (“under bump metallization interconnects 109” is formed before “first photo resist layer 1000”, para. 0065 FIG. 10A) material on the substrate.
Yoneyama, modified by Gatterbauer, and Wang teach bumps with slanted sidewalls. The “under bump metallization interconnects 109” are formed before “first photo resist layer 1000”, leading to “pillar interconnects 104” being formed over the entire top surfaces of individual “under bump metallization interconnects 109”. Since “first layer 102 may be a barrier layer” (Gatterbauer para. 0062), it is understood that “first layer 102” protects against any diffusion of material from the bump structure to the “surface 111” and the formation of undesired inter-metallic alloys. Unlike in Wang, the “first layer 102” does not span the whole width of the conductive bump, leaving portions of “third layer 112” to contact “first surface 111”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having the “first layer 102” in Gatterbauer having a same width as the bottom surface of “third layer 112” and “second layer 104” may better prevent “third layer 112” from diffusing into “surface 111”. This is achieved by forming “first layer 102” before forming ““first mask structure 202”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yoneyama and Gatterbauer with the steps taught in Wang. Forming the base layer before the photoresist enables the base layer to completely underlap the protrusion.
Regarding claim 17, Yoneyama, modified by Gatterbauer and Wang, teaches the manufacturing method as claimed in claim 16 wherein forming each of the first semiconductor die and the second semiconductor die comprises:
removing the photoresist from the substrate (“first photo resist layer 1000 is removed from the die portion 102”, Wang para. 0059 FIG. 10B); and
removing a portion of the base layer material (“Portions of the under bump metallization interconnects 109 may also be removed” Wang para. 0062 FIG. 10C), wherein a remaining portion of the base layer material forms the base layer (remaining “under bump metallization interconnects 109” are analogous to the “first and second under bump metallization interconnects 109a and 109b” in FIG. 1), and the base layer and the protrusion form the conductive contact (“first under bump metallization interconnect 109a” and “first pillar interconnect 104a” are a conductive contact over the bump “first pad 107a”, para. 0031).
Regarding claim 18, Yoneyama, modified by Gatterbauer and Wang, teaches the manufacturing method as claimed in claim 17, wherein the base layer has a lateral surface (“first layer 102” in FIG. Gatterbauer FIG. 6C, as well as “first under bump metallization interconnect 109a” in FIG. 1 and FIG. 10C in Wang, are suggested to have a lateral surface), the protrusion has the outer lateral sidewall (“primary bump 31” in Yoneyama has outer lateral sidewall, as well as “second layer 104” and “third layer112” in Gatterbauer and “first pillar interconnect 104” in Wang), there is an outer obtuse angle included between the lateral surface of the base layer and the outer lateral sidewall (by depositing “primary bump 31” with the sloped side over “first layer 012”, now extending to the lower edge of “third layer 112” as modified by Wang, with the vertical lateral side, there is an obtuse outer angle between the lateral sides), and the outer obtuse angle is greater than 180° (since the lateral sidewall of “primary bump 31” tapers inward, the outer angle between the vertical lateral sidewall of “first layer 102” and the sidewall of “primary bump 31” is greater than 180°).
Regarding claim 19, Yoneyama, modified by Gatterbauer and Wang, teaches the manufacturing method as claimed in claim 17, wherein the protrusion has a protrusion thickness (“second layer 104” and “third layer 112” in Gatterbauer each have a thickness between 10nm to 5µm, para. 0087), the base layer has a base thickness (“first layer 102” has a thickness between 10nm to 5µm, para. 0084), and the protrusion thickness is 3 times to 10 times of the base thickness (In example cases taking “first layer 102” with a thickness of 5nm or 100nm and a combined thickness of “third layer 112” with “second layer 104” of 15nm or 300, the thickness of “third layer 112” with “second layer 104” is 3 to 7 times thicker than “first layer 102”).
Regarding claim 21, Yoneyama, modified by Gatterbauer na Wang, teaches the manufacturing method as claimed in claim 16, in one of the first semiconductor die and the second semiconductor die, the inner acute angle ranges between 55° and 85° (As discussed in the rejection of claim 16, the inner acute angle is a result effective variable depending on the desired smallest width of “primary bump 31”. Furthermore, “sidewall 104s which is inclined with respect to the surface 111 by an angle 102w in the range from about 70° to about 85°” in para. 0075 of Gatterbauer).
Regarding claim 24, Yoneyama, modified by Gatterbauer and Wang, teaches manufacturing method as claimed in claim 16, wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact has a width gradually decreasing in a direction away from the substrate (“primary and secondary bumps 31 and 32” have tapered sides, para. 0039 FIG. 1).
Regarding claim 30, Yoneyama, modified by Gatterbauer and Wang, teaches the manufacturing method as claimed in claim 16, in one of the first semiconductor die and the second semiconductor die, the inner acute angle ranges between 55° and 85° (As discussed in the rejection of claim 16, the inner acute angle is a result effective variable depending on the desired smallest width of “primary bump 31”. Furthermore, “sidewall 104s which is inclined with respect to the surface 111 by an angle 102w in the range from about 70° to about 85°” para. 0075 of Gatterbauer).
Regarding claim 32, Yoneyama, modified by Gatterbauer and Wang, teaches the manufacturing method as claimed in claim 16, wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact has a width gradually decreasing in a direction away from the substrate (“primary and secondary bumps 31 and 32” have tapered sides, para. 0039 FIG. 1).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama, modified by Gatterbauer and Wang as applied to claim 16 above, in view of Lin et al. US 20130069225 A1 (hereinafter referred to as Lin).
Yoneyama, modified by Gatterbauer and Wang, teaches the manufacturing method as claimed in claim 16, wherein forming each of the first semiconductor die and the second semiconductor die comprises:
forming the protrusion on the base layer material through the opening of the photoresist (“pillar interconnect 104” is formed over “under bump metallization interconnects 109” within “opening 1001” as taught in Wang);
removing the photoresist from the substrate (“first photo resist layer 1000 is removed from the die portion 102”, Wang para. 0059 FIG. 10B); and
removing a portion of the base layer material and wherein a remaining portion of the base layer material forms the base layer (remaining “under bump metallization interconnects 109” are analogous to the “first and second under bump metallization interconnects 109a and 109b” in FIG. 1), the base layer has a second lateral surface (“first under bump metallization interconnect 109a” in FIG. 1 and FIG. 10C in Wang is suggested to have a lateral surface).
However, Yoneyama, modified by Gatterbauer and Wang, fails to teach forming a seed layer material on the substrate; forming the base layer material on the seed layer material; removing a portion of the seed layer material, a remaining portion of the seed layer material forms the seed layer, the seed layer has a first lateral surface, the first lateral surface and the second lateral surface are flush with each other.
Nevertheless, Lin teaches
forming a seed layer material (“blanket conductive layer 148 acts as a seed layer” para. 0042 FIG. 3d) on the substrate (“semiconductor wafer 120” para. 0041);
forming the base layer material (“conductive layer 152” para. 0044) on the seed layer material;
removing a portion of the seed layer material, a remaining portion of the seed layer material forms the seed layer (portion of “seed layer 148” under “photoresist layer 140” is removed by etching, para. 0047 FIG. 3g), the seed layer has a first lateral surface (“seed layer 148” has a lateral surface as suggested in FIG. 3g), the first lateral surface and the second lateral surface are flush with each other (the lateral surfaces of “seed layer 148” and “conductive layer 152” are shown as flush)
Yoneyama, modified by Gatterbauer and Wang, and Lin teach methods of forming interconnect structures. The examiner understands seed layers are used to help deposit conductive structures more easily by acting as a growth site, as evidenced in para. 0025 of Wu et al. US 20200227368 A1. The “seed layer 148” is understood to act as a growth site for the deposited “conductive layer 152”, which is a barrier layer made of nickel, platinum, or palladium (para. 0044). The “first layer 102” in Gatterauer is a barrier layer made of platinum (Gatterbauer para. 0067). “Seed layer 148” and “conductive layer 152” constitute part of a “UBM layer 159” upon which “bumps 162” are formed, analogous to the “under bump metallization interconnects 109” with “pillar interconnects 104” in Wang. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the use of “seed layer 148” improves the ability to deposit the barrier layer “first layer 102”. By forming the “seed layer 148” under the “first layer 102” in Gatterbauer and patterning as taught in Wang, the lateral surfaces of “seed layer 148” and “first layer 102” will be flush.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yoneyama, Gatterbauer, and Wang with the seed layer taught in Lin. The seed enables easier formation of the base layer.
Claims 22-23 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama, Gatterbauer, and Wang as applied in claim 16, in view of Mirkarimi et al. WO 2022187402 A1 (hereinafter referred to as Mirkarimi).
Regarding claim 22, Yoneyama, modified by Gatterbauer and Wang, teaches the manufacturing method as claimed in claim 16 but fails to teach in one of the first semiconductor die and the second semiconductor die, the conductive contact comprises a plurality of grains, and each grain has a diameter ranging between 2 nm to 100 nm.
Nevertheless, Mirkarimi teaches
in one of the first semiconductor die (“first element 1” para. 0032 FIG. 2) and the second semiconductor die (“second element 3” para. 0032), the conductive contact comprises a plurality of grains (“conductive feature 28” is a fine gain metal, para. 0038), and each grain has a diameter ranging between 2 nm to 100 nm (“an average grain width less than 20nm, less than 50 nm, less than 100 nm, less than 300 nm, or less than 500 nm” para. 0038).
Yoneyama, modified by Gatterbauer and Wang, and Mirkarimi teach interconnect structures. Mirkarimi teaches that copper conductive structures with smaller grain sizes have a larger grain boundary surface area, have a greater creep rate which improves bonding between conductive patterns, and can be bonded at lower temperatures than conductive structures having larger grains (para. 0028). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that fine grain metal “conductive features 28” such as fine grain copper has properties than improve the bonding speed and quality of the interconnect structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yoneyama, Gatterbauer, and Wang with fine grain conductive contact taught in Mirkarimi. A conductive contact with small grain diameter has a larger grain surface area, increased creep rate, and can bond to another conductive contact at a lower temperature than a conductive contact with larger grain diameter, which lead to an improved bonded structure.
Regarding claim 23, Yoneyama, modified by Gatterbauer and Wang, teaches the manufacturing method as claimed in claim 16 but fails to teach wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact of the first semiconductor die and the conductive contact of the second semiconductor die are connected in a connection, and the connection has a width ranging between 0.6 µm to 2.5 µm.
Nevertheless, Mirkarimi teaches
Wherein in one of the first semiconductor die (“first element 1” para. 0032 FIG. 2) and the second semiconductor die (“second element 3” para. 0032), the conductive contact of the first semiconductor die (“conductive feature 28” para. 0038) and the conductive contact of the second semiconductor die (“conductive feature 48” para. 0045) are connected in a connection (“first element 1 can be bonded to the second element 3” by the conductive features, para. 0045 FIG. 2), and the connection has a width ranging between 0.6 µm to 2.5 µm (“a width of the conductive features 28 may range in a range of, for example, 0.3 µm to 60µm, 0.5 µm to 40 µm, or 0.5 m to 20 µm” and “conductive features 48” appear to have substantially similar width in FIG. 2).
Yoneyama, modified by Gatterbauer and Wang, and Mirkarimi teach interconnect structures. The conductive contacts taught between Yoneyama, Gatterbauer, and Wang are larger than 5µm (Gatterbauer para. 0040). The “conductive features” in Mirkarimi can be as small as 0.3µm such that the interconnected structure can have a total width between 0.3 µm and 60µm even including the barrier layers (para. 0035). As technology as progressed, semiconductor devices continue to require greater integration with other devices and signals paths. This leads to more interconnections between devices while also minimizing the sizes of the packages, such that interconnect densities must also increase. Interconnect density can be increased by forming contact structures with smaller diameters. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the interconnect sizes taught in Mirkarimi can be used for devices that require high density interconnects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yoneyama, Gatterbauer, and Wang with the conductive contact sizes taught in Mirkarimi. Smaller conductive contacts are suitable for devices that require a high density of interconnects.
Regarding claim 31, Yoneyama, modified by Gatterbauer and Wang, teaches the manufacturing method as claimed in claim 16 but fails to teach wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact of the first semiconductor die and the conductive contact of the second semiconductor die are connected in a connection, and the connection has a width ranging between 0.6 µm to 2.5 µm.
Nevertheless, Mirkarimi teaches
Wherein in one of the first semiconductor die (“first element 1” para. 0032 FIG. 2) and the second semiconductor die (“second element 3” para. 0032), the conductive contact of the first semiconductor die (“conductive feature 28” para. 0038) and the conductive contact of the second semiconductor die (“conductive feature 48” para. 0045) are connected in a connection (“first element 1 can be bonded to the second element 3” by the conductive features, para. 0045 FIG. 2), and the connection has a width ranging between 0.6 µm to 2.5 µm (“a width of the conductive features 28 may range in a range of, for example, 0.3 µm to 60µm, 0.5 µm to 40 µm, or 0.5 m to 20 µm” and “conductive features 48” appear to have substantially similar width in FIG. 2).
Yoneyama, modified by Gatterbauer and Wand, and Mirkarimi teach interconnect structures. The conductive contacts taught between Yoneyama, Gatterbauer, and Wang are larger than 5µm (Gatterbauer para. 0040). The “conductive features” in Mirkarimi can be as small as 0.3µm such that the interconnected structure can have a total width between 0.3 µm and 60µm even including the barrier layers (para. 0035). As technology as progressed, semiconductor devices continue to require greater integration with other devices and signals paths. This leads to more interconnections between devices while also minimizing the sizes of the packages, such that interconnect densities must also increase. Interconnect density can be increased by forming contact structures with smaller diameters. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the interconnect sizes taught in Mirkarimi can be used for devices that require high density interconnects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yoneyama, Gatterbauer, and Wang with the conductive contact sizes taught in Mirkarimi. Smaller conductive contacts are suitable for devices that require a high density of interconnects.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama, in view of Wang.
Yoneyama teaches
A manufacturing method of a semiconductor device (“a packaging method for producing the packaging structure indicated in FIG. 1” para. 0032), comprising:
forming each of a first semiconductor die (“substrate 10” para. 0032 FIG. 1-2) and a second semiconductor die (“semiconductor device 20” para. 0032), comprising:
forming a conductive bump (“pads 13” on “substrate 10”, para. 0027, and pads upon which “bumps 32” are disposed, FIG. 1) on a substrate (“substrate 10”); and
forming a conductive contact (“pads 13” on “substrate 10”, para. 0027, and pads upon which “bumps 32” are disposed, FIG. 1) the conductive bump;
connecting the conductive contact of the first semiconductor die opposite to the conductive contact of the second semiconductor die (“bumps 32” para. 0027, connected to “bumps 31” as seen in FIG. 1);
wherein the conductive contact has an outer lateral sidewall (“primary and secondary bumps 31 and 32” have sidewalls), there is an inner acute angle included between the outer lateral sidewall and the substrate (since the sidewalls of “primary bumps 31” are tapered, there is an inner acute angle between sidewalls of “primary bumps 31” and “substrate 10”), and the conductive contact of the first semiconductor die is connected opposite to the conductive contact of the second semiconductor die (“bumps 32” para. 0027, connected to “bumps 31” as seen in FIG. 1).
However, Yoneyama fails to expressly teach the inner acute angle is smaller than 85°, wherein forming each of the first semiconductor die and the second semiconductor die comprises: forming a base layer material on the substrate; and forming a protrusion on a portion of an upper surface of the base layer material.
Nevertheless, FIG. 2 appears to suggest “secondary bumps 32” having a slightly smaller inner acute angle than “primary bumps 31”. The “diameter d1” of the top surface of “primary bump 31” is larger than the “diameter d2” of the bottom surface of “secondary bumps 32” before bonding takes place (para. 0042). The examiner understands that for a fixed bump height and fixed greatest width, the slope of the sidewall of the bump will depend on the desired smallest width. For smaller values of “diameters d1 and d2” while having a same greatest width and height, smaller inner acute angles will be required for the bumps. In other words, the inner acute angle of the sidewall is smaller for bumps having larger differences between the widths at opposite ends of the bump. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the taper angle of the “primary bumps 31” depends on the desired “diameter d1” for a given height and a width in contact with “pad 13”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the angle of the inner acute angle is a result effective variable dependent on the difference between the width of the conductive contact at the conductive bump side and the width of the conductive contact at the bonding side. The greater the difference between opposite ends of the conductive contact, the smaller the inner acute angle.
However, Yoneyama fails to teach wherein forming each of the first semiconductor die and the second semiconductor die comprises: forming a base layer material on the substrate; and forming a protrusion on a portion of an upper surface of the base layer material.
Nevertheless, Wang teaches
wherein forming each of the first semiconductor die and the second semiconductor die comprises:
forming a base layer (“under bump metallization interconnects 109” is formed before “first photo resist layer 1000”, para. 0065 FIG. 10A) material on the substrate: and
forming a protrusion (“pillar interconnect 104” para. 0027) on a portion of an upper surface of the base layer material through the opening of the photoresist (“pillar interconnect 104” is formed over “under bump metallization interconnects 109” within “opening 1001”).
Yoneyama and Wang teach bumps with slanted sidewalls. The “under bump metallization interconnects 109” are formed before “first photo resist layer 1000”, leading to “pillar interconnects 104” being formed over the entire top surfaces of individual “under bump metallization interconnects 109”. The “under bump metallization patterns 109” provide a surface for the “pillar interconnects 104” to form successfully and securely: under bump metallization patterns typically contain a barrier layer, seed layer, and/or an adhesion layer to act as a foundation for reliable bump formation, as evidenced in para. 0003 of Tsai et al. US 20120091576 A1 and para. 0047 of Lin. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having the “under bump metallization 109” under “primary bumps 31” and “secondary bumps 32” leads to a more reliable conductive contact.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yoneyama with the base and protrusion steps taught in Wang. The base layer is a formation site for the protrusion, such that the conductive contact is securely and reliable formed.
Regarding claim 26, Yoneyama, modified by Wang, teaches the manufacturing method as claimed in claim 25, wherein forming each of the first semiconductor die and the second semiconductor die comprises:
removing a portion of the base layer material (“Portions of the under bump metallization interconnects 109 may also be removed” Wang para. 0062 FIG. 10C), wherein a remaining portion of the base layer material forms the base layer (remaining “under bump metallization interconnects 109” are analogous to the “first and second under bump metallization interconnects 109a and 109b” in FIG. 1), and the base layer and the protrusion form the conductive contact (“first under bump metallization interconnect 109a” and “first pillar interconnect 104a” are a conductive contact over the bump “first pad 107a”, para. 0031).
Regarding claim 27, Yoneyama, modified by Wang, teaches the manufacturing method as claimed in claim 26, wherein the base layer has a lateral surface (“under bump metallization interconnects 109” in Wang have a lateral surface), the protrusion has the outer lateral sidewall (“primary bumps 31” and “secondary bumps 32” in Yoneyama have a lateral sidewall and so do “pillar interconnects 104” in Wang), there is an outer obtuse angle included between the lateral surface of the base layer and the outer lateral sidewall (by depositing “primary bump 31” with the sloped side over “Under bump metallization interconnect 109” with the vertical lateral side, there is an obtuse outer angle between the lateral sides), and the outer obtuse angle is greater than 180° (since the lateral sidewall of “primary bump 31” tapers inward, the outer angle between the vertical lateral sidewall of “under bump metallization interconnect 109” and the sidewall of “primary bump 31” is greater than 180°).
Claims 28 is rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama, modified by Wang, as applied in claim 26, in view of Gatterbauer.
Regarding claim 28, Yoneyama, modified by Wang, teaches the manufacturing method as claimed in claim 26 but fails to teach wherein the protrusion has a protrusion thickness, the base layer has a base thickness, and the protrusion thickness is 3 times to 10 times of the base thickness.
Nevertheless, Gatterbauer teaches
wherein the protrusion has a protrusion thickness (“second layer 104” and “third layer 112” in Gatterbauer each have a thickness between 10nm to 5µm, para. 0087), the base layer has a base thickness (“first layer 102” has a thickness between 10nm to 5µm, para. 0084), and the protrusion thickness is 3 times to 10 times of the base thickness (In example cases taking “first layer 102” with a thickness of 5nm or 100nm and a combined thickness of “third layer 112” with “second layer 104” of 15nm or 300, the thickness of “third layer 112” with “second layer 104” is 3 to 7 times thicker than “first layer 102”).
Yoneyama, modified by Wang, and Gatterbauer teach methods of forming conductive contacts. Gatterbauer teaches ranges of suitable thicknesses for the formation of a conductive contact. Barrier layers, seed layers, adhesion layers, or all together forming an under bump metallurgy are usually relatively thin compared to the bump portion, as evidenced in para. 0045-0048 of Chen et al. US 20230060457 A1. In the case of Gatterbauer, “first layer 102” is a barrier layer and is thinner than the “third layer 112” and “second layer 104” protrusion. The desired overall thickness can depend on the desired standoff between the connected devices. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the ranges of thickness of the “first layer 102”, “third layer 112” and “second layer 104” conductive contact in Gatterbauer are suitable for forming the conductive contact taught between Yoneyama and Wang. The thickness of the protrusion “primary and secondary bumps 31 and 32” can be as much as desired based on the intended separation between “substrate 10” and “semiconductor die 20” in Yoneyama.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yoneyama and Wang with the thicknesses taught in Gatterbauer. The ranges of thicknesses are suitable for forming a conductive contact and the total thickness will depend on the desired standoff between semiconductor die.
Claims 29 is rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama, modified by Wang, as applied in claim 26, in view of Lin.
Yoneyama, modified by Wang, teaches the manufacturing method as claimed in claim 25, wherein forming each of the first semiconductor die and the second semiconductor die comprises:
forming the protrusion on the base layer material (“pillar interconnect 104” is formed over “under bump metallization interconnects 109” within “opening 1001” as taught in Wang);
removing a portion of the base layer material and wherein a remaining portion of the base layer material forms the base layer (remaining “under bump metallization interconnects 109” are analogous to the “first and second under bump metallization interconnects 109a and 109b” in FIG. 1), the base layer has a second lateral surface (“first under bump metallization interconnect 109a” in FIG. 1 and FIG. 10C in Wang is suggested to have a lateral surface).
However, Yoneyama, modified by Wang, fails to teach forming a seed layer material on the substrate; forming the base layer material on the seed layer material; removing a portion of the seed layer material, a remaining portion of the seed layer material forms the seed layer, the seed layer has a first lateral surface, the first lateral surface and the second lateral surface are flush with each other.
Nevertheless, Lin teaches
forming a seed layer material (“blanket conductive layer 148 acts as a seed layer” para. 0042 FIG. 3d) on the substrate (“semiconductor wafer 120” para. 0041);
forming the base layer material (“conductive layer 152” para. 0044) on the seed layer material;
removing a portion of the seed layer material, a remaining portion of the seed layer material forms the seed layer (portion of “seed layer 148” under “photoresist layer 140” is removed by etching, para. 0047 FIG. 3g), the seed layer has a first lateral surface (“seed layer 148” has a lateral surface as suggested in FIG. 3g), the first lateral surface and the second lateral surface are flush with each other (the lateral surfaces of “seed layer 148” and “conductive layer 152” are shown as flush)
Yoneyama, modified by Wang, and Lin teach methods of forming interconnect structures. The examiner understands seed layers are used to help deposit conductive structures more easily by acting as a growth site, as evidenced in para. 0025 of Wu et al. US 20200227368 A1. The “seed layer 148” is understood to act as a growth site for the deposited “conductive layer 152”, which is a barrier layer (para. 0044). “Seed layer 148” and “conductive layer 152” constitute part of a “UBM layer 159” upon which “bumps 162” are formed, analogous to the “under bump metallization interconnects 109” with “pillar interconnects 104” in Wang. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the use of “seed layer 148” improves the ability to deposit the barrier layer “conductive layer 152” and forms part of the under bump metallurgy. By forming the “seed layer 148” as part of the “under bump metallization interconnects 109” and patterning as taught in Wang, the lateral surfaces of “seed layer 148” and “conductive layer 152” will be flush.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yoneyama and Wang with the seed layer taught in Lin. The seed enables easier formation of the base layer.
Claims 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama, in view of Mirkarimi.
Regarding claim 33, Yoneyama teaches
A manufacturing method of a semiconductor device (“a packaging method for producing the packaging structure indicated in FIG. 1” para. 0032), comprising:
forming each of a first semiconductor die (“substrate 10” para. 0032 FIG. 1-2) and a second semiconductor die (“semiconductor device 20” para. 0032), comprising:
forming a conductive bump (“pads 13” on “substrate 10”, para. 0027, and pads upon which “bumps 32” are disposed, FIG. 1) on a substrate; and
forming a conductive contact (“pads 13” on “substrate 10”, para. 0027, and pads upon which “bumps 32” are disposed, FIG. 1) the conductive bump;
connecting the conductive contact of the first semiconductor die opposite to the conductive contact of the second semiconductor die (“bumps 32” para. 0027, connected to “bumps 31” as seen in FIG. 1);
wherein the conductive contact has an outer lateral sidewall (“primary and secondary bumps 31 and 32” have sidewalls), there is an inner acute angle included between the outer lateral sidewall and the substrate (since the sidewalls of “primary bumps 31” are tapered, there is an inner acute angle between sidewalls of “primary bumps 31” and “substrate 10”), and the conductive contact of the first semiconductor die is connected opposite to the conductive contact of the second semiconductor die (“bumps 32” para. 0027, connected to “bumps 31” as seen in FIG. 1).
However, Yoneyama fails to expressly teach the inner acute angle is smaller than 85°, wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact comprises a plurality of grains.
Nevertheless, FIG. 2 appears to suggest “secondary bumps 32” having a slightly smaller inner acute angle than “primary bumps 31”. The “diameter d1” of the top surface of “primary bump 31” is larger than the “diameter d2” of the bottom surface of “secondary bumps 32” before bonding takes place (para. 0042). The examiner understands that for a fixed bump height and fixed greatest width, the slope of the sidewall of the bump will depend on the desired smallest width. For smaller values of “diameters d1 and d2” while having a same greatest width and height, smaller inner acute angles will be required for the bumps. In other words, the inner acute angle of the sidewall is smaller for bumps having larger differences between the widths at opposite ends of the bump. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the taper angle of the “primary bumps 31” depends on the desired “diameter d1” for a given height and a width in contact with “pad 13”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the angle of the inner acute angle is a result effective variable dependent on the difference between the width of the conductive contact at the conductive bump side and the width of the conductive contact at the bonding side. The greater the difference between opposite ends of the conductive contact, the smaller the inner acute angle.
However, Yoneyama fails to teach wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact comprises a plurality of grains, wherein forming each of the first semiconductor die and the second semiconductor die comprises: forming a base layer material on the substrate; and forming a protrusion on a portion of an upper surface of the base layer material.
Nevertheless, Wang teaches
wherein forming each of the first semiconductor die and the second semiconductor die comprises:
forming a base layer (“under bump metallization interconnects 109” is formed before “first photo resist layer 1000”, para. 0065 FIG. 10A) material on the substrate: and
forming a protrusion (“pillar interconnect 104” para. 0027) on a portion of an upper surface of the base layer material through the opening of the photoresist (“pillar interconnect 104” is formed over “under bump metallization interconnects 109” within “opening 1001”).
Yoneyama and Wang teach bumps with slanted sidewalls. The “under bump metallization interconnects 109” are formed before “first photo resist layer 1000”, leading to “pillar interconnects 104” being formed over the entire top surfaces of individual “under bump metallization interconnects 109”. The “under bump metallization patterns 109” provide a surface for the “pillar interconnects 104” to form successfully and securely: under bump metallization patterns typically contain a barrier layer, seed layer, and/or an adhesion layer to act as a foundation for reliable bump formation, as evidenced in para. 0003 of Tsai et al. US 20120091576 A1 and para. 0047 of Lin. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having the “under bump metallization 109” under “primary bumps 31” and “secondary bumps 32” leads to a more reliable conductive contact.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yoneyama with the base and protrusion steps taught in Wang. The base layer is a formation site for the protrusion, such that the conductive contact is securely and reliable formed.
However, Yoneyama, modified by Wang, fails to teach wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact comprises a plurality of grains.
Nevertheless, Mirkarimi teaches
wherein in one of the first semiconductor die (“first element 1” para. 0032 FIG. 2) and the second semiconductor die (“second element 3” para. 0032), the conductive contact comprises a plurality of grains (“conductive feature 28” is a fine gain metal, para. 0038)
Yoneyama, modified by Wang, and Mirkarimi teach interconnect structures. Mirkarimi teaches that copper conductive structures with small grain sizes have a larger grain boundary surface area, have a greater creep rate which improves bonding between conductive patterns, and can be bonded at lower temperatures than conductive structures having larger grains (para. 0028). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that fine grain metal “conductive features 28” such as fine grain copper has properties than improve the bonding speed and quality of the interconnect structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yoneyama and Wang with fine grain conductive contact taught in Mirkarimi. A conductive contact with small grain diameter has a larger grain surface area, increased creep rate, and can bond to another conductive contact at a lower temperature than a conductive contact with larger grain diameter, which lead to an improved bonded structure.
Regarding claim 34, Yoneyama, modified by Wang Mirkarimi, teaches the manufacturing method as claimed in claim 33, each grain has a diameter ranging between 2 nm to 100 nm (“an average grain width less than 20nm, less than 50 nm, less than 100 nm, less than 300 nm, or less than 500 nm” Mirkarimi para. 0038).
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Yonemaya, modified by Wang and Mirkarimi, as applied to claim 33, in view of Chen.
Yoneyama, modified by Wang and Mirkarimi, teaches the manufacturing method as claimed in claim 33, wherein forming each of the first semiconductor die and the second semiconductor die comprises:
removing a portion of the base layer material (“Portions of the under bump metallization interconnects 109 may also be removed” Wang para. 0062 FIG. 10C), wherein a remaining portion of the base layer material forms the base layer (remaining “under bump metallization interconnects 109” are analogous to the “first and second under bump metallization interconnects 109a and 109b” in FIG. 1), and the base layer and the protrusion form the conductive contact (“first under bump metallization interconnect 109a” and “first pillar interconnect 104a” are a conductive contact over the bump “first pad 107a”, para. 0031),
base layer has a lateral surface (“first under bump metallization interconnect 109a” in FIG. 1 and FIG. 10C in Wang is suggested to have a lateral surface), the protrusion has the outer lateral sidewall (“primary bump 31” in Yoneyama has outer lateral sidewall, as well as “first pillar interconnect 104” in Wang), there is an outer obtuse angle included between the lateral surface of the base layer and the outer lateral sidewall (by depositing “primary bump 31” with the sloped side over “under bump metallization interconnects 109” as modified by Wang, with the vertical lateral side, there is an obtuse outer angle between the lateral sides), and the outer obtuse angle is greater than 180° (since the lateral sidewall of “primary bump 31” tapers inward, the outer angle between the vertical lateral sidewall of “under bump metallization interconnect 109” and the sidewall of “primary bump 31” is greater than 180°).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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/ERIC MANUEL MULERO FLORES/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898