DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/25/2026 has been entered.
Response to Amendment
The amendments filed 6/25/2026 have been entered and considered. The amendments to claims 16, 25, and 33 are acknowledged.
The amendments to claim 25 overcome the rejections under 35 U.S.C. 112 presented in the previous Office Action and are therefore withdrawn. The objections to the specification are also withdrawn in view of these amendments.
Response to Arguments
Applicant’s arguments with respect to claim(s) 16, 25, and 33 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 16-21, 24, 30, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. US 20070023483 A1 (hereinafter referred to as Yoneyama), in view of Gatterbauer et al. US 9502248 B1 (hereinafter referred to as Gatterbauer), in view of Choi et al. US 20170148753 A1 (hereinafter referred to as Choi).
Regarding claim 16, Yoneyama teaches
A manufacturing method of a semiconductor device (“a packaging method for producing the packaging structure indicated in FIG. 1” para. 0032), comprising:
forming each of a first semiconductor die (“substrate 10” para. 0032 FIG. 1-2) and a second semiconductor die (“semiconductor device 20” para. 0032), comprising:
forming a conductive bump on a substrate (“pads 13” on “substrate 10”, para. 0027, and pads upon which “bumps 32” are disposed, FIG. 1);
forming a conductive contact (“bumps 31” para. 0027) on the conductive bump, wherein the conductive contact has an outer lateral sidewall (“bumps 31” have a sloped outer sidewall), there is an inner acute angle included between the outer lateral sidewall and the substrate (since the sidewalls of “primary bumps 31” are tapered, there is an inner acute angle between sidewalls of “primary bumps 31” and “substrate 10”),
connecting a conductive contact of the first semiconductor die opposite to the conductive contact of the second semiconductor die (“bumps 32” para. 0027, connected to “bumps 31” as seen in FIG. 1),
However, Yoneyama fails to expressly teach the inner acute angle is smaller than 85°, forming a photoresist on the substrate, wherein the photoresist has an opening having an inner lateral sidewall, there is an outer acute angle included between the inner lateral sidewall and the substrate, and the outer acute angle is smaller than 85°, and forming the conductive contact through the opening of the photoresist, wherein forming each of the first semiconductor die and the second semiconductor die comprises: before forming the photoresist on the substrate, forming the base layer material on the substrate: and after forming the photoresist on the substrate, forming a protrusion on a portion of an upper surface of the base layer material through the opening of the photoresist.
Nevertheless, Gatterbauer teaches
the inner acute angle is smaller than 85° (“second layer stack 514” has an inner “angle 102w” as shown in FIG. 5B, para. 0075. The examiner understands the “second layer stack 514” in FIG 5C and 6C are similar with the exception of the deposition process, para. 0085-0087.),
forming a photoresist (“second mask structure 204” para. 0087, showing as element 202 in FIG. 6A-6C) on the substrate (“surface 111” para. 0085), wherein the photoresist has an opening (“second opening 204o” para. 0049, not seen in FIG. 6A-6B but analogous to that in FIG. 3C and having a common “second extension 204d”) having an inner lateral sidewall (not shown in FIG. 6A-6C but the examiner understands “sidewall 204s” in FIG. 5B is the same as the sidewall of “second mask structure 204” in FIG. 6A-6C), there is an outer acute angle included between the inner lateral sidewall and the substrate (there is an angle between “204s” and “surface 111” in “opening 204o”), and the outer acute angle is smaller than 85° (as is analogous in FIG. 3C, “second angle 204w in the range from about 70° to about 85°” para. 0045.), and
forming a conductive contact (“second layer 104” and “third layer 112” on “first layer 102”, para. 0085-0086) through the opening of the photoresist,
forming a base layer material (“first layer 102”, para. 0085) on the substrate,
after forming the photoresist on the substrate, forming a protrusion (“second layer 104” and “third layer 112”) on a portion of an upper surface of the base layer material through the opening of the photoresist (“second layer 104” and “third layer 112” are formed over “first layer 102”).
Yoneyama and Gatterbauer teach contacts having sloped sidewalls. “Bumps 31, 32” in Yoneyama are made by a wirebonding method (para. 0027, 0030). The conductive contact comprising “first layer 102”, “second layer 104” and “third layer 112” in Gatterbauer are formed by physical vapor deposition such as sputtering in the openings of different masks (para. 0027, 0030, 0056). Because multiple openings can be made in the masks, a plurality of “second layer stacks 514” can be made simultaneously instead of by wirebonding. Furthermore, the outer acute angle of the “second mask pattern 204” and the inner acute angle of the conductive pattern do not need to be the same; either can be between about 70° to about 85°. The range of the “angle 102w” overlaps with the claimed range. Because the conductive pattern is formed by sputtering, the examiner understands the inner acute angle is subject to the deposition angle which can depend on the position of the sputtering target. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the deposition and mask lift-off method of forming conductive contacts in Gatterbauer is a suitable way to form multiple contacts with acute angles simultaneously. The conductive pattern can be formed in a photomask that has a range of appropriate outer acute angles.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Yoneyama with the contact formation method taught in Gatterbauer. The plurality of contacts in Gatterbauer can be made at the same time with acute inner angles using photoresists with varying outer acute angles.
However, Yoneyama, modified by Gatterbauer, fails to teach, before forming the photoresist on the substrate, forming the base layer material on the substrate, wherein after forming the photoresist on the substrate, the photoresist covers a portion of the base layer material which is not exposed from the opening, wherein the protrusion is made of a material the same as that of the base layer material.
Nevertheless, Choi teaches
before forming the photoresist on the substrate (“mold layer 39”, formed using a photolithography process, para. 0093 FIG. 17), forming a base layer material (“second seed layer 36” para. 0092 FIG. 16) on the substrate (“substrate 21” para. 0092);
wherein after forming the photoresist on the substrate, the photoresist covers a portion of the base layer material which is not exposed from the opening (“mold layer 39” is formed on and covers “second seed layer 36” except at “holes 39H”, para. 0093);
wherein the protrusion (“conductive support layers 41” para. 0095) is made of a material the same as that of the base layer material (“second seed layer 36” is copper and “conductive support layers 41” are made of copper, para. 0092 and 0096).
Yoneyama, modified by Gatterbauer, and Choi teach multilayer conductive contacts made in photoresists. The protrusion “conductive support layer 41” in Choi is formed on a multilayer “seed layer 37”, the uppermost layer being a copper “second seed layer 36”. The examiner understands seed layers act as growth sites for conductors that may impart a crystal orientation to the grown material. As further seen in Huang et al. FIG. 3-7 para. 0019-0022 and Wang et al. US 20240006361 A1 FIG. 10A-10C para. 0056-0062, the process steps of forming a base layer across a substrate and covering portions thereof with a photoresist are well-known in the art. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that base layer “first layer 102” from Gatterbauer can be made like “second seed layer 36” so it may serve as a growth site for the protrusion of the same material.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the manufacturing method taught between Yoneyama and Gatterbauer with the base layer photoresist formation steps taught in Choi. A base layer having the same material as the protrusion can serve as a growth site for the protrusion. Forming the base layer over the substrate and forming a patterned photoresist thereupon is a known method of forming conductive contacts comprising a base layer.
Regarding claim 17, Yoneyama, modified by Gatterbauer and Choi, teaches the manufacturing method as claimed in claim 16 wherein forming each of the first semiconductor die and the second semiconductor die comprises:
removing the photoresist from the substrate (“removing the mold layer 39”, Choi para. 0106 FIG. 22); and
removing a portion of the base layer material (“seed layer 37 is etched” Choi para. 0114 FIG. 24A), wherein a remaining portion of the base layer material forms the base layer (remaining “seed layer 37”, and therefore “second seed layer 36”, under “conductive support 41” is the base layer of the conductive contact, analogous to “first layer 102” from Gatterbauer), and the base layer and the protrusion form the conductive contact (remaining “seed layer 37” and “conductive support layer 41” are a conductive contact, analogous to “first layer 102” with “second layer 104” and “third layer 112” from Gatterbauer).
Regarding claim 18, Yoneyama, modified by Gatterbauer and Choi, teaches the manufacturing method as claimed in claim 17, wherein the base layer has a lateral surface (“first layer 102” in FIG. Gatterbauer FIG. 6C, as well as “second seed layer 36” in FIG. 24A in Choi, are understood to have a lateral surface), the protrusion has the outer lateral sidewall (“primary bump 31” in Yoneyama has outer lateral sidewall, as well as “second layer 104” and “third layer112” in Gatterbauer), there is an outer obtuse angle included between the lateral surface of the base layer and the outer lateral sidewall (by depositing “primary bump 31” with the sloped side over “first layer 012”, now extending to the lower edge of “third layer 112” as modified by “second seed layer 36” from Choi with the vertical lateral side, there is an obtuse outer angle between the lateral sides), and the outer obtuse angle is greater than 180° (since the lateral sidewall of “primary bump 31” tapers inward, the outer angle between the vertical lateral sidewall of “first layer 102” and the sidewall of “primary bump 31” is greater than 180°).
Regarding claim 19, Yoneyama, modified by Gatterbauer and Choi, teaches the manufacturing method as claimed in claim 17, wherein the protrusion has a protrusion thickness (“second layer 104” and “third layer 112” in Gatterbauer each have a thickness between 10nm to 5µm, para. 0087), the base layer has a base thickness (“first layer 102” has a thickness between 10nm to 5µm, para. 0084), and the protrusion thickness is 3 times to 10 times of the base thickness (In example cases taking “first layer 102” with a thickness of 5nm or 100nm and a combined thickness of “third layer 112” with “second layer 104” of 15nm or 300, the thickness of “third layer 112” with “second layer 104” is 3 to 7 times thicker than “first layer 102”).
Regarding claim 20, Yoneyama, modified by Gatterbauer and Choi, teaches the manufacturing method as claimed in claim 16, wherein forming each of the first semiconductor die and the second semiconductor die comprises:
forming a seed layer material (“first seed layer 35” para. 0092 FIG. 16) on the substrate (“substrate 21” para. 0092);
forming the protrusion on the base layer material through the opening of the photoresist (“conductive support layer 41” is formed over “second seed layer 36” within “hole 39H” as taught in Choi);
removing the photoresist from the substrate (“removing the mold layer 39”, Choi para. 0106 FIG. 22); and
removing a portion of the base layer material and a portion of the seed layer material (“seed layer 37 is etched”, which comprises “first seed layer 35” and “second seed layer 36” Choi para. 0114) wherein a remaining portion of the base layer material forms the base layer (remaining “seed layer 37”, and therefore “second seed layer 36”, under “conductive support 41” is the base layer of the conductive contact, analogous to “first layer 102” from Gatterbauer), a remaining portion of the seed layer material forms the seed layer (portion of “first seed layer 35” under “conductive support layer 41”), the seed layer has a first lateral surface (“first seed layer 35” has a lateral surface as suggested in FIG. 24A), the base layer has a second lateral surface (“first layer 102” in FIG. Gatterbauer FIG. 6C, as well as “second seed layer 36” in FIG. 24A in Choi, are understood to have a lateral surface), the first lateral surface and the second lateral surface are flush with each other (the lateral surfaces of “first seed layer 35” and “second seed layer 36” are shown as flush).
Regarding claim 21, Yoneyama, modified by Gatterbauer and Choi, teaches the manufacturing method as claimed in claim 16, in one of the first semiconductor die and the second semiconductor die, the inner acute angle ranges between 55° and 85° (As discussed in the rejection of claim 16, the inner acute angle is a result effective variable depending on the desired smallest width of “primary bump 31”. Furthermore, “sidewall 104s which is inclined with respect to the surface 111 by an angle 102w in the range from about 70° to about 85°” in para. 0075 of Gatterbauer).
Regarding claim 24, Yoneyama, modified by Gatterbauer and Choi, teaches manufacturing method as claimed in claim 16, wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact has a width gradually decreasing in a direction away from the substrate (“primary and secondary bumps 31 and 32” have tapered sides, para. 0039 FIG. 1).
Regarding claim 30, Yoneyama, modified by Gatterbauer and Choi, teaches the manufacturing method as claimed in claim 16, in one of the first semiconductor die and the second semiconductor die, the inner acute angle ranges between 55° and 85° (As discussed in the rejection of claim 16, the inner acute angle is a result effective variable depending on the desired smallest width of “primary bump 31”. Furthermore, “sidewall 104s which is inclined with respect to the surface 111 by an angle 102w in the range from about 70° to about 85°” para. 0075 of Gatterbauer).
Regarding claim 32, Yoneyama, modified by Gatterbauer and Choi, teaches the manufacturing method as claimed in claim 16, wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact has a width gradually decreasing in a direction away from the substrate (“primary and secondary bumps 31 and 32” have tapered sides, para. 0039 FIG. 1).
Claims 22-23 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama, Gatterbauer, and Choi as applied in claim 16, in view of Mirkarimi et al. WO 2022187402 A1 (hereinafter referred to as Mirkarimi).
Regarding claim 22, Yoneyama, modified by Gatterbauer and Choi, teaches the manufacturing method as claimed in claim 16 but fails to teach in one of the first semiconductor die and the second semiconductor die, the conductive contact comprises a plurality of grains, and each grain has a diameter ranging between 2 nm to 100 nm.
Nevertheless, Mirkarimi teaches
in one of the first semiconductor die (“first element 1” para. 0032 FIG. 2) and the second semiconductor die (“second element 3” para. 0032), the conductive contact comprises a plurality of grains (“conductive feature 28” is a fine gain metal, para. 0038), and each grain has a diameter ranging between 2 nm to 100 nm (“an average grain width less than 20nm, less than 50 nm, less than 100 nm, less than 300 nm, or less than 500 nm” para. 0038).
Yoneyama, modified by Gatterbauer and Choi, and Mirkarimi teach interconnect structures. Mirkarimi teaches that copper conductive structures with smaller grain sizes have a larger grain boundary surface area, have a greater creep rate which improves bonding between conductive patterns, and can be bonded at lower temperatures than conductive structures having larger grains (para. 0028). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that fine grain metal “conductive features 28” such as fine grain copper has properties than improve the bonding speed and quality of the interconnect structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yoneyama, Gatterbauer, and Choi with fine grain conductive contact taught in Mirkarimi. A conductive contact with small grain diameter has a larger grain surface area, increased creep rate, and can bond to another conductive contact at a lower temperature than a conductive contact with larger grain diameter, which lead to an improved bonded structure.
Regarding claim 23, Yoneyama, modified by Gatterbauer and Choi, teaches the manufacturing method as claimed in claim 16 but fails to teach wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact of the first semiconductor die and the conductive contact of the second semiconductor die are connected in a connection, and the connection has a width ranging between 0.6 µm to 2.5 µm.
Nevertheless, Mirkarimi teaches
Wherein in one of the first semiconductor die (“first element 1” para. 0032 FIG. 2) and the second semiconductor die (“second element 3” para. 0032), the conductive contact of the first semiconductor die (“conductive feature 28” para. 0038) and the conductive contact of the second semiconductor die (“conductive feature 48” para. 0045) are connected in a connection (“first element 1 can be bonded to the second element 3” by the conductive features, para. 0045 FIG. 2), and the connection has a width ranging between 0.6 µm to 2.5 µm (“a width of the conductive features 28 may range in a range of, for example, 0.3 µm to 60µm, 0.5 µm to 40 µm, or 0.5 m to 20 µm” and “conductive features 48” appear to have substantially similar width in FIG. 2).
Yoneyama, modified by Gatterbauer and Choi, and Mirkarimi teach interconnect structures. The conductive contacts taught between Yoneyama, Gatterbauer, and Choi are larger than 5µm (Gatterbauer para. 0040). The “conductive features” in Mirkarimi can be as small as 0.3µm such that the interconnected structure can have a total width between 0.3 µm and 60µm even including the barrier layers (para. 0035). As technology as progressed, semiconductor devices continue to require greater integration with other devices and signals paths. This leads to more interconnections between devices while also minimizing the sizes of the packages, such that interconnect densities must also increase. Interconnect density can be increased by forming contact structures with smaller diameters. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the interconnect sizes taught in Mirkarimi can be used for devices that require high density interconnects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yoneyama, Gatterbauer, and Choi with the conductive contact sizes taught in Mirkarimi. Smaller conductive contacts are suitable for devices that require a high density of interconnects.
Regarding claim 31, Yoneyama, modified by Gatterbauer and Choi, teaches the manufacturing method as claimed in claim 16 but fails to teach wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact of the first semiconductor die and the conductive contact of the second semiconductor die are connected in a connection, and the connection has a width ranging between 0.6 µm to 2.5 µm.
Nevertheless, Mirkarimi teaches
Wherein in one of the first semiconductor die (“first element 1” para. 0032 FIG. 2) and the second semiconductor die (“second element 3” para. 0032), the conductive contact of the first semiconductor die (“conductive feature 28” para. 0038) and the conductive contact of the second semiconductor die (“conductive feature 48” para. 0045) are connected in a connection (“first element 1 can be bonded to the second element 3” by the conductive features, para. 0045 FIG. 2), and the connection has a width ranging between 0.6 µm to 2.5 µm (“a width of the conductive features 28 may range in a range of, for example, 0.3 µm to 60µm, 0.5 µm to 40 µm, or 0.5 m to 20 µm” and “conductive features 48” appear to have substantially similar width in FIG. 2).
Yoneyama, modified by Gatterbauer and Choi, and Mirkarimi teach interconnect structures. The conductive contacts taught between Yoneyama, Gatterbauer, and Choi are larger than 5µm (Gatterbauer para. 0040). The “conductive features” in Mirkarimi can be as small as 0.3µm such that the interconnected structure can have a total width between 0.3 µm and 60µm even including the barrier layers (para. 0035). As technology as progressed, semiconductor devices continue to require greater integration with other devices and signals paths. This leads to more interconnections between devices while also minimizing the sizes of the packages, such that interconnect densities must also increase. Interconnect density can be increased by forming contact structures with smaller diameters. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the interconnect sizes taught in Mirkarimi can be used for devices that require high density interconnects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yoneyama, Gatterbauer, and Choi with the conductive contact sizes taught in Mirkarimi. Smaller conductive contacts are suitable for devices that require a high density of interconnects.
Claim 25-27 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama, in view of Gaterbuaer, and in view of Choi.
Yoneyama teaches
A manufacturing method of a semiconductor device (“a packaging method for producing the packaging structure indicated in FIG. 1” para. 0032), comprising:
forming each of a first semiconductor die (“substrate 10” para. 0032 FIG. 1-2) and a second semiconductor die (“semiconductor device 20” para. 0032), comprising:
forming a conductive bump (“pads 13” on “substrate 10”, para. 0027, and pads upon which “bumps 32” are disposed, FIG. 1) on a substrate (“substrate 10”); and
forming a conductive contact (“pads 13” on “substrate 10”, para. 0027, and pads upon which “bumps 32” are disposed, FIG. 1) the conductive bump;
connecting the conductive contact of the first semiconductor die opposite to the conductive contact of the second semiconductor die (“bumps 32” para. 0027, connected to “bumps 31” as seen in FIG. 1);
wherein the conductive contact has an outer lateral sidewall (“primary and secondary bumps 31 and 32” have sidewalls), there is an inner acute angle included between the outer lateral sidewall and the substrate (since the sidewalls of “primary bumps 31” are tapered, there is an inner acute angle between sidewalls of “primary bumps 31” and “substrate 10”), and the conductive contact of the first semiconductor die is connected opposite to the conductive contact of the second semiconductor die (“bumps 32” para. 0027, connected to “bumps 31” as seen in FIG. 1).
However, Yoneyama fails to expressly teach forming a base layer material on the substrate and the conductive bump; and forming a photoresist on the substrate, wherein the photoresist has an opening, and the photoresist covers a portion of the base layer material which is not exposed from the opening; the inner acute angle is smaller than 85°, wherein forming each of the first semiconductor die and the second semiconductor die comprises; forming a protrusion on a portion of an upper surface of the base layer material, wherein the protrusion is made of a material the same as that of the base layer material.
Nevertheless, Gatterbauer teaches
the inner acute angle is smaller than 85° (“second layer stack 514” has an inner “angle 102w” as shown in FIG. 5B, para. 0075.)
Yoneyama and Gatterbauer teach contacts having sloped sidewalls. “Bumps 31, 32” in Yoneyama are made by a wirebonding method (para. 0027, 0030). The conductive contact comprising “first layer 102”, “second layer 104” and “third layer 112” in Gatterbauer are formed by physical vapor deposition such as sputtering in the openings of different masks (para. 0027, 0030, 0056). Because multiple openings can be made in the masks, a plurality of “second layer stacks 514” can be made simultaneously instead of by wirebonding. The range of the “angle 102w” overlaps with the claimed range. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the deposition and mask lift-off method of forming conductive contacts in Gatterbauer is a suitable way to form multiple contacts with acute angles simultaneously. The conductive pattern can be formed in a photomask that has a range of appropriate outer acute angles.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Yoneyama with the contact formation method taught in Gatterbauer. The plurality of contacts in Gatterbauer can be made at the same time with acute inner angles using photoresists with varying outer acute angles.
However, Yoneyama, modified by Gaterbauer, fails to teach forming a base layer material on the substrate and the conductive bump; and forming a photoresist on the substrate, wherein the photoresist has an opening, and the photoresist covers a portion of the base layer material which is not exposed from the opening; wherein forming each of the first semiconductor die and the second semiconductor die comprises; forming a protrusion on a portion of an upper surface of the base layer material, wherein the protrusion is made of a material the same as that of the base layer material.
Nevertheless, Choi teaches
forming a base layer material (“second seed layer 36” para. 0092 FIG. 16) on the substrate (“substrate 21” para. 0092); and
forming a photoresist (“mold layer 39”, formed using a photolithography process, para. 0093 FIG. 17) on the substrate, wherein the photoresist has an opening (hole 39H” para. 0093), and the photoresist covers a portion of the base layer material which is not exposed from the opening (“mold layer 39” is formed on and covers “second seed layer 36” except at “holes 39H”, para. 0093);
wherein forming each of the first semiconductor die and the second semiconductor die comprises:
forming a protrusion (“conductive support layers 41” para. 0095) on a portion of an upper surface of the base layer material through the opening of the photoresist (“conductive support layer 41” is formed over “second seed layer 36” within “hole 39H”, para. 0096 FIG. 19),
wherein the protrusion is made of a material the same as that of the base layer material (“second seed layer 36” is copper and “conductive support layers 41” are made of copper, para. 0092 and 0096).
Yoneyama, modified by Gatterbauer, and Choi teach the formation of conductive contacts on semiconductor devices. The protrusion “conductive support layer 41” in Choi is formed on a multilayer “seed layer 37”, the uppermost layer being a copper “second seed layer 36”. The examiner understands seed layers act as growth sites for conductors that may impart a crystal orientation to the grown material. As further seen in Huang et al. FIG. 3-7 para. 0019-0022 and Wang et al. US 20240006361 A1 FIG. 10A-10C para. 0056-0062, the process steps of forming a base layer across a substrate and covering portions thereof with a photoresist are well-known in the art. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that base layer “second seed layer 36” may serve as a growth site for the protrusion of the same material.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the manufacturing method taught between Yoneyama and Gaterbauer with the base layer photoresist formation steps taught in Choi. A base layer having the same material as the protrusion can serve as a growth site for the protrusion. Forming the base layer over the substrate and forming a patterned photoresist thereupon is a known method of forming conductive contacts comprising a base layer.
Regarding claim 26, Yoneyama, modified by Gaterbauer and Choi, teaches the manufacturing method as claimed in claim 25, wherein forming each of the first semiconductor die and the second semiconductor die comprises:
removing a portion of the base layer material (“seed layer 37 is etched”, which comprises “first seed layer 35” and “second seed layer 36” Choi para. 0114 FIG. 24A), wherein a remaining portion of the base layer material forms the base layer (remaining “seed layer 37”, and therefore “second seed layer 36”, under “conductive support 41”), and the base layer and the protrusion form the conductive contact (remaining “second seed layer 36” and “conductive support 41” comprise the conductive contact in Choi. As combined, “second seed layer 36” and “primary bumps 31” comprise the conductive contact.).
Regarding claim 27, Yoneyama, modified by Gaterbauer and Choi, teaches the manufacturing method as claimed in claim 26, wherein the base layer has a lateral surface (“second seed layer 36” is shown in FIG. 24A in Choi is shown having a lateral surface), the protrusion has the outer lateral sidewall (“primary bumps 31” and “secondary bumps 32” in Yoneyama have a lateral sidewall), there is an outer obtuse angle included between the lateral surface of the base layer and the outer lateral sidewall (by depositing “primary bump 31” with the sloped side over “second seed layer 36” with the vertical lateral side, there is an obtuse outer angle between the lateral sides), and the outer obtuse angle is greater than 180° (since the lateral sidewall of “primary bump 31” tapers inward, the outer angle between the vertical lateral sidewall of “second seed layer 36” and the sidewall of “primary bump 31” is greater than 180°).
Regarding claim 28, Yoneyama, modified by Gaterbaur and Choi, teaches the manufacturing method as claimed in claim 26. Yoneyama and Choi fail to teach wherein the protrusion has a protrusion thickness, the base layer has a base thickness, and the protrusion thickness is 3 times to 10 times of the base thickness.
Nevertheless, Gatterbauer teaches
wherein the protrusion has a protrusion thickness (“second layer 104” and “third layer 112” in Gatterbauer each have a thickness between 10nm to 5µm, para. 0087), the base layer has a base thickness (“first layer 102” has a thickness between 10nm to 5µm, para. 0084), and the protrusion thickness is 3 times to 10 times of the base thickness (In example cases taking “first layer 102” with a thickness of 5nm or 100nm and a combined thickness of “third layer 112” with “second layer 104” of 15nm or 300, the thickness of “third layer 112” with “second layer 104” is 3 to 7 times thicker than “first layer 102”).
Yoneyama, modified by Choi, and Gatterbauer teach methods of forming conductive contacts. Gatterbauer teaches ranges of suitable thicknesses for the formation of a conductive contact. Barrier layers, seed layers, adhesion layers, or all together forming an under bump metallurgy are usually relatively thin compared to the bump portion, as evidenced in para. 0045-0048 of Chen et al. US 20230060457 A1. In the case of Gatterbauer, “first layer 102” is a barrier layer and is thinner than the “third layer 112” and “second layer 104” protrusion. Likewise, “seed layer 37”, and therefore “second seed layer 36”, has a smaller thickness than “conductive support layer 41 (Choi para. 0056). The desired overall thickness can depend on the desired standoff between the connected devices. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the ranges of thickness of the “first layer 102”, “third layer 112” and “second layer 104” conductive contact in Gatterbauer are suitable for forming the conductive contact taught between Yoneyama and Choi. The thickness of the protrusion “primary and secondary bumps 31 and 32” can be as much as desired based on the intended separation between “substrate 10” and “semiconductor die 20” in Yoneyama.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the method taught between Yoneyama, Gatterbauer, and Choi The ranges of thicknesses are suitable for forming a conductive contact and the total thickness will depend on the desired standoff between semiconductor die.
Regarding claim 29, Yoneyama, modified Gaterbauer and Choi, teaches the manufacturing method as claimed in claim 25, wherein forming each of the first semiconductor die and the second semiconductor die comprises:
forming a seed layer material (“first seed layer 35” para. 0092 FIG. 16) on the substrate (“substrate 21” para. 0092);
forming the protrusion on the base layer material (“conductive support layer 41” is formed over “second seed layer 36” as taught in Choi);
removing a portion of the base layer material and a portion of the seed layer material (“seed layer 37 is etched”, which comprises “first seed layer 35” and “second seed layer 36” Choi para. 0114) wherein a remaining portion of the base layer material forms the base layer (remaining “seed layer 37”, and therefore “second seed layer 36”, under “conductive support 41”), a remaining portion of the seed layer material forms the seed layer (portion of “first seed layer 35” under “conductive support layer 41”), the seed layer has a first lateral surface (“first seed layer 35” has a lateral surface as suggested in FIG. 24A), the base layer has a second lateral surface ( “second seed layer 36” is shown as having a lateral side surface in FIG. 24A in Choi), the first lateral surface and the second lateral surface are flush with each other (the lateral surfaces of “first seed layer 35” and “second seed layer 36” are shown as flush).
Claims 33-35 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama, in view of Gatterbauer, in view of Choi, and in view of Mirkarimi.
Regarding claim 33, Yoneyama teaches
A manufacturing method of a semiconductor device (“a packaging method for producing the packaging structure indicated in FIG. 1” para. 0032), comprising:
forming each of a first semiconductor die (“substrate 10” para. 0032 FIG. 1-2) and a second semiconductor die (“semiconductor device 20” para. 0032), comprising:
forming a conductive bump (“pads 13” on “substrate 10”, para. 0027, and pads upon which “bumps 32” are disposed, FIG. 1) on a substrate; and
forming a conductive contact (“pads 13” on “substrate 10”, para. 0027, and pads upon which “bumps 32” are disposed, FIG. 1) the conductive bump;
connecting the conductive contact of the first semiconductor die opposite to the conductive contact of the second semiconductor die (“bumps 32” para. 0027, connected to “bumps 31” as seen in FIG. 1);
wherein the conductive contact has an outer lateral sidewall (“primary and secondary bumps 31 and 32” have sidewalls), there is an inner acute angle included between the outer lateral sidewall and the substrate (since the sidewalls of “primary bumps 31” are tapered, there is an inner acute angle between sidewalls of “primary bumps 31” and “substrate 10”), and the conductive contact of the first semiconductor die is connected opposite to the conductive contact of the second semiconductor die (“bumps 32” para. 0027, connected to “bumps 31” as seen in FIG. 1).
However, Yoneyama fails to expressly teach forming a base layer material on the substrate and the conductive bump; and forming a photoresist on the substrate, wherein the photoresist has an opening, and the photoresist covers a portion of the base layer material which is not exposed from the opening the inner acute angle is smaller than 85°, wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact comprises a plurality of grains, wherein forming each of the first semiconductor die and the second semiconductor die comprises: forming a protrusion on a portion of an upper surface of the base layer material; wherein the protrusion is made of a material the same as that of the base layer material.
Nevertheless, Gatterbauer teaches
the inner acute angle is smaller than 85° (“second layer stack 514” has an inner “angle 102w” as shown in FIG. 5B, para. 0075.)
Yoneyama and Gatterbauer teach contacts having sloped sidewalls. “Bumps 31, 32” in Yoneyama are made by a wirebonding method (para. 0027, 0030). The conductive contact comprising “first layer 102”, “second layer 104” and “third layer 112” in Gatterbauer are formed by physical vapor deposition such as sputtering in the openings of different masks (para. 0027, 0030, 0056). Because multiple openings can be made in the masks, a plurality of “second layer stacks 514” can be made simultaneously instead of by wirebonding. The range of the “angle 102w” overlaps with the claimed range. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the deposition and mask lift-off method of forming conductive contacts in Gatterbauer is a suitable way to form multiple contacts with acute angles simultaneously. The conductive pattern can be formed in a photomask that has a range of appropriate outer acute angles.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Yoneyama with the contact formation method taught in Gatterbauer. The plurality of contacts in Gatterbauer can be made at the same time with acute inner angles using photoresists with varying outer acute angles.
However, Yoneyama, modified by Gatterbauer, fails to teach forming a base layer material on the substrate and the conductive bump; and forming a photoresist on the substrate, wherein the photoresist has an opening, and the photoresist covers a portion of the base layer material which is not exposed from the opening, wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact comprises a plurality of grains, wherein forming each of the first semiconductor die and the second semiconductor die comprises: forming a protrusion on a portion of an upper surface of the base layer material; wherein the protrusion is made of a material the same as that of the base layer material.
Nevertheless, Choi teaches
wherein forming each of the first semiconductor die and the second semiconductor die comprises:
forming a base layer material (“second seed layer 36” para. 0092 FIG. 16) on the substrate (“substrate 21” para. 0092) and the conductive bump (“conductive pad 31” para. 0055; and
forming a photoresist (“mold layer 39”, formed using a photolithography process, para. 0093 FIG. 17) on the substrate, wherein the photoresist has an opening (hole 39H” para. 0093), and the photoresist covers a portion of the base layer material which is not exposed from the opening (“mold layer 39” is formed on and covers “second seed layer 36” except at “holes 39H”, para. 0093); wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact comprises a plurality of grains,
wherein forming each of the first semiconductor die and the second semiconductor die comprises: forming a protrusion (“conductive support layers 41” para. 0095) on a portion of an upper surface of the base layer material (“conductive support layer 41” is formed over “second seed layer 36”, para. 0096 FIG. 19); wherein the protrusion is made of a material the same as that of the base layer material (“second seed layer 36” is copper and “conductive support layers 41” are made of copper, para. 0092 and 0096).
Yoneyama, modified by Gatterbauer, and Choi teach the formation of conductive contacts on semiconductor devices. The protrusion “conductive support layer 41” in Choi is formed on a multilayer “seed layer 37”, the uppermost layer being a copper “second seed layer 36”. The examiner understands seed layers act as growth sites for conductors that may impart a crystal orientation to the grown material. As further seen in Huang et al. FIG. 3-7 para. 0019-0022 and Wang et al. US 20240006361 A1 FIG. 10A-10C para. 0056-0062, the process steps of forming a base layer across a substrate and covering portions thereof with a photoresist are well-known in the art. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that base layer “second seed layer 36” may serve as a growth site for the protrusion of the same material.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the manufacturing method taught in Yoneyama with the base layer photoresist formation steps taught in Choi. A base layer having the same material as the protrusion can serve as a growth site for the protrusion. Forming the base layer over the substrate and forming a patterned photoresist thereupon is a known method of forming conductive contacts comprising a base layer.
However, Yoneyama, modified by Gatterbauer and Choi, fails to teach wherein in one of the first semiconductor die and the second semiconductor die, the conductive contact comprises a plurality of grains.
Nevertheless, Mirkarimi teaches
wherein in one of the first semiconductor die (“first element 1” para. 0032 FIG. 2) and the second semiconductor die (“second element 3” para. 0032), the conductive contact comprises a plurality of grains (“conductive feature 28” is a fine gain metal, para. 0038)
Yoneyama, modified by Choi, and Mirkarimi teach interconnect structures. Mirkarimi teaches that copper conductive structures with small grain sizes have a larger grain boundary surface area, have a greater creep rate which improves bonding between conductive patterns, and can be bonded at lower temperatures than conductive structures having larger grains (para. 0028). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that fine grain metal “conductive features 28” such as fine grain copper has properties than improve the bonding speed and quality of the interconnect structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Yoneyama, Gatterbauer, and Choi with fine grain conductive contact taught in Mirkarimi. A conductive contact with small grain diameter has a larger grain surface area, increased creep rate, and can bond to another conductive contact at a lower temperature than a conductive contact with larger grain diameter, which lead to an improved bonded structure.
Regarding claim 34, Yoneyama, modified by Gatterbauer, Choi and Mirkarimi, teaches the manufacturing method as claimed in claim 33, each grain has a diameter ranging between 2 nm to 100 nm (“an average grain width less than 20nm, less than 50 nm, less than 100 nm, less than 300 nm, or less than 500 nm” Mirkarimi para. 0038).
Regarding claim 35, Yonemaya, modified by Gatterbauer, Choi and Mirkarimi, teaches the manufacturing method as claimed in claim 33, wherein forming each of the first semiconductor die and the second semiconductor die comprises:
removing a portion of the base layer material (“seed layer 37 is etched”, which comprises “first seed layer 35” and “second seed layer 36” Choi para. 0114), wherein a remaining portion of the base layer material forms the base layer (remaining “second seed layer 36” under “conductive support 41” is the base layer of the conductive contact), and the base layer and the protrusion form the conductive contact (remaining “second seed layer 36” and “conductive support 41” comprise the conductive contact in Choi. As combined, “second seed layer 36” and “primary bumps 31” comprise the conductive contact.),
wherein the base layer has a lateral surface (“second seed layer 36” has a lateral surface as suggested in Choi FIG. 24A), the protrusion has the outer lateral sidewall (“primary bump 31” in Yoneyama has outer lateral sidewall), there is an outer obtuse angle included between the lateral surface of the base layer and the outer lateral sidewall (by depositing “primary bump 31” with the sloped side over “second seed layer 36” as modified by Choi with the vertical lateral side, there is an obtuse outer angle between the lateral sides), and the outer obtuse angle is greater than 180° (since the lateral sidewall of “primary bump 31” tapers inward, the outer angle between the vertical lateral sidewall of “second seed layer 36” and the sidewall of “primary bump 31” is greater than 180°).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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/ERIC MANUEL MULERO FLORES/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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