Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 11 is objected to because of the following informalities: “connected the substrate” in line 2. For the sake of compact prosecution, claim 11 is interpreted in the instant Office action as follows: “connected the substrate” is found to be a typographical error and is believed to be equivalent to “connected to the substrate”; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 10-11 is rejected under 35 U.S.C. 103 as being unpatentable over Song (US 20230058485 A1, claiming priority to KR 10-2021-0111229, published as KR-20230029123-A, which was effectively filed 8/23/2021) in view of Lin (US 20210232744 A1) and Leung (US 20070070759 A1).
Regarding independent claim 10, Song discloses an IC package (Fig. 1), comprising:
a substrate (100);
a first dynamic random access memory (DRAM) monolithic die (200; [0029]: “a DRAM device”) in which a first plurality of DRAM arrays are formed (220; [0029]: “circuits” is plural, and each circuit 220 is described singularly as DRAM in [0029]: “such as a DRAM”, thus plural “arrays”), wherein the first plurality of DRAM arrays comprise at least 16GBytes, and the first plurality of DRAM arrays include a first counter electrode on a top portion of the first DRAM monolithic die; the first DRAM monolithic die comprises a first redistribution layer (RDL) (240/251/252) disposed on a bottom portion (See annotated figure designating the bottom and top portions. Note: “top” and “bottom” designations are consistent with Applicant’s disclosure, Fig. 22.) of the first DRAM monolithic die; and
a second DRAM monolithic die (300; [0039]: “a DRAM device”) in which a second plurality of DRAM arrays are formed (320; [0039]: “circuits” is plural, and each circuit 320 is described singularly as DRAM in [0039]: “such as a DRAM”, thus plural “arrays”), wherein the second plurality of DRAM arrays comprise at least 16GBytes, and the second plurality of DRAM arrays comprise a second counter electrode on a top portion of the second DRAM monolithic die; the second DRAM monolithic die comprises a second RDL (340/352) disposed on a bottom portion (See annotated figure designating the bottom and top portions. Note: “top” and “bottom” designations are consistent with Applicant’s disclosure, Fig. 22.) of the second DRAM monolithic die and facing to the first RDL of the first DRAM monolithic die ([0013]: “a face-to-face (F2F) configuration”);
wherein the first DRAM monolithic die and the second DRAM monolithic die are vertically stacked over the substrate (See annotated figure for direction designation) in a staggered manner (horizontally staggered, See annotated figure for direction designation); a bonding area of the first RDL (211/212) is not overlapped with the second DRAM monolithic die (these bonding areas are not vertically overlapped by die 300), the second DRAM monolithic die is electrically connected to the substrate through the first RDL of the first DRAM monolithic die (electrically connected at least by 251) and the second RDL of the second DRAM monolithic die (electrically connected at least by 352).
Illustrated below is a marked and annotated figure of Fig. 1 of Song.
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Song teaches the first and second DRAM monolithic dies, but fails to teach specific capacities for these dies. Thus, Song fails to teach “wherein the first plurality of DRAM arrays comprise at least 16GBytes” and “wherein the second plurality of DRAM arrays comprise at least 16GBytes”.
Lin discloses a DRAM monolithic die ([0085]: “DRAM chip”) in which a plurality of DRAM arrays are formed (the plurality of bits composing the ultimate storage capacity cited below necessarily allows a plurality of groupings, these groupings are being defined here as a “plurality of DRAM arrays”), wherein the plurality of DRAM arrays comprise at least 16GBytes ([0085]: “128 Gb”).
Modifying the first and second monolithic dies of Song to respectively include the array capacities of Lin would arrive at the claimed first and second DRAM monolithic die capacities. A person of ordinary skill in the art before the effective filing date would have had predictable results doing so because in each situation the arrays include the same memory configuration (Song: [0029]: “a DRAM device”; Lin: [0085]: “DRAM chip”). Lin teaches a design incentive that would have prompted adaptation of an alternative DRAM array capacity in that it is a design choice according to design requirement ([0085]: “standard memory density” which is selecting from a plurality of known differing designs, i.e., a standardized design). Thus, the differences between the claimed invention and the prior art were encompassed in known predictable variations of Song’s monolithic die. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed array capacity configuration because it is a known variation based on design incentive that would enable an IC package with greater storage capacity. MPEP 2143(I)(F); MPEP 2144.05(I).
Song in view of Lin fails to teach specific structures of the pluralities of DRAM arrays and therefore fails to teach “the first plurality of DRAM arrays include a first counter electrode on a top portion of the first DRAM monolithic die” and “the second plurality of DRAM arrays comprise a second counter electrode on a top portion of the second DRAM monolithic die”.
Leung discloses a DRAM cell in the same field of endeavor (Fig. 2), wherein the DRAM cell comprises a counter electrode (Vplate; [0017]: “counter-electrode”) on a top portion of the die (See annotated figure for portion designation). Additionally, this DRAM cell comprises a redistribution layer (RDL) (Bit Line; the bit line must be in a layer and it redistributes the charge of capacitor 202 to/from operational circuitry beyond the illustrated schematic, thus a “redistribution layer”) disposed on a bottom portion of this DRAM (See annotated figure for portion designation).
One of ordinary skill in the art before the effective filing date could have combined the counter-electrode and redistribution layer configuration of Leung with the DRAM of Song and Lin in the same way claimed, because Leung teaches the counter electrode and redistribution layer are required structures during operation of DRAM (Vplate is one of the two electrodes of the storage capacitor 202; [0017]: “Storage capacitor”; Bit Line is illustrated as connected in series to the other of the two electrodes of the storage capacitor 202). The results would have been predictable to one of ordinary skill in the art before the effective filing date because in each situation the memory is DRAM (Song: [0029]: “a DRAM device”; Lin: [0085]: “DRAM chip”; Leung: [0017]: “DRAM”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed DRAM structure configuration because it would provide the structures required for an operational DRAM cell in the array. MPEP 2143 (I)(A).
Illustrated below is a marked and annotated figure of Fig. 2 of Leung.
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Regarding claim 11, Song in view of Lin and Leung discloses the IC package according to claim 10 (Song: Fig. 1), wherein a bonding wire (610/620) is connected the substrate with the bonding area (directly connected).
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Song, Lin, and Leung as applied to claim 10 above, and further in view of Kim (US 20220392844 A1, hereinafter Kim ‘844) and Swier (CN 111183016 A).
Regarding claim 12, Song in view of Lin and Leung discloses an integration system (Song: Fig. 1), comprising:
a carrier substrate (100);
a first IC package, wherein the first IC package is bonded to the carrier substrate, wherein the first IC package comprises:
a substrate;
a first monolithic die in which a processing unit circuit is formed; and
a second monolithic die in which a plurality of static random access memory (SRAM) arrays are formed, wherein the plurality of SRAM arrays comprise at least 2GBytes-15GBytes; and
a third monolithic die in which a plurality of dynamic random access memory (DRAM) arrays are formed, wherein the plurality of DRAM arrays comprise at least 16GBytes- 256GBytes;
wherein the first monolithic die, the second monolithic die and the third monolithic die are vertically stacked above the substrate;
a second IC package (Fig. 1: dies 200/300 are grouped together, thus a “package”) being an IC package according to claim 10, wherein the second IC package is bonded to the carrier substrate (bonded by 510); and
a metal shielding case encapsulating the first IC package and the second IC package.
The combination of Song, Lin, and Leung as applied teaches the second IC package, but fails to teach specific system configurations using this package. Thus, Song, Lin and Leung as applied fails to teach “an integration system, comprising:
a carrier substrate;
a first IC package, wherein the first IC package is bonded to the carrier substrate, wherein the first IC package comprises:
a substrate;
a first monolithic die in which a processing unit circuit is formed; and
a second monolithic die in which a plurality of static random access memory (SRAM) arrays are formed, wherein the plurality of SRAM arrays comprise at least 2GBytes-15GBytes; and
a third monolithic die in which a plurality of dynamic random access memory (DRAM) arrays are formed, wherein the plurality of DRAM arrays comprise at least 16GBytes- 256GBytes;
wherein the first monolithic die, the second monolithic die and the third monolithic die are vertically stacked above the substrate;
a second IC package being an IC package according to claim 10, wherein the second IC package is bonded to the carrier substrate; and
a metal shielding case encapsulating the first IC package and the second IC package”.
Kim ‘844 discloses an integration system, comprising:
a carrier substrate (Fig. 7: 100);
a first IC package (200; [0034]: “a vertically stacked plurality of chips”), wherein the first IC package is bonded to the carrier substrate (at least through 50), wherein the first IC package comprises:
a substrate;
a first monolithic die in which a processing unit circuit is formed; and
a second monolithic die in which a plurality of static random access memory (SRAM) arrays are formed, wherein the plurality of SRAM arrays comprise at least 2GBytes-15GBytes; and
a third monolithic die in which a plurality of dynamic random access memory (DRAM) arrays are formed, wherein the plurality of DRAM arrays comprise at least 16GBytes- 256GBytes;
wherein the first monolithic die, the second monolithic die and the third monolithic die are vertically stacked above the substrate;
a second IC package (300 on right) being an IC package (including a plurality of 330, thus a package) according to claim 10, wherein the second IC package is bonded to the carrier substrate (at least through 50); and
a metal shielding case (400e) encapsulating the first IC package and the second IC package (at least partially encapsulating; [0081]: “at least one of, for example, copper (Cu) and steel use stainless (SUS)”).
Modifying the integration system of Song, Lin, and Leung by including a first IC package and metal shielding case in the same way as Kim ‘844 would arrive at the claimed IC package configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Song teaches system configuration may be varied as a design choice according to required system function ([0075]-[0076]: “electronic system 8710” is described according to varied configurations providing different system function). Kim ‘844 provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have a system configuration including the first and second IC packages and metal shielding case in that it would enable an integration system with enhanced performance while protecting against warpage ([0002]: “expanding demands for performance” in combination with [0004]: “warpage is better suppressed across a range of temperatures”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed integration system configuration because it would enable an integration system having enhance performance while protecting against warpage. MPEP 2143 (I)(G).
Song, Lin, Leung, and Kim ‘844 as applied above fails to teach the claimed configuration within the first IC package “wherein the first IC package comprises:
a substrate;
a first monolithic die in which a processing unit circuit is formed; and
a second monolithic die in which a plurality of static random access memory (SRAM) arrays are formed, wherein the plurality of SRAM arrays comprise at least 2GBytes-15GBytes; and
a third monolithic die in which a plurality of dynamic random access memory (DRAM) arrays are formed, wherein the plurality of DRAM arrays comprise at least 16GBytes- 256GBytes;
wherein the first monolithic die, the second monolithic die and the third monolithic die are vertically stacked above the substrate;”.
Tsai discloses a first IC package (Fig. 3E: S1a, an alternative subcomponent interpretation), wherein the first IC package comprises:
a substrate (122);
a first monolithic die (112 erroneously annotated as 121) in which a processing unit circuit is formed ([0012]: selecting “GPU”); and
a second monolithic die (150d) in which a plurality of static random access memory (SRAM) arrays are formed ([0040]: selecting “SRAM”), wherein the plurality of SRAM arrays comprise at least 2GBytes-15GBytes; and
a third monolithic die (150c) in which a plurality of dynamic random access memory (DRAM) arrays are formed ([0040]: selecting “DRAM”), wherein the plurality of DRAM arrays comprise at least 16GBytes- 256GBytes;
wherein the first monolithic die, the second monolithic die and the third monolithic die are vertically stacked above the substrate (these dies are shown as a single vertical stack above substrate 122).
Modifying the first IC package of Song, Lin, Leung, and Kim ‘844 by incorporating the alternative package configuration of Tsai would arrive at the claimed IC package configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because:
Song teaches system configuration may be varied as a design choice according to required system function ([0075]-[0076]: “electronic system 8710” is described according to varied configurations providing different system function).
Tsai teaches the integration system can include additional subcomponents (Fig. 3E: at least subcomponent 200).
Tsai only generally describes utility of the additional subcomponents ([0096] “A plurality of devices”), thus, no particular utility or configuration of the additional subcomponents is required for operation of the integration system.
Tsai teaches IC package configuration may be varied ([0085]: “The number of the die stack structure and the number of the die electrically connected to the die stack structure are not limited in the disclosure”).
Thus, the particular IC package configuration does not appear critical to operation of the integration system and it is a configuration chosen according to package design requirements. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because it appears to be a mere combination of prior art element configurations according to known functional configurations yielding a predictable integration system configuration serving a particular utility. One of ordinary skill in the art before the effective filing date would have been motivated to do so to produce an integration system serving a particular utility. MPEP 2143 (I)(A).
Tsai fails to give explicit detail regarding the specifications of the first, second, and third monolithic dies, and therefore fails to teach “a second monolithic die in which a plurality of static random access memory (SRAM) arrays are formed, wherein the plurality of SRAM arrays comprise at least 2GBytes-15GBytes;
and a third monolithic die in which a plurality of dynamic random access memory (DRAM) arrays are formed, wherein the plurality of DRAM arrays comprise at least l6GBytes-256GBytes”.
Swier discloses a die in which SRAM is formed (pg. 22 of translation: selecting “SRAM”) in which a plurality of SRAM arrays are formed (the plurality of bits composing the ultimate storage capacity cited below necessarily allows a plurality of groupings, these groupings being defined as arrays), wherein the plurality of SRAM arrays comprise at least 2GBytes-15GBytes (pg. 22 of translation: “about 2GB, or more”, this range overlapping the claimed range). Swier teaches a design incentive that would have prompted adaptation of an alternative SRAM capacity in that it is a design choice according to design requirement (pg. 22 of translation: “any number of memory device to provide a given amount of system memory”).
Lin discloses a die in which DRAM is formed ([0085]: “DRAM chip”) in which a plurality of DRAM arrays are formed (the plurality of bits composing the ultimate storage capacity cited below necessarily allows a plurality of groupings, these groupings being defined as arrays), wherein the plurality of DRAM arrays comprise more at least 16GBytes-256GBytes ([0085]: “greater than or equal to…512 Gb” equating to more than 64GBytes, this range overlapping the claimed range). Lin teaches a design incentive that would have prompted adaptation of an alternative DRAM capacity in that it is a design choice according to design requirement ([0085]: selecting from a plurality of known differing designs “standard memory density”).
Modifying the second monolithic die and the third monolithic die of Tsai to respectively include the capacities of Swier and Lin would arrive at the claimed second and third monolithic die configurations. The differences between the claimed invention and the prior art were encompassed in known predictable variations of Tsai’s second and third monolithic dies. One of ordinary skill in the art before the effective filing date, in view of the identified design incentives, could have implemented the claimed variations of the prior art (of Swier and of Lin), and the claimed variations would have been predictable to one of ordinary skill in the art before the effective filing date. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed second and third monolithic die configurations because it would result in an IC package designed for a specific use. MPEP 2143(I)(F); MPEP 2144.05(I).
Regarding claim 13, Song in view of Lin and Leung discloses an integration system (Song: Fig. 1), comprising:
a carrier substrate (100);
a first IC package, wherein the first IC package is bonded to the carrier substrate, wherein the first IC package comprises:
a substrate;
a first monolithic die in which a processing unit circuit is formed; and
a second monolithic die in which a plurality of static random access memory (SRAM) arrays are formed, wherein the plurality of SRAM arrays comprise at least 2GBytes-15GBytes; and
a third monolithic die in which a plurality of dynamic random access memory (DRAM) arrays are formed, wherein the plurality of DRAM arrays comprise at least 16GBytes- 256GBytes;
wherein the first monolithic die, the second monolithic die and the third monolithic die are vertically stacked above the substrate;
a second IC package (Fig. 1: dies 200/300 are grouped together, thus a “package”) being an IC package according to claim 10, wherein the second IC package is bonded to the carrier substrate (bonded by 510);
a first metal shielding case encapsulating the first IC package; and
a third IC package being another IC package according to claim 10, wherein the third IC package is bonded to the carrier substrate; and
a second metal shielding case encapsulating the first IC package, the second IC package, and the third IC package.
The combination of Song, Lin, and Leung as applied teaches the second IC package, but fails to teach specific system configurations using this package. Thus, Jenson, lin and Leung as applied fails to teach “an integration system, comprising:
a carrier substrate;
a first IC package, wherein the first IC package is bonded to the carrier substrate, wherein the first IC package comprises:
a substrate;
a first monolithic die in which a processing unit circuit is formed; and
a second monolithic die in which a plurality of static random access memory (SRAM) arrays are formed, wherein the plurality of SRAM arrays comprise at least 2GBytes-15GBytes; and
a third monolithic die in which a plurality of dynamic random access memory (DRAM) arrays are formed, wherein the plurality of DRAM arrays comprise at least 16GBytes- 256GBytes;
wherein the first monolithic die, the second monolithic die and the third monolithic die are vertically stacked above the substrate;
a second IC package being an IC package according to claim 10, wherein the second IC package is bonded to the carrier substrate;
a first metal shielding case encapsulating the first IC package; and
a third IC package being another IC package according to claim 10, wherein the third IC package is bonded to the carrier substrate; and
a second metal shielding case encapsulating the first IC package, the second IC package, and the third IC package.
Kim ‘844 discloses an integration system, comprising:
a carrier substrate (Fig. 7: 100);
a first IC package (200; [0034]: “a vertically stacked plurality of chips”), wherein the first IC package is bonded to the carrier substrate (at least through 32), wherein the first IC package comprises:
a substrate;
a first monolithic die in which a processing unit circuit is formed; and
a second monolithic die in which a plurality of static random access memory (SRAM) arrays are formed, wherein the plurality of SRAM arrays comprise at least 2GBytes-15GBytes; and
a third monolithic die in which a plurality of dynamic random access memory (DRAM) arrays are formed, wherein the plurality of DRAM arrays comprise at least 16GBytes- 256GBytes;
wherein the first monolithic die, the second monolithic die and the third monolithic die are vertically stacked above the substrate;
a second IC package (300 on right) being an IC package (including a plurality of 330, thus a package) according to claim 10, wherein the second IC package is bonded to the carrier substrate (at least through 50);
a first metal shielding case (430; [0081]: “at least one of, for example, copper (Cu) and steel use stainless (SUS)”) encapsulating the first IC package (at least partially encapsulating); and
a third IC package (300 on left) being another IC package according to claim 10, wherein the third IC package is bonded to the carrier substrate (at least through 50); and
a second metal shielding case (440; [0081]: “at least one of, for example, copper (Cu) and steel use stainless (SUS)”) encapsulating the first IC package, the second IC package, and the third IC package (at least partially encapsulating).
Modifying the integration system of Song, Lin, and Leung by including a first and third IC package and first and second metal shielding case in the same way as Kim ‘844 would arrive at the claimed IC package configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Song teaches system configuration may be varied as a design choice according to required system function ([0075]-[0076]: “electronic system 8710” is described according to varied configurations providing different system function). Kim ‘844 provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have a system configuration including the first, second, and third IC packages and first and second metal shielding cases in that it would enable an integration system with enhanced performance while protecting against warpage ([0002]: “expanding demands for performance” in combination with [0004]: “warpage is better suppressed across a range of temperatures”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed integration system configuration because it would enable an integration system having enhance performance while protecting against warpage. MPEP 2143 (I)(G).
Song, Lin, Leung, and Kim ‘844 as applied above fails to teach the claimed configuration within the first IC package “wherein the first IC package comprises:
a substrate;
a first monolithic die in which a processing unit circuit is formed; and
a second monolithic die in which a plurality of static random access memory (SRAM) arrays are formed, wherein the plurality of SRAM arrays comprise at least 2GBytes-15GBytes; and
a third monolithic die in which a plurality of dynamic random access memory (DRAM) arrays are formed, wherein the plurality of DRAM arrays comprise at least 16GBytes- 256GBytes;
wherein the first monolithic die, the second monolithic die and the third monolithic die are vertically stacked above the substrate;
Tsai discloses a first IC package (Fig. 3E: S1a, an alternative subcomponent interpretation), wherein the first IC package comprises:
a substrate (122);
a first monolithic die (112 erroneously annotated as 121) in which a processing unit circuit is formed ([0012]: selecting “GPU”); and
a second monolithic die (150d) in which a plurality of static random access memory (SRAM) arrays are formed ([0040]: selecting “SRAM”), wherein the plurality of SRAM arrays comprise at least 2GBytes-15GBytes; and
a third monolithic die (150c) in which a plurality of dynamic random access memory (DRAM) arrays are formed ([0040]: selecting “DRAM”), wherein the plurality of DRAM arrays comprise at least 16GBytes- 256GBytes;
wherein the first monolithic die, the second monolithic die and the third monolithic die are vertically stacked above the substrate (these dies are shown as a single vertical stack above substrate 122).
Modifying the first IC package of Song, Lin, Leung, and Kim ‘844 by incorporating the alternative package configuration of Tsai would arrive at the claimed IC package configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because:
Song teaches system configuration may be varied as a design choice according to required system function ([0075]-[0076]: “electronic system 8710” is described according to varied configurations providing different system function).
Tsai teaches the integration system can include additional subcomponents (Fig. 3E: at least subcomponent 200).
Tsai only generally describes utility of the additional subcomponents ([0096] “A plurality of devices”), thus, no particular utility or configuration of the additional subcomponents is required for operation of the integration system.
Tsai teaches IC package configuration may be varied ([0085]: “The number of the die stack structure and the number of the die electrically connected to the die stack structure are not limited in the disclosure”).
Thus, the particular IC package configuration does not appear critical to operation of the integration system and it is a configuration chosen according to package design requirements. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because it appears to be a mere combination of prior art element configurations according to known functional configurations yielding a predictable integration system configuration serving a particular utility. One of ordinary skill in the art before the effective filing date would have been motivated to do so to produce an integration system serving a particular utility. MPEP 2143 (I)(A).
Tsai fails to give explicit detail regarding the specifications of the first, second, and third monolithic dies, and therefore fails to teach “a second monolithic die in which a plurality of static random access memory (SRAM) arrays are formed, wherein the plurality of SRAM arrays comprise at least 2GBytes-15GBytes;
and a third monolithic die in which a plurality of dynamic random access memory (DRAM) arrays are formed, wherein the plurality of DRAM arrays comprise at least l6GBytes-256GBytes”.
Swier discloses a die in which SRAM is formed (pg. 22 of translation: selecting “SRAM”) in which a plurality of SRAM arrays are formed (the plurality of bits composing the ultimate storage capacity cited below necessarily allows a plurality of groupings, these groupings being defined as arrays), wherein the plurality of SRAM arrays comprise at least 2GBytes-15GBytes (pg. 22 of translation: “about 2GB, or more”, this range overlapping the claimed range). Swier teaches a design incentive that would have prompted adaptation of an alternative SRAM capacity in that it is a design choice according to design requirement (pg. 22 of translation: “any number of memory device to provide a given amount of system memory”).
Lin discloses a die in which DRAM is formed ([0085]: “DRAM chip”) in which a plurality of DRAM arrays are formed (the plurality of bits composing the ultimate storage capacity cited below necessarily allows a plurality of groupings, these groupings being defined as arrays), wherein the plurality of DRAM arrays comprise more at least 16GBytes-256GBytes ([0085]: “greater than or equal to…512 Gb” equating to more than 64GBytes, this range overlapping the claimed range). Lin teaches a design incentive that would have prompted adaptation of an alternative DRAM capacity in that it is a design choice according to design requirement ([0085]: selecting from a plurality of known differing designs “standard memory density”).
Modifying the second monolithic die and the third monolithic die of Tsai to respectively include the capacities of Swier and Lin would arrive at the claimed second and third monolithic die configurations. The differences between the claimed invention and the prior art were encompassed in known predictable variations of Tsai’s second and third monolithic dies. One of ordinary skill in the art before the effective filing date, in view of the identified design incentives, could have implemented the claimed variations of the prior art (of Swier and of Lin), and the claimed variations would have been predictable to one of ordinary skill in the art before the effective filing date. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed second and third monolithic die configurations because it would result in an IC package designed for a specific use. MPEP 2143(I)(F); MPEP 2144.05(I).
Regarding claim 14, the combination of Song, Lin, Leung, Kim ‘844, Tsai, and Swier discloses the integration system according to claim 13 (Kim ‘844: Fig. 7), wherein the second metal shielding case is thermally coupled to the first counter electrode on the top portion of the first DRAM monolithic die of the second IC package (the second metal shielding case and the first counter electrode are inclusive within the same integration system, therefore there must necessarily be at least some direct or indirect thermal coupling among these two features), and thermally coupled to the first counter electrode on the top portion of the first DRAM monolithic die of the third IC package (the second metal shielding case and the first counter electrode are inclusive within the same integration system, therefore there must necessarily be at least some direct or indirect thermal coupling among these two features).
Allowable Subject Matter
Claims 1-7, 9, and 15 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 1-7, 9, and 15 is the inclusion of the limitation “a counter electrode; and a first molding or shielding compound encapsulating the first monolithic die, the second monolithic die, and the third monolithic die, wherein a top surface of the counter electrode is revealed and not covered by the first molding or shielding compound” in combination with the other limitations in the claim. For example, prior art of record teaches a counter electrode but fails to teach, or be reasonably combined, to render obvious the claimed combination of limitations “counter electrode” with “revealed and not covered” in combination with all other limitations in claim 1.
Response to Arguments
Applicant's arguments filed 6/12/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 10 that “the cited references […] fails to disclose or suggest the features of […]the first DRAM monolithic die and the second DRAM monolithic die are vertically stacked over the substrate, in a staggered manner; a bonding area of the firs RDL is not overlapped with the t second DRAM monolithic die...” as set forth in the amended independent claim 10”. Remarks at pg. 18.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The claim amendment has introduced new limitation beyond the teachings or suggestions of the prior art of record. Accordingly, Song is relied upon in the instant Office action to teach the contended arrangement of parts.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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