Prosecution Insights
Last updated: April 19, 2026
Application No. 18/099,697

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §103
Filed
Jan 20, 2023
Examiner
TIVARUS, CRISTIAN ALEXANDRU
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
3 (Non-Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
3y 3m
To Grant
94%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
25 granted / 33 resolved
+7.8% vs TC avg
Strong +18% interview lift
Without
With
+18.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
46 currently pending
Career history
79
Total Applications
across all art units

Statute-Specific Performance

§103
54.3%
+14.3% vs TC avg
§102
25.6%
-14.4% vs TC avg
§112
20.1%
-19.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 33 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/16/2025 has been entered. Response to Amendment The Amendment filed on 12/16/2025 has been entered. Claims 1-20 remain pending in the application. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6, 8, 9, 12, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Raschid Jose Bezama et al., (United States Patent Number, US 8,115,303 B2), hereinafter referenced as Bezama, in view of Nakamura et al., (United States Patent Publication Application Number, US 2006/0243504 A1) hereinafter referenced as Nakamura. Regarding claim 1, Bezama teaches a semiconductor device, comprising: a substrate (Fig.9, element #121, column 13, row 43); a semiconductor component disposed on the substrate (Fig.9, element #122, column 13, row 52, is disposed on the substrate, element #121); and a heat dissipation component disposed on the substrate (Fig.9, component formed by the metallic liquid cooling module, element #223 and extensions #242, column 13, rows 36-38, is disposed on top of the substrate, element #121) and having a cavity (Fig.12B, shows element #404 that may be implemented as element #223, column 15, rows 11-12, has a cavity and flow channels #402, column 15, row 21), an inlet and an outlet (Fig.12B, shows element #404 that may be implemented as element #223, column 15, rows 11-12, has an inlet, elements #P1, M1 and an outlet #P2, M2 column 15, rows 29-31), wherein the inlet and the outlet communicate with the cavity (column 15, rows 29-31), wherein the heat dissipation component comprises a main body comprising the cavity (Fig.12B, shows element #404 that may be implemented as element #223, column 15, rows 11-12, has a cavity and flow channels #402, column 15, row 21) Bezama does not teach a first extension portion and a first flank, the inlet is exposed from an outer surface of the first flank, the first extension portion is connected with, protrudes relative to and is perpendicular to an upper surface of the main body and extends in a first direction, and the first flank is connected with the first extension portion and extends in a second direction perpendicular to the first direction. Nakamura teaches an inlet and an outlet, wherein the inlet and the outlet communicate with the cavity (Fig.10A, inlet, element #200 and outlet, element #201 communicate with the cavity inside element #114); wherein the heat dissipation component comprises a main body comprising the cavity (Fig.10A, element #114 comprises a cavity), a first extension portion and a first flank (Fig.10A, extension, element #902, and first flank, element #901), the inlet is exposed from an outer surface of the first flank (Fig.10A, element #200 is exposed from an outer surface of element #901), the first extension portion is connected with, protrudes relative to and is perpendicular to an upper surface of the main body and extends in a first direction (Fig.10B, rotated vertically with 180 degrees, extension, element #902, is connected to and protrudes relative to the top surface of element #114, the inside vertical wall of element #902 is perpendicular to the upper surface of element #114, and element #902 extends in the horizontal direction), and the first flank is connected with the first extension portion and extends in a second direction perpendicular to the first direction (Fig.10B, first flank, element #901 is connected to extension, element #902, and extends in the vertical direction). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Nakamura and disclose wherein the heat dissipation component comprises a main body comprising the cavity, a first extension portion and a first flank, the inlet is exposed from an outer surface of the first flank, the first extension portion is connected with, protrudes relative to, and is perpendicular to an upper surface of the main body and extends in a first direction, and the first flank is connected with the first extension portion and extends in a second direction perpendicular to the first direction. As disclosed by Nakamura, the extensions and the flanks allow for uniform cooling to be achieved without the need for coolant accumulating parts, which improves the thermal characteristics of the heat dissipation structure while enabling no coolant pressure loss (paragraph [0010], rows 1-5). Regarding claim 2, the combination of Bezama and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Bezama further teaches the semiconductor device comprising a thermal interface material (TIM) disposed between the semiconductor component and the heat dissipation component (Fig.9, element #127, column 12, rows 13-15 is disposed between the semiconductor component, element #122 and the heat dissipation component, element #223). Regarding claim 3, the combination of Bezama and Nakamura teaches the semiconductor device of claims 1 and 2 as set forth in the obviousness rejection. Bezama further teaches the semiconductor device as claimed in claim 2, wherein the thermal interface material connects the semiconductor component with the heat dissipation component (Fig.9, element #127, column 12, rows 13-15, connects the semiconductor component, element #122 and the heat dissipation component, element #223). Regarding claim 4, the combination of Bezama and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Bezama further teaches the semiconductor device as claimed in claim 1, further comprising: an adhesive layer disposed between the substrate and the heat dissipation component (Fig.9, element #233, column 13, rows 42-43, is disposed between the substrate, element #121 and the heat dissipation component, element #223). Regarding claim 5, the combination of Bezama and Nakamura teaches the semiconductor device of claims 1 and 5 as set forth in the obviousness rejection. Bezama further teaches the semiconductor device as claimed in claim 4, wherein the adhesive layer connects the substrate and the heat dissipation component (Fig.9, the adhesive layer element #233, column 13, rows 42-43, connects the substrate, element #121 and the heat dissipation component, element #223). Regarding claim 6, the combination of Bezama and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Bezama further teaches the semiconductor device as claimed in claim 1, wherein the heat dissipation component has a terminal surface (Fig.9, bottom surface of element #242) and a recess (Fig.9, recess below element #223 and between elements #242), the recess is recessed with respect to the terminal surface for receiving the semiconductor component (Fig.9, the semiconductor component, element #122 is inside the recess). Regarding claim 8, the combination of Bezama and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Bezama further teaches the semiconductor device as claimed in claim 1, wherein the heat dissipation component (Fig.9, component formed by the metallic liquid cooling module, element #223 and extensions #242, column 13, rows 36-38) has a first lateral surface (Fig.9, surface of the left side of element #242), the substrate has a second lateral surface (Fig.9, surface of the left side of element #121), and the first lateral surface and the second lateral surface are flush with each other (Fig.9, the two surfaces are flushed with each other). Regarding claim 9, the combination of Bezama and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Bezama further teaches the semiconductor device as claimed in claim 1, wherein the heat dissipation component (Fig.9, component formed by the metallic liquid cooling module, element #223 and extensions #242, column 13, rows 36-38) has a first lateral surface (Fig.9, surface of left side of element #223), the substrate has a second lateral surface (Fig.9, surface of the left side of element #121), and the first lateral surface is recessed with respect to the second lateral surface (Fig.9, surface of the left side of element #223 is recess with respect to the surface of the left side of element #121). Regarding claim 12, the combination of Bezama and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Bezama further teaches the semiconductor device as claimed in claim 1, wherein the heat dissipation component is shaped from a single, continuous piece of material (Fig.9, column 13, rows 44-47). Regarding claim 17, Bezama teaches a manufacturing method of a semiconductor device, comprising: disposing a semiconductor component on a substrate (Fig.9, element #122, column 9, row 54 is disposed on a substrate, element #121, column 13, row 43); and disposing a heat dissipation component on the substrate (Fig.9, component formed by the metallic liquid cooling module, element #223 and extensions #242, column 13, rows 36-38, is disposed on the substrate, element #121), wherein the heat dissipation component has a cavity (Fig.12B, shows element #404 that may be implemented as element #223, column 15, rows 11-12, has a cavity and flow channels #402, column 15, row 21). wherein the heat dissipation component comprises a main body comprising the cavity (Fig.12B, shows element #404 that may be implemented as element #223, column 15, rows 11-12, has a cavity and flow channels #402, column 15, row 21). Bezama does not teach a first extension portion and a first flank, the inlet is exposed from an outer surface of the first flank, the first extension portion is connected with, protrudes relative to, and is perpendicular to an upper surface of the main body and extends in a first direction, and the first flank is connected with the first extension portion and extends in a second direction perpendicular to the first direction. Nakamura teaches an inlet and an outlet, wherein the inlet and the outlet communicate with the cavity (Fig.10A, inlet, element #200 and outlet, element #201 communicate with the cavity inside element #114); wherein the heat dissipation component comprises a main body comprising the cavity (Fig.10A, element #114 comprises a cavity), a first extension portion and a first flank (Fig.10A, extension, element #902, and first flank, element #901), the inlet is exposed from an outer surface of the first flank (Fig.10A, element #200 is exposed from an outer surface of element #901), the first extension portion is connected with, protrudes relative to, and is perpendicular to an upper surface of the main body and extends in a first direction (Fig.10B, rotated vertically with 180 degrees, extension, element #902, is connected to and protrudes relative to the top surface of element #114, the inside vertical wall of element #902 is perpendicular to the upper surface of element #114, and element #902 extends in the horizontal direction), and the first flank is connected with the first extension portion and extends in a second direction perpendicular to the first direction (Fig.10B, first flank, element #901 is connected to the extension, element #902, and extends in the vertical direction). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Nakamura and disclose wherein the heat dissipation component comprises a main body comprising the cavity, a first extension portion and a first flank, the inlet is exposed from an outer surface of the first flank, the first extension portion is connected with, protrudes relative to, and is perpendicular to an upper surface of the main body and extends in a first direction, and the first flank is connected with the first extension portion and extends in a second direction perpendicular to the first direction. As disclosed by Nakamura, the extensions and the flanks allow for uniform cooling to be achieved without the need for coolant accumulating parts, which improves the thermal characteristics of the heat dissipation structure, while enabling no coolant pressure loss (paragraph [0010], rows 1-5). Regarding claim 19, the combination of Bezama and Nakamura teaches the method of claim 17 as set forth in the obviousness rejection. Bezama further teaches the manufacturing method as claimed in claim 17, further comprising: disposing the heat dissipation component on the substrate (Fig.9, component formed by the metallic liquid cooling module, element #223 and extensions #242, column 13, rows 37-38, is disposed on the substrate, element #121) through an adhesive layer (Fig.9, element #233, column 13, rows 42-43). Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Bezama, in view of Nakamura and in view of Peng Li et al., (United States Patent Application Publication Number, US 2020/0006192 A1) hereinafter referenced as Li. Regarding claim 7, the combination of Bezama and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. The combination of Bezama and Nakamura does not teach the semiconductor device as claimed in claim 1, wherein there is an air layer among the substrate, the heat dissipation component and the semiconductor component. Li teaches the semiconductor device wherein there is an air layer among the substrate, the heat dissipation component and the semiconductor component (Fig.1, element #170, can be air, paragraph [0023], rows 14-15, is among the substrate, element #102, semiconductor device, element #114 and heat dissipation component element #140, paragraph [0018], rows 4-7). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Li and disclose an air layer among the substrate, the heat dissipation component and the semiconductor component. Because air has low thermal conductivity, the heat generated by the semiconductor component will be dissipated only through the TIM layer and from the TIM layer to the heat dissipation component, preventing it from spreading to other heat sensitive areas of the device that are in contact with the air layer. Claims 10, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Bezama in view of Nakamura, and in view of Nael Zohni et al., (United States Patent Number, US 10,840,192 B2) hereinafter referenced as Zohni. Regarding claim 10, the combination of Bezama and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Bezama teaches the semiconductor device as claimed in claim 1, wherein the heat dissipation component (Fig.9, component formed by the metallic liquid cooling module, element #223 and extensions #242, column 13, rows 37-38) has a first lateral surface (Fig.9, left side of left element #242), the substrate has a second lateral surface (Fig.9, left side of element #121), and the first lateral surface and the second lateral surface are flush with each other (Fig.9, the two surfaces are flushed with each other). The combination of Bezama and Nakamura does not teach wherein the heat dissipation component has a first lateral surface, the substrate has a second lateral surface, and the first lateral surface protrudes with respect to the second lateral surface. Zohni teaches wherein the heat dissipation component (Fig.1, formed by element #150, column 3, rows 47-50 and elements #154, column 4, rows 17-21) has a first lateral surface (Fig.1, surface of the leftmost side of element #154), the substrate (Fig.1, element #122, column 3, rows 22-23) has a second lateral surface (Fig.1, side mounting surface, element #160), and the first lateral surface protrudes with respect to the second lateral surface (Fig.1, column 4, rows 4-6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Zohni and disclose wherein the heat dissipation component has a first lateral surface, the substrate has a second lateral surface, and the first lateral surface protrudes with respect to the second lateral surface. As disclosed by Zohni, this provides mechanical support and helps prevent the semiconductor device from bowing and twisting (column 4, rows 3-7). Regarding claim 11, the combination of Bezama and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection, and the combination of Bezama, Nakamura and Zohni teaches semiconductor of claim 10 as set forth in the obviousness rejection. Bezama further teaches the semiconductor device as claimed in claim 10, wherein the heat dissipation component comprises a connection portion connected with the main body, the inlet and the outlet (Fig.9, left element #242 connected with element #223, and Fig.12B, element #404, that may be implemented as element #223 of Fig.9, column 15, rows 11-12, has a cavity and flow channels #402, column 15, row 21, an inlet and an outlet) the connection portion has the first lateral surface (Fig.9, left side of left element #242), the main body has a third lateral surface (Fig.9, element #223 has a left lateral surface). In a different embodiment, Bezama teaches the third lateral surface (Fig.2A, surface of the leftmost side of main body element #40, column 2, row 58) protrudes with respect to the first lateral surface (Fig.2A, surface of the leftmost side of the connection portion formed by element #64 and #62, column 4, rows 60). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings Bezama and disclose the third lateral surface protrudes with respect to the first lateral surface. This results in an increase of the overall surface area of the main body of the heat dissipation component which improves its heat dissipation ability. Regarding claim 18, the combination of Bezama and Nakamura teaches the method of claim 17 as set forth in the obviousness rejection. The combination of Bezama and Nakamura does not teach the manufacturing method as claimed in claim 17, further comprising: disposing an interposer on the substrate; and disposing the semiconductor component on the substrate through the interposer. Zohni teaches the manufacturing method, further comprising: disposing an interposer on the substrate (Fig.2, element #112, is disposed on the substrate, element #122, column 2, row 63); and disposing the semiconductor component on the substrate through the interposer (Fig.2, elements #114, are disposed on the interposer, column 3, rows 20-23). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Zohni and disclose disposing an interposer on the substrate and disposing the semiconductor component on the substrate through the interposer. As Zohni discloses, the interposer can include circuitry for connecting the semiconductor components to the substrate or transistors and other circuit elements (column 3, rows 6-10) which enable communication between the semiconductor components and the substrate or a PCB (column 3, rows 31-35). Claims 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bezama, in view of Nakamura and in view of Cheng-Chieh Hsieh et al., (United States Patent Number, US 9,034,695 B2) hereinafter referenced as Hsieh. Regarding claim 13, the combination of Bezama and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. The combination of Bezama and Nakamura does not teach the semiconductor device as claimed in claim 1, further comprising: a plurality of the semiconductor components each having a top surface, wherein the top surfaces of the semiconductor components are flush with each other; and a thermal interface material disposed on the top surfaces of the semiconductor components. Hsieh teaches the semiconductor device further comprising: a plurality of the semiconductor components (Fig.5A, elements #44, column 4, row 18-19) each having a top surface (Fig.5A, elements #44 have a top surface), wherein the top surfaces of the semiconductor components are flush with each other (Fig.5A, top surfaces of the right and left elements #44 are flush with each other, column 3, rows 10-16); and a thermal interface material disposed on the top surfaces of the semiconductor components (Fig.5A, element #55, column 3, rows 27-30 is disposed on the top surfaces of the semiconductor components). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hsieh and disclose a plurality of the semiconductor components each having a top surface, wherein the top surfaces of the semiconductor components are flush with each other; and a thermal interface material disposed on the top surfaces of the semiconductor components. Having multiple semiconductor components in a semiconductor device allows for increased functionality of the device, and reduced packaging costs as compared to having a separate package for each individual component. Furthermore, having the top surfaces of the semiconductor components flush with each other provides a planar surface on which flat heat dissipation parts can be easily attached, with each semiconductor component being at the same distance from the heat dissipation part to ensure uniform heat dissipation. The TIM layer disposed on the top surfaces of the semiconductor components helps dissipate heat away from the semiconductor components. Regarding claim 20, the combination of Bezama and Nakamura teaches the method of claim 17 as set forth in the obviousness rejection. The combination of Bezama and Nakamura does not teach the manufacturing method as claimed in claim 17, further comprising: disposing a plurality of the semiconductor components on the substrate, wherein each semiconductor component has a top surface, and the top surfaces of the semiconductor components are flush with each other; and disposing a thermal interface material on the top surfaces of the semiconductor components. Hsieh teaches the manufacturing method, further comprising: disposing a plurality of the semiconductor components on the substrate (Fig.5A, elements #44, column 4, rows 18-19, are disposed on the substrate, element #22, column 4, row 12), wherein each semiconductor component has a top surface (Fig.5A, elements #44 have a top surface), and the top surfaces of the semiconductor components are flush with each other (Fig.5A, top surfaces of the right and left elements #44 are flush with each other, column 3, rows 10-16); and disposing a thermal interface material on the top surfaces of the semiconductor components (Fig.5A, element #55, column 3, rows 27-30 is disposed on the top surfaces of semiconductor components). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hsieh and disclose a plurality of the semiconductor components each having a top surface, wherein the top surfaces of the semiconductor components are flush with each other; and a thermal interface material disposed on the top surfaces of the semiconductor components. Having multiple semiconductor components in a semiconductor device allows for increased functionality of the device, and reduces packaging costs as compared to having a separate package for each individual component. Furthermore, having the top surfaces of the semiconductor components flush with each other provides a planar surface on which flat heat dissipation parts can be easily attached, with each semiconductor component being at the same distance from the heat dissipation part to ensure uniform heat dissipation. The TIM layer disposed on the top surfaces of the semiconductor components helps dissipate heat away from the semiconductor components. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Bezama in view of Nakamura, and in view of Boxi Liu et al., (United States Patent Application Publication Number, US 2018/0374776 A1), hereinafter referenced as Liu. Regarding claim 14, the combination of Bezama and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Bezama further teaches the semiconductor device as claimed in claim 1, wherein the heat dissipation component and the semiconductor component are connected by only a thermal interface material (Fig.9, TIM, element #127, column 12, rows 13-15 is disposed between the semiconductor component, element #122, and the heat dissipation component, element #223). Bezama further teaches where the thermal interface material is an adhesive or a gel (column 11, rows 52-54). The combination of Bezama and Nakamura does not teach that the thermal interface material is an insulation material. Liu teaches a heat dissipating component (Fig.4, element #204, paragraph [0029], rows 4-5) and a semiconductor component (Fig.4, element #210, paragraph [0029], row 7) connected by only a thermal interface material (Fig.4, element #212, paragraph [0029], rows 10-11) which is an insulating material (the dielectric adhesive are electrically insulating materials, paragraph [0036], rows 10-11). Thus, both references, Bezama and Liu, teach a thermal interface material connecting the semiconductor and the heat dissipation components. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the gel disclosed by Bezama could have been replaced for the electrically insulating adhesive disclosed by Liu because both serve the same purpose of providing a thermal interface material between the semiconductor and the heat dissipation components. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing a thermal connection between the semiconductor and the heat dissipation components. Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zohni, in view of Nakamura. Regarding claim 15, Zohni teaches a semiconductor device, comprising: a substrate (Fig.2, element #122, column 5, row 39), an interposer disposed on the substrate (Fig.2, interposer element #112, is disposed on the substrate, element #122, column 2, row 63), a plurality of semiconductor components disposed on the substrate (Fig.2, elements #114, column 5, rows 38, are disposed on element #122) and a heat dissipation component (Fig.2, Zohni does not teach the heat dissipation component having a cavity, an inlet and an outlet, wherein the inlet and the outlet communicate with the cavity; wherein the heat dissipation component comprises a main body comprising the cavity, a first extension portion and a first flank, the inlet is exposed from an outer surface of the first flank, the first extension portion is connected with, protrudes relative to, and is perpendicular to an upper surface of the main body and extends in a first direction, and the first flank is connected with the first extension portion and extends in a second direction perpendicular to the first direction. Nakamura teaches the heat dissipation component having a cavity (Fig.10A, element #114 has a cavity) an inlet and an outlet, wherein the inlet and the outlet communicate with the cavity (Fig,10A, inlet, element #200 and outlet, element #201 communicate with the cavity inside element #114); wherein the heat dissipation component comprises a main body comprising the cavity (Fig.10A, element #114 comprises a cavity), a first extension portion and a first flank (Fig.10A, extension, element #902, and first flank, element #901), the inlet is exposed from an outer surface of the first flank (Fig.10A, element #200 is exposed from an outer surface of element #901), the first extension portion is connected with, protrudes relative to, and is perpendicular to an upper surface of the main body and extends in a first direction (Fig.10B, rotated vertically with 180 degrees, extension, element #902, is connected to and protrudes relative to the top surface of element #114, the inside vertical wall of element #902 is perpendicular to the upper surface of element #114, and element #902 extends in the horizontal direction) and the first flank is connected with the first extension portion and extends in a second direction perpendicular to the first direction (Fig.10B, first flank, element #901 is connected to extension, element #902, and extends in the vertical direction). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Nakamura and disclose a heat dissipation part having a cavity, an inlet and an outlet, wherein the inlet and the outlet communicate with the cavity; wherein the heat dissipation component comprises a main body comprising the cavity, a first extension portion and a first flank, the inlet is exposed from an outer surface of the first flank, the first extension portion is connected with, protrudes relative to, and is perpendicular to an upper surface of the main body and extends in a first direction, and the first flank is connected with the first extension portion and extends in a second direction perpendicular to the first direction. As disclosed by Nakamura, the extensions and the flanks allow for uniform cooling to be achieved without the need for coolant accumulating parts, which improves the thermal characteristics of the heat dissipation structure, while enabling no coolant pressure loss (paragraph [0010], rows 1-5), while the cavity allows the flow of a coolant through the heat dissipating component, which increases heat dissipation, as compared to passive cooling Furthermore, both references Zohni and Nakamura teach a heat dissipation component. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the heat dissipation component disclosed by Zohni could have been replaced for heat sink disclosed by Nakamura because both serve the same purpose of dissipating heat away from the semiconductor components. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of dissipating heat away from the semiconductor components. Regarding claim 16, the combination of Zohni and Nakamura teaches the semiconductor device of claim 15 as set forth in the obviousness rejection. Zohni further teaches the semiconductor device as claimed in claim 15, wherein each semiconductor component has a top surface and the top surfaces of the semiconductor components are flush with each other (Fig.2, elements #144 have a top surface and the top surfaces are flush with each other). Response to Arguments Applicant’s arguments filed on 12/16/2025 have been fully considered but they are not persuasive. Applicant’s arguments with respect to claims 1, 15, and 17 have been considered but are moot because the new ground of rejection (a different embodiment of Nakamura, as shown in Figures 10A and 10B, is being used as new ground of rejection) does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN A TIVARUS whose telephone number is (703)756-4688. The examiner can normally be reached Monday- Friday 8:00 AM -5:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jan 20, 2023
Application Filed
May 14, 2025
Non-Final Rejection — §103
Aug 14, 2025
Response Filed
Oct 06, 2025
Final Rejection — §103
Dec 16, 2025
Request for Continued Examination
Jan 06, 2026
Response after Non-Final Action
Jan 16, 2026
Non-Final Rejection — §103
Apr 01, 2026
Applicant Interview (Telephonic)
Apr 01, 2026
Examiner Interview Summary

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
94%
With Interview (+18.1%)
3y 3m
Median Time to Grant
High
PTA Risk
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