Prosecution Insights
Last updated: August 17, 2026
Application No. 18/099,697

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Final Rejection §103
Filed
Jan 20, 2023
Priority
Sep 30, 2022 — provisional 63/411,833
Examiner
TIVARUS, CRISTIAN ALEXANDRU
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
4 (Final)
78%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
35 granted / 45 resolved
+9.8% vs TC avg
Strong +22% interview lift
Without
With
+21.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
39 currently pending
Career history
89
Total Applications
across all art units

Statute-Specific Performance

§103
58.0%
+18.0% vs TC avg
§102
25.1%
-14.9% vs TC avg
§112
16.9%
-23.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 45 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The Amendment filed on 04/27/2026 has been entered. Claims 1-20 remain pending in the application. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 6, 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Betsegaw Gebrehiwot et al., (United States Patent Application Publication Number, US 2020/0409398 A1), hereinafter referenced as Gebrehiwot, in view of Nakamura et al., (United States Patent Publication Application Number, US 2006/0243504 A1) hereinafter referenced as Nakamura. Regarding claim 1, Gebrehiwot teaches a semiconductor device, comprising: a substrate (Fig.6, element #658); a semiconductor component disposed on the substrate (Fig.6, element 602); and a heat dissipation component disposed on the substrate (Fig.6, component formed by elements #654, #608, #610, #646 and #656) and having a cavity (Fig.6,elements #608 and #610 form a cavity), an inlet and an outlet wherein the inlet and the outlet communicate with the cavity (Fig.6, elements #626 and #636), wherein the heat dissipation component comprises a main body comprising the cavity (Fig.6, main body formed by elements #608 and #610). Gebrehiwot teaches a first extension portion (Fig.1B, element #141). Gebrehiwot does not teach a first flank, the inlet is exposed from an outer surface of the first flank, the first extension portion is connected with, protrudes relative to, is perpendicular to an upper surface of the main body and upwardly extends in a vertical direction, and the first flank is connected with the first extension portion, laterally extends in a horizontal direction and protrudes relative to the lateral surface of the first extension portion in the horizontal direction. Nakamura teaches an inlet and an outlet, wherein the inlet and the outlet communicate with the cavity (Fig.3, element #200 and #201); wherein the heat dissipation component comprises a main body comprising the cavity (Fig.3, element #114), a first extension portion and a first flank (Fig.3, extension, element #303, and first flank, element #301), the inlet is exposed from an outer surface of the first flank (Fig.3, element #200 is exposed from an outer surface of element #301), the first extension portion is connected with, protrudes relative to, is perpendicular to an upper surface of the main body and upwardly extends in a vertical direction (Fig.3 rotated vertically with 180 degrees, element #303 extends upwardly is connected and protrudes relative to an upper horizontal surface of the main body), and the first flank is connected with the first extension portion, laterally extends in a horizontal direction and protrudes relative to the lateral surface of the first extension portion in the horizontal direction (Fig.3, elements #301 is connected to element #303, extends in the horizontal direction and protrudes in the horizontal direction relative to element #306). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Nakamura and disclose wherein the heat dissipation component comprises a main body comprising the cavity, a first extension portion and a first flank, the inlet is exposed from an outer surface of the first flank, the first extension portion is connected with, protrudes relative to, is perpendicular to an upper surface of the main body and upwardly extends in a vertical direction, and the first flank is connected with the first extension portion, laterally extends in a horizontal direction and protrudes relative to the lateral surface of the first extension portion in the horizontal direction. As disclosed by Nakamura, the extensions and the flanks allow for uniform cooling to be achieved without the need for coolant accumulating parts, which improves the thermal characteristics of the heat dissipation structure while enabling no coolant pressure loss (paragraph [0010], rows 1-5). Regarding claim 2, the combination of Gebrehiwot and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Gebrehiwot further teaches the semiconductor device comprising a thermal interface material (TIM) disposed between the semiconductor component and the heat dissipation component (Fig.6, element #606). Regarding claim 3, the combination of Gebrehiwot and Nakamura teaches the semiconductor device of claims 1 and 2 as set forth in the obviousness rejection. Gebrehiwot further teaches the semiconductor device as claimed in claim 2, wherein the thermal interface material connects the semiconductor component with the heat dissipation component (Fig.6, element #606 connects the semiconductor device, element #602, with element #608). Regarding claim 6, the combination of Gebrehiwot and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Gebrehiwot further teaches the semiconductor device as claimed in claim 1, wherein the heat dissipation component has a terminal surface (Fig.6, bottom surface of element #654) and a recess (Fig.6, bottom surface of element #608 is recessed), the recess is recessed with respect to the terminal surface for receiving the semiconductor component (Fig.6, element #602 is inside the recess). Regarding claim 9, the combination of Gebrehiwot and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Gebrehiwot further teaches wherein the heat dissipation component has a first lateral surface, the substrate has a second lateral surface, and the first lateral surface is recessed with respect to the second lateral surface (Fig.6, the left lateral surface of element #654 is recessed with respect to the left lateral surface of element #658). Regarding claim 17, Gebrehiwot teaches a manufacturing method of a semiconductor device, comprising: disposing a semiconductor component on a substrate (Fig.6, element #602 is disposed on the substrate, element #658); and disposing a heat dissipation component on the substrate (Fig.6, component formed by elements #654, #608, #610, #646 and #656 is disposed on the substrate, element #658), wherein the heat dissipation component has a cavity, an inlet and an outlet, and the inlet and the outlet communicate with the cavity (Fig.6, elements #626 and #636 communicate with the cavity formed between elements #608 and #610); wherein the heat dissipation component comprises a main body comprising the cavity (Fig.6, main body formed by elements #608 and #610). Gebrehiwot teaches a first extension portion (Fig.1B, element #141). Gebrehiwot does not teach a first flank, the inlet is exposed from an outer surface of the first flank, the first extension portion is connected with, protrudes relative to, is perpendicular to an upper surface of the main body and upwardly extends in a vertical direction, and the first flank is connected with the first extension portion, laterally extends in a horizontal direction and protrudes relative to a lateral surface of the first extension portion in the horizontal direction. Nakamura teaches an inlet and an outlet, wherein the inlet and the outlet communicate with the cavity (Fig.3, element #200 and #201); wherein the heat dissipation component comprises a main body comprising the cavity (Fig.3, element #114), a first extension portion and a first flank (Fig.3, extension, element #303, and first flank, element #301), the inlet is exposed from an outer surface of the first flank (Fig.3, element #200 is exposed from an outer surface of element #301), the first extension portion is connected with, protrudes relative to, is perpendicular to an upper surface of the main body and upwardly extends in a vertical direction (Fig.3 rotated vertically with 180 degrees, element #303 extends upwardly is connected and protrudes relative to an upper horizontal surface of the main body), and the first flank is connected with the first extension portion, laterally extends in a horizontal direction and protrudes relative to the lateral surface of the first extension portion in the horizontal direction (Fig.3, elements #301 is connected to element #303, extends in the horizontal direction and protrudes in the horizontal direction relative to element #306). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Nakamura and disclose wherein the heat dissipation component comprises a main body comprising the cavity, a first extension portion and a first flank, the inlet is exposed from an outer surface of the first flank, the first extension portion is connected with, protrudes relative to, is perpendicular to an upper surface of the main body and upwardly extends in a vertical direction, and the first flank is connected with the first extension portion, laterally extends in a horizontal direction and protrudes relative to the lateral surface of the first extension portion in the horizontal direction. As disclosed by Nakamura, the extensions and the flanks allow for uniform cooling to be achieved without the need for coolant accumulating parts, which improves the thermal characteristics of the heat dissipation structure while enabling no coolant pressure loss (paragraph [0010], rows 1-5). Claims 4, 5, 8, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gebrehiwot in view of Nakamura and in view of Raschid Jose Bezama et al., (United States Patent Number, US 8,115,303 B2), hereinafter referenced as Bezama Regarding claim 4, the combination of Gebrehiwot and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Gebrehiwot further teaches the semiconductor device as claimed in claim 1, the heat dissipation component is connected to the substrate (Fig.6, elements #654 and #656 are connected to element #658). The combination of Gebrehiwot and Nakamura does not teach an adhesive layer disposed between the substrate and the heat dissipation component (Fig.9, element #233, column 13, rows 42-43, is disposed between the substrate, element #121 and the heat dissipation component, element #223). Bezama teaches an adhesive layer disposed between the substrate and the heat dissipation component (Fig.9, element #233, column 13, rows 42-43, is disposed between the substrate, element #121 and the heat dissipation component, element #223). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Bezama and disclose an adhesive layer disposed between the substrate and the heat dissipation component. Using adhesives to attach the heat dissipation component to the substrate is a cheap and reliable method, providing mechanical stability to the package. Regarding claim 5, the combination of Gebrehiwot and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection, and the combination of Gebrehiwot, Nakamura and Bezama teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Bezama further teaches the semiconductor device as claimed in claim 4, wherein the adhesive layer connects the substrate and the heat dissipation component (Fig.9, the adhesive layer element #233, column 13, rows 42-43, connects the substrate, element #121 and the heat dissipation component, element #223). Regarding claim 8, the combination of Gebrehiwot and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. The combination of Gebrehiwot and Nakamura does not teach the semiconductor device as claimed in claim 1, wherein the heat dissipation component has a first lateral surface, the substrate has a second lateral surface, and the first lateral surface and the second lateral surface are flush with each other. Bezama further teaches the semiconductor device as claimed in claim 1, wherein the heat dissipation component (Fig.9, component formed by the metallic liquid cooling module, element #223 and extensions #242, column 13, rows 36-38) has a first lateral surface (Fig.9, surface of the left side of element #242), the substrate has a second lateral surface (Fig.9, surface of the left side of element #121), and the first lateral surface and the second lateral surface are flush with each other (Fig.9, the two surfaces are flushed with each other). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Bezama and disclose the substrate has a second lateral surface, and the first lateral surface and the second lateral surface are flush with each other. This results is a package without the substrate or the heat dissipation component having portions extending laterally beyond one another, which would increase the possibility of these portions being subject to chipping or damage. Regarding claim 12, the combination of Gebrehiwot and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. The combination of Gebrehiwot and Nakamura does not teach the semiconductor device as claimed in claim 1, wherein the heat dissipation component is shaped from a single, continuous piece of material. Bezama teaches the semiconductor device as claimed in claim 1, wherein the heat dissipation component is shaped from a single, continuous piece of material (Fig.9, column 13, rows 44-47). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Bezama and disclose wherein the heat dissipation component is shaped from a single, continuous piece of material. Manufacturing the heat dissipation component from a single, continuous piece of material nay reduce the number of manufacturing steeps and thus reduce costs. Regarding claim 19, the combination of Gebrehiwot and Nakamura teaches the method of claim 17 as set forth in the obviousness rejection. The combination of Gebrehiwot and Nakamura does not teach the manufacturing method as claimed in claim 17, further comprising: disposing the heat dissipation component on the substrate through an adhesive layer. Bezama further teaches the manufacturing method as claimed in claim 17, further comprising: disposing the heat dissipation component on the substrate (Fig.9, component formed by the metallic liquid cooling module, element #223 and extensions #242, column 13, rows 37-38, is disposed on the substrate, element #121) through an adhesive layer (Fig.9, element #233, column 13, rows 42-43). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Bezama and disclose disposing the heat dissipation component on the substrate through an adhesive layer. Using adhesives to attach the heat dissipation component to the substrate is a cheap and reliable method, providing mechanical stability to the package. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Gebrehiwot, in view of Nakamura and in view of Peng Li et al., (United States Patent Application Publication Number, US 2020/0006192 A1) hereinafter referenced as Li. Regarding claim 7, the combination of Gebrehiwot and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Gebrehiwot does not explicitly teach the semiconductor device as claimed in claim 1, wherein there is an air layer among the substrate. Li teaches the semiconductor device wherein there is an air layer among the substrate, the heat dissipation component and the semiconductor component (Fig.1, element #170, can be air, paragraph [0023], rows 14-15, is among the substrate, element #102, semiconductor device, element #114 and heat dissipation component element #140, paragraph [0018], rows 4-7). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Li and disclose an air layer among the substrate, the heat dissipation component and the semiconductor component. Because air has low thermal conductivity, the heat generated by the semiconductor component will be dissipated only through the TIM layer and from the TIM layer to the heat dissipation component, preventing it from spreading to other heat sensitive areas of the device that are in contact with the air layer. Claims 10 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Gebrehiwot in view of Nakamura, and in view of Nael Zohni et al., (United States Patent Number, US 10,840,192 B2) hereinafter referenced as Zohni. Regarding claim 10, the combination of Gebrehiwot and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Gebrehiwot teaches the semiconductor device as claimed in claim 1, wherein the heat dissipation component has a first lateral surface, the substrate has a second lateral surface and the first lateral surface is recessed with respect to the second lateral surface (Fig.6, the left lateral surface of element #654 is recessed with respect to the left lateral surface of element #658).The combination of Gebrehiwot and Nakamura does not teach wherein the heat dissipation component has a first lateral surface, the substrate has a second lateral surface, and the first lateral surface protrudes with respect to the second lateral surface. Zohni teaches wherein the heat dissipation component (Fig.1, formed by element #150, column 3, rows 47-50 and elements #154, column 4, rows 17-21) has a first lateral surface (Fig.1, surface of the leftmost side of element #154), the substrate (Fig.1, element #122, column 3, rows 22-23) has a second lateral surface (Fig.1, side mounting surface, element #160), and the first lateral surface protrudes with respect to the second lateral surface (Fig.1, column 4, rows 4-6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Zohni and disclose wherein the heat dissipation component has a first lateral surface, the substrate has a second lateral surface, and the first lateral surface protrudes with respect to the second lateral surface. As disclosed by Zohni, this provides mechanical support and helps prevent the semiconductor device from bowing and twisting (column 4, rows 3-7). Regarding claim 18, the combination of Gebrehiwot and Nakamura teaches the method of claim 17 as set forth in the obviousness rejection. The combination of Gebrehiwot and Nakamura does not teach the manufacturing method as claimed in claim 17, further comprising: disposing an interposer on the substrate; and disposing the semiconductor component on the substrate through the interposer. Zohni teaches the manufacturing method, further comprising: disposing an interposer on the substrate (Fig.2, element #112, is disposed on the substrate, element #122, column 2, row 63); and disposing the semiconductor component on the substrate through the interposer (Fig.2, elements #114, are disposed on the interposer, column 3, rows 20-23). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Zohni and disclose disposing an interposer on the substrate and disposing the semiconductor component on the substrate through the interposer. As Zohni discloses, the interposer can include circuitry for connecting the semiconductor components to the substrate or transistors and other circuit elements (column 3, rows 6-10) which enable communication between the semiconductor components and the substrate or a PCB (column 3, rows 31-35). Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Gebrehiwot in view of Nakamura, Zohni and in view of Bezama. Regarding claim 11, the combination of Gebrehiwot and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection, and the combination of Gebrehiwot, Nakamura and Zohni teaches semiconductor of claim 10 as set forth in the obviousness rejection. Gebrehiwot further teaches the semiconductor device as claimed in claim 10, wherein the heat dissipation component comprises a connection portion connected with the main body, the inlet and the outlet, the connection portion has the first lateral surface (Fig.6, element #654 is connected to the inlet, outlet and the main body). The combination of Gebrehiwot, Nakamura and Zohni does not teach the connection portion has the first lateral surface, the main body has a third lateral surface, and the third lateral surface protrudes with respect to the first lateral surface. Bezama teaches the third lateral surface (Fig.2A, surface of the leftmost side of main body element #40, column 2, row 58) protrudes with respect to the first lateral surface (Fig.2A, surface of the leftmost side of the connection portion formed by element #64 and #62, column 4, rows 60). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings Bezama and disclose the third lateral surface protrudes with respect to the first lateral surface. This results in an increase of the overall surface area of the main body of the heat dissipation component which improves its heat dissipation ability. Claims 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gebrehiwot, in view of Nakamura and in view of Cheng-Chieh Hsieh et al., (United States Patent Number, US 9,034,695 B2) hereinafter referenced as Hsieh. Regarding claim 13, the combination of Gebrehiwot and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. The combination of Gebrehiwot and Nakamura does not teach the semiconductor device as claimed in claim 1, further comprising: a plurality of the semiconductor components each having a top surface, wherein the top surfaces of the semiconductor components are flush with each other; and a thermal interface material disposed on the top surfaces of the semiconductor components. Hsieh teaches the semiconductor device further comprising: a plurality of the semiconductor components (Fig.5A, elements #44, column 4, row 18-19) each having a top surface (Fig.5A, elements #44 have a top surface), wherein the top surfaces of the semiconductor components are flush with each other (Fig.5A, top surfaces of the right and left elements #44 are flush with each other, column 3, rows 10-16); and a thermal interface material disposed on the top surfaces of the semiconductor components (Fig.5A, element #55, column 3, rows 27-30 is disposed on the top surfaces of the semiconductor components). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hsieh and disclose a plurality of the semiconductor components each having a top surface, wherein the top surfaces of the semiconductor components are flush with each other; and a thermal interface material disposed on the top surfaces of the semiconductor components. Having multiple semiconductor components in a semiconductor package allows for increased functionality, and reduced packaging costs as compared to having a separate package for each individual component. Furthermore, having the top surfaces of the semiconductor components flush with each other provides a planar surface on which flat heat dissipation parts can be easily attached, with each semiconductor component being at the same distance from the heat dissipation part to ensure uniform heat dissipation. The TIM layer disposed on the top surfaces of the semiconductor components helps dissipate heat away from the semiconductor components. Regarding claim 20, the combination of Gebrehiwot and Nakamura teaches the method of claim 17 as set forth in the obviousness rejection. The combination of Gebrehiwot and Nakamura does not teach the manufacturing method as claimed in claim 17, further comprising: disposing a plurality of the semiconductor components on the substrate, wherein each semiconductor component has a top surface, and the top surfaces of the semiconductor components are flush with each other; and disposing a thermal interface material on the top surfaces of the semiconductor components. Hsieh teaches the manufacturing method, further comprising: disposing a plurality of the semiconductor components on the substrate (Fig.5A, elements #44, column 4, rows 18-19, are disposed on the substrate, element #22, column 4, row 12), wherein each semiconductor component has a top surface (Fig.5A, elements #44 have a top surface), and the top surfaces of the semiconductor components are flush with each other (Fig.5A, top surfaces of the right and left elements #44 are flush with each other, column 3, rows 10-16); and disposing a thermal interface material on the top surfaces of the semiconductor components (Fig.5A, element #55, column 3, rows 27-30 is disposed on the top surfaces of semiconductor components). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hsieh and disclose a plurality of the semiconductor components each having a top surface, wherein the top surfaces of the semiconductor components are flush with each other; and a thermal interface material disposed on the top surfaces of the semiconductor components. Having multiple semiconductor components in a semiconductor device allows for increased functionality of the device, and reduces packaging costs as compared to having a separate package for each individual component. Furthermore, having the top surfaces of the semiconductor components flush with each other provides a planar surface on which flat heat dissipation parts can be easily attached, with each semiconductor component being at the same distance from the heat dissipation part to ensure uniform heat dissipation. The TIM layer disposed on the top surfaces of the semiconductor components helps dissipate heat away from the semiconductor components. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Gebrehiwot in view of Nakamura, and in view of Boxi Liu et al., (United States Patent Application Publication Number, US 2018/0374776 A1), hereinafter referenced as Liu. Regarding claim 14, the combination of Gebrehiwot and Nakamura teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Gebrehiwot further teaches the semiconductor device as claimed in claim 1, wherein the heat dissipation component and the semiconductor component are connected by only a thermal interface material (Fig.6, TIM, element #606). The combination of Gebrehiwot and Nakamura does not teach that the thermal interface material is an insulation material. Liu teaches a heat dissipating component (Fig.4, element #204, paragraph [0029], rows 4-5) and a semiconductor component (Fig.4, element #210, paragraph [0029], row 7) connected by only a thermal interface material (Fig.4, element #212, paragraph [0029], rows 10-11) which is an insulating material (the dielectric adhesive are electrically insulating materials, paragraph [0036], rows 10-11). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Liu and disclose that the thermal interface material is an insulation material. An insulating materials overs electrical isolation preventing shorts between the semiconductor components and the heat dissipation component. Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zohni, in view of Nakamura. Regarding claim 15, Zohni teaches a semiconductor device, comprising: a substrate (Fig.2, element #122, column 5, row 39), an interposer disposed on the substrate (Fig.2, interposer element #112, is disposed on the substrate, element #122, column 2, row 63), a plurality of semiconductor components disposed on the substrate (Fig.2, elements #114, column 5, rows 38, are disposed on element #122) and a heat dissipation component (Fig.2, Zohni does not teach the heat dissipation component having a cavity, an inlet and an outlet, wherein the inlet and the outlet communicate with the cavity; wherein the heat dissipation component comprises a main body comprising the cavity, a first extension portion and a first flank, the inlet is exposed from an outer surface of the first flank, the first extension portion is connected with, protrudes relative to, is perpendicular to an upper surface of the main body and upwardly extends in a vertical direction, and the first flank is connected with the first extension portion laterally extends in a horizontal direction and protrudes relative to a lateral surface of the first extension portion in the horizontal direction. Nakamura teaches a heat dissipation component having a cavity entire structure showed in Fig.3) an inlet and an outlet, wherein the inlet and the outlet communicate with the cavity (Fig.3, element #200 and #201); wherein the heat dissipation component comprises a main body comprising the cavity (Fig.3, element #114), a first extension portion and a first flank (Fig.3, extension, element #303, and first flank, element #301), the inlet is exposed from an outer surface of the first flank (Fig.3, element #200 is exposed from an outer surface of element #301), the first extension portion is connected with, protrudes relative to, is perpendicular to an upper surface of the main body and upwardly extends in a vertical direction (Fig.3 rotated vertically with 180 degrees, element #303 extends upwardly is connected and protrudes relative to an upper horizontal surface of the main body), and the first flank is connected with the first extension portion laterally extends in a horizontal direction and protrudes relative to a lateral surface of the first extension portion in the horizontal direction (Fig.3, elements #301 is connected to element #303, extends in the horizontal direction and protrudes in the horizontal direction relative to element #306). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Nakamura and disclose wherein the heat dissipation component comprises a main body comprising the cavity, a first extension portion and a first flank, the inlet is exposed from an outer surface of the first flank, the first extension portion is connected with, protrudes relative to, is perpendicular to an upper surface of the main body and upwardly extends in a vertical direction, and the first flank is connected with the first extension portion, laterally extends in a horizontal direction and protrudes relative to the lateral surface of the first extension portion in the horizontal direction. As disclosed by Nakamura, the extensions and the flanks allow for uniform cooling to be achieved without the need for coolant accumulating parts, which improves the thermal characteristics of the heat dissipation structure while enabling no coolant pressure loss (paragraph [0010], rows 1-5). Regarding claim 16, the combination of Zohni and Nakamura teaches the semiconductor device of claim 15 as set forth in the obviousness rejection. Zohni further teaches the semiconductor device as claimed in claim 15, wherein each semiconductor component has a top surface and the top surfaces of the semiconductor components are flush with each other (Fig.2, elements #144 have a top surface and the top surfaces are flush with each other). Response to Arguments Applicant’s arguments filed on 04/27/2026 have been fully considered but they are not persuasive. Applicant’s arguments with respect to claims have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN A TIVARUS whose telephone number is (703)756-4688. The examiner can normally be reached Monday- Friday 8:00 AM-5:00 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Show 3 earlier events
Oct 08, 2025
Final Rejection mailed — §103
Dec 16, 2025
Request for Continued Examination
Jan 06, 2026
Response after Non-Final Action
Jan 27, 2026
Non-Final Rejection mailed — §103
Apr 01, 2026
Applicant Interview (Telephonic)
Apr 01, 2026
Examiner Interview Summary
Apr 27, 2026
Response Filed
Jul 02, 2026
Final Rejection mailed — §103 (current)

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ELECTRONIC DEVICE
3y 11m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

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Prosecution Projections

5-6
Expected OA Rounds
78%
Grant Probability
99%
With Interview (+21.9%)
3y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 45 resolved cases by this examiner. Grant probability derived from career allowance rate.

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