Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-9 and 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHANG (Pub. No.: US 2017/0317178) in view of LEE (Pub. No.: US 2012/0261748).
Re claim 6, CHANG teaches a method for manufacturing an interconnecting metal layer for a semiconductor device, the semiconductor device comprising a first gate electrode, a second gate electrode, a dielectric layer and an insulating layer, the dielectric layer being disposed on a side of the first gate electrode and the second gate electrode, the insulating layer being disposed on another side of the first gate electrode and the second gate electrode gate layer and the method for manufacturing the interconnecting metal layer comprising:
forming a trench (151, Fig. 4) between the first (121, ¶ [0012]) and second gate electrodes (123), the trench passing through the dielectric layer (141/143), and an epitaxial layer (130, [0023]) being deposited in the trench and formed at a bottom of the trench;
forming a sidewall liner (150/160, [0033]) on a sidewall of the trench, and one end of the sidewall liner being connected to the epitaxial layer (130);
CHANG fails to teach performing hydrogen and oxygen plasma treatments on the sidewall liner to convert the sidewall liner from a high dielectric constant material to a low dielectric constant material.
LEE teaches performing hydrogen and oxygen plasma treatments on the sidewall liner to convert the sidewall liner (36, FIG. 3C, [0069]) from a high dielectric constant material to a low dielectric constant material (36A/36B).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of removing the impurities and defects within the gate insulation layer as taught by LEE, [0068].
Re claim 7, in the combination, CHANG teaches the method according to claim 6, further comprising forming a metal layer (170/171, Fig. 5, [0035]) in the trench (151), the metal layer is connected to the epitaxial layer (130), and the sidewall liner (150/160) is separated from the metal layer (170/171) and the first and second gate electrodes (121/123).
Re claim 8, in the combination, LEE teaches the method according to claim 7, wherein before forming the metal layer in the trench, the method further comprises forming a metal silicide (tungsten silicide layer of bottom layer of 37, [0074]) and a seed layer (middle layer of 37) at the bottom of the trench, the metal silicide is located between the seed layer and the epitaxial layer (35).
Re claim 9, in the combination, LEE teaches the method according to claim 6, wherein converting the sidewall liner from the high dielectric constant material to the low dielectric constant material comprises introducing an oxygen ion plasma to react with silicon nitride (SiNx) (silicon nitride material of layer 106, [0045]) to generate silicon dioxide (SiO2) (36A, [0071]).
Re claim 21, CHANG teaches a method for manufacturing a semiconductor device, comprising:
forming a dielectric layer (middle 141/143), a first gate electrode, a second gate electrode (121/123), gate layer and an insulating layer (far right and left of (141/143)) stacked to each other, the dielectric layer being disposed on a side of the first and second gate electrodes, and the insulating layer being disposed on another side of the first and second gate electrodes;
forming a trench (151, Fig. 4) between the first and second gate electrodes, the trench passing through the dielectric layer (middle 141/143), and an epitaxial layer (130) being deposited in the trench and formed at a bottom of the trench;
forming a sidewall liner (150/160) on a sidewall of the trench, and one end of the sidewall liner being connected to the epitaxial layer (130), wherein the sidewall liner comprises a surface layer and a bottom layer, the bottom layer is silicon nitride 150, [0037]).
CHANG fails to teach the surface layer is generated by a reaction of the silicon nitride with oxygen ions to form silicon dioxide; forming a metal silicide and a seed layer at the bottom of the trench, the metal silicide is located between the seed layer and the second epitaxial layer; and forming a conductive plug in the trench, wherein the conductive plug is surrounded by the sidewall liner.
LEE teaches the surface layer is generated by a reaction of the silicon nitride with oxygen ions to form silicon dioxide (36 → 36A, FIG. 3B → 3C);
forming a metal silicide (middle layer of 37) and a seed layer (bottom layer of 37) at the bottom of the trench, the metal silicide is located between the seed layer and the second epitaxial layer (35); and
forming a conductive plug (top most layer of 37) in the trench, wherein the conductive plug is surrounded by the sidewall liner (36A/36B).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of for the purpose of removing the impurities and defects within the gate insulation layer as taught by LEE, [0068].
Re claim 22, in the combination, LEE teaches the method according to claim 21, wherein a material of the metal silicide is tungsten silicide (middle tungsten silicide layer 37, [0074]), a material of the seed layer is fluorine-free tungsten (FFW) (tungsten layer 37, [0074]), and a material of the conductive plug is tungsten (top most tungsten layer 37).
LEE differs from the invention by not showing wherein a material of the metal silicide is titanium silicide.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the above said teaching because titanium is a very well-known material for forming diffusion layer since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416.
Re claim 23, in the combination, CHANG teaches the method according to claim 21, wherein the conductive plug (170/171, Fig 6) is formed between the first and second gate electrodes (121/123), and the conductive plug serves as a source/drain (130, [0012]) contact of a transistor.
Re claim 24, in the combination, LEE teaches the method according to claim 21, wherein a step of forming the sidewall liner on the sidewall of the trench comprises performing a thermal plasma oxidation (FIG. 3C, [0069]).
Re claim 25, in the combination, CHANG teaches the method according to claim 24, wherein the thermal plasma oxidation comprises introducing argon gas, hydrogen ion plasma and oxygen ion plasma in a high temperature environment greater than 100 degrees Celsius to make the silicon nitride react with the oxygen ions to generate the silicon dioxide ([0066]-[0071]).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHANG/LEE in view of Chambers (Pub. No.: US 2010/0127336).
Re claim 10, CHANG/LEE teaches all the limitation of claim 9.
CHANG/LEE fails to teach the limitation of claim 10.
Chambers, FIG. 1F teaches the method according to claim 9, wherein during the hydrogen and oxygen plasma treatments, the sidewall liner comprises a surface layer and a bottom layer, the bottom layer is silicon nitride (SiNx) (bottom most line layer 1014), and the surface layer is silicon dioxide (SiO2) generated by the reaction of the silicon nitride (SiNx) with oxygen ions (1014+1040).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of improving on-state current densities as taught by Chambers, [0004].
Re claim 11, in the combination, Chambers, FIG. 1F teaches the method according to claim 10, further comprising reacting the silicon nitride of the bottom layer with oxygen ions to generate silicon dioxide (SiO2) (1014+1040).
Response to Arguments
Applicant' s arguments with respect to claim(s) 6 and 21 on the remarks filed on 12/08/2025 have been considered but are moot because the new ground of obviousness rejection rebuts the subject matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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